timestamp sync basically works

diff --git a/nxyter/source/nx_i2c_master.vhd b/nxyter/source/nx_i2c_master.vhd
index 2c74b9d6e0ba7d75a6a37a456329aa6f8525d67a..8f1b7996aee700839ae71eaa7ee6d26a92548dad 100644 (file)
--- a/nxyter/source/nx_i2c_master.vhd
+++ b/nxyter/source/nx_i2c_master.vhd
@@ -118,7 +118,10 @@ architecture Behavioral of nx_i2c_master is
 begin\r
 \r
   -- Timer\r
-  nx_i2c_timer_1: nx_i2c_timer\r
+  nx_timer_1: nx_timer\r
+    generic map (\r
+      CTR_WIDTH => 12\r
+      )\r
     port map (\r
       CLK_IN         => CLK_IN,\r
       RESET_IN       => RESET_IN,\r

diff --git a/nxyter/source/nx_i2c_readbyte.vhd b/nxyter/source/nx_i2c_readbyte.vhd
index 58a31974388241fa85733da2498a27f7f084c4b1..42857f9fe455afbe2ac17d28b7d905fe258c6489 100644 (file)
--- a/nxyter/source/nx_i2c_readbyte.vhd
+++ b/nxyter/source/nx_i2c_readbyte.vhd
@@ -68,7 +68,10 @@ architecture Behavioral of nx_i2c_readbyte is
 begin\r
 \r
   -- Timer\r
-  nx_i2c_timer_1: nx_i2c_timer\r
+  nx_timer_1: nx_timer\r
+    generic map(\r
+      CTR_WIDTH => 12\r
+      )\r
     port map (\r
       CLK_IN         => CLK_IN,\r
       RESET_IN       => RESET_IN,\r

diff --git a/nxyter/source/nx_i2c_sendbyte.vhd b/nxyter/source/nx_i2c_sendbyte.vhd
index 2044e31645cd8effbd654a0d51149bac4701b82b..88d0be9822fc6bd9429d9e5b227860f7a511507b 100644 (file)
--- a/nxyter/source/nx_i2c_sendbyte.vhd
+++ b/nxyter/source/nx_i2c_sendbyte.vhd
@@ -68,7 +68,10 @@ architecture Behavioral of nx_i2c_sendbyte is
 begin\r
 \r
   -- Timer\r
-  nx_i2c_timer_1: nx_i2c_timer\r
+  nx_timer_1: nx_timer\r
+    generic map (\r
+      CTR_WIDTH => 12\r
+      )\r
     port map (\r
       CLK_IN         => CLK_IN,\r
       RESET_IN       => RESET_IN,\r

diff --git a/nxyter/source/nx_i2c_startstop.vhd b/nxyter/source/nx_i2c_startstop.vhd
index 7b9c0fe8af3a27a0c6cf530ca9e6ea1bdac98491..82d612a9bf550885906d8f65ffe2afbddde84432 100644 (file)
--- a/nxyter/source/nx_i2c_startstop.vhd
+++ b/nxyter/source/nx_i2c_startstop.vhd
@@ -54,7 +54,10 @@ architecture Behavioral of nx_i2c_startstop is
 begin\r
 \r
   -- Timer\r
-  nx_i2c_timer_1: nx_i2c_timer\r
+  nx_timer_1: nx_timer\r
+    generic map (\r
+      CTR_WIDTH => 12\r
+      )\r
     port map (\r
       CLK_IN         => CLK_IN,\r
       RESET_IN       => RESET_IN,\r

diff --git a/nxyter/source/nx_i2c_timer.vhd b/nxyter/source/nx_timer.vhd
similarity index 82%
rename from nxyter/source/nx_i2c_timer.vhd
rename to nxyter/source/nx_timer.vhd
index 15d5ab92f4cef8ed9209b6516f02b86f0f6cdbf4..6381d986d8760de02e0f6c4b812c8da7b997c21b 100644 (file)
--- a/nxyter/source/nx_i2c_timer.vhd
+++ b/nxyter/source/nx_timer.vhd
@@ -2,23 +2,26 @@ library ieee;
 use ieee.std_logic_1164.all;\r
 use ieee.numeric_std.all;\r
 \r
-entity nx_i2c_timer is\r
+entity nx_timer is\r
+  generic (\r
+    CTR_WIDTH : integer := 12\r
+    );\r
   port(\r
     CLK_IN               : in    std_logic;\r
     RESET_IN             : in    std_logic;\r
 \r
-    TIMER_START_IN       : in unsigned(11 downto 0);\r
+    TIMER_START_IN       : in unsigned(CTR_WIDTH - 1 downto 0);\r
     TIMER_DONE_OUT       : out std_logic\r
     );\r
 end entity;\r
 \r
-architecture Behavioral of nx_i2c_timer is\r
+architecture Behavioral of nx_timer is\r
 \r
   -- Timer\r
-  signal timer_ctr       : unsigned(11 downto 0);\r
+  signal timer_ctr       : unsigned(CTR_WIDTH - 1 downto 0);\r
   signal timer_done_o    : std_logic;\r
 \r
-  signal timer_ctr_x     : unsigned(11 downto 0);\r
+  signal timer_ctr_x     : unsigned(CTR_WIDTH - 1 downto 0);\r
   signal timer_done_o_x  : std_logic;\r
 \r
   type STATES is (S_IDLE,\r

diff --git a/nxyter/source/nx_timestamp_fifo_read.vhd b/nxyter/source/nx_timestamp_fifo_read.vhd
index 250b819304db887e3536ba7a7cb1ec3c013680da..62bdf6390aa273c99b56c8d5b24bba8c8ab6eab6 100644 (file)
--- a/nxyter/source/nx_timestamp_fifo_read.vhd
+++ b/nxyter/source/nx_timestamp_fifo_read.vhd
@@ -28,38 +28,41 @@ entity nx_timestamp_fifo_read is
     SLV_NO_MORE_DATA_OUT : out std_logic;\r
     SLV_UNKNOWN_ADDR_OUT : out std_logic;\r
 \r
-    DEBUG_OUT            : out std_logic_vector(7 downto 0)\r
+    DEBUG_OUT            : out std_logic_vector(15 downto 0)\r
     );\r
 end entity;\r
 \r
 architecture Behavioral of nx_timestamp_fifo_read is\r
 \r
-\r
   -- FIFO Input Handler\r
-  signal nx_timestamp_n      : std_logic_vector(7 downto 0);\r
-  signal fifo_skip_write_x   : std_logic;\r
-  signal fifo_skip_write_l   : std_logic;\r
-  signal fifo_skip_write     : std_logic;\r
-  signal fifo_full_i         : std_logic;\r
-  signal fifo_write_enable_o : std_logic;\r
-  signal fifo_write_skip_ctr : unsigned(7 downto 0);\r
-  signal nx_frame_clock_o    : std_logic;\r
-  signal frame_clock_ctr     : unsigned(1 downto 0);\r
+  signal fifo_full                : std_logic;\r
+  signal fifo_write_enable        : std_logic;\r
+  signal frame_tag_o              : std_logic;\r
+\r
+  -- FRAME_CLOCK_GENERATOR  \r
+  signal frame_clock_ctr          : unsigned(1 downto 0);\r
+  signal nx_frame_clock_o         : std_logic;\r
+\r
+  signal frame_clock_ctr_inc_x    : std_logic;\r
+  signal frame_clock_ctr_inc_l    : std_logic;\r
+  signal frame_clock_ctr_inc      : std_logic;\r
 \r
   -- FIFO Output Handler\r
-  signal fifo_empty_i        : std_logic;       \r
-  signal fifo_empty_x        : std_logic;       \r
-  signal fifo_empty          : std_logic;       \r
-  signal fifo_full_x         : std_logic;\r
-  signal fifo_full           : std_logic;\r
-  signal fifo_out            : std_logic_vector(31 downto 0);\r
-  signal fifo_read_enable_o  : std_logic;\r
-  signal fifo_skip_write_o   : std_logic;\r
-  signal fifo_skip_write_r   : std_logic;\r
-  signal fifo_skip_write_s   : std_logic;\r
-\r
-  -- SYNC NX Frame Process\r
+  signal fifo_out                 : std_logic_vector(35 downto 0);\r
+  signal fifo_empty               : std_logic;\r
+  signal fifo_read_enable_x       : std_logic;\r
+  signal fifo_read_enable         : std_logic;\r
+  signal register_fifo_data_x     : std_logic_vector(31 downto 0);\r
+  signal register_fifo_data       : std_logic_vector(31 downto 0);\r
+  signal fifo_new_data_x          : std_logic;\r
+  signal fifo_new_data            : std_logic;\r
+\r
+  signal frame_clock_ctr_inc_r    : std_logic;\r
+  signal frame_clock_ctr_inc_s    : std_logic;\r
+  signal frame_clock_ctr_inc_o    : std_logic;\r
   \r
+  -- Sync NX Frame Process\r
+\r
   -- RS Sync FlipFlop\r
   signal nx_frame_synced_o     : std_logic;\r
   signal rs_sync_set           : std_logic;\r
@@ -70,74 +73,67 @@ architecture Behavioral of nx_timestamp_fifo_read is
   signal frame_sync_wait_ctr   : unsigned (7 downto 0);\r
   \r
   -- Slave Bus\r
-  signal register_fifo_data    : std_logic_vector(31 downto 0);\r
-  signal register_fifo_status  : std_logic_vector(31 downto 0);\r
   signal slv_data_out_o        : std_logic_vector(31 downto 0);\r
   signal slv_no_more_data_o    : std_logic;\r
   signal slv_unknown_addr_o    : std_logic;\r
   signal slv_ack_o             : std_logic;\r
-  signal fifo_write_enable_x   : std_logic;\r
-  signal fifo_write_enable     : std_logic;\r
-  signal fifo_read_enable_x    : std_logic;\r
-  signal fifo_read_enable      : std_logic;\r
-  signal fifo_write_skip_ctr_x : std_logic_vector(7 downto 0);\r
-  signal fifo_write_skip_ctr_o : std_logic_vector(7 downto 0);\r
-  \r
-  type STATES is (IDLE,\r
-                  READ_FIFO\r
+  signal register_fifo_status  : std_logic_vector(31 downto 0);\r
+\r
+  type STATES is (S_IDLE,\r
+                  S_READ_FIFO\r
                   );\r
-  signal STATE : STATES;\r
+  signal STATE, NEXT_STATE : STATES;\r
 \r
-  type STATES_SYNC is (SYNC_CHECK,\r
-                       SYNC_RESYNC,\r
-                       SYNC_WAIT\r
+  type STATES_SYNC is (S_SYNC_CHECK,\r
+                       S_SYNC_RESYNC,\r
+                       S_SYNC_WAIT\r
                        );\r
   signal STATE_SYNC : STATES_SYNC;\r
-  \r
-begin\r
 \r
-  DEBUG_OUT(0) <= fifo_write_enable_o;\r
-  DEBUG_OUT(1) <= fifo_full;\r
-  DEBUG_OUT(2) <= fifo_read_enable_o;\r
-  DEBUG_OUT(3) <= fifo_empty;\r
 \r
-  DEBUG_OUT(4) <= nx_frame_synced_o;\r
-  DEBUG_OUT(5) <= fifo_skip_write_o;\r
-  DEBUG_OUT(6) <= nx_frame_clock_o;\r
-  DEBUG_OUT(7) <= CLK_IN;\r
+begin\r
+  \r
+  DEBUG_OUT(0)           <= CLK_IN;\r
+  \r
+  DEBUG_OUT(1)           <= NX_TIMESTAMP_CLK_IN; -- fifo_write_enable;\r
+--    DEBUG_OUT(2)           <= fifo_full;\r
+--    DEBUG_OUT(3)           <= fifo_write_enable;\r
+--    DEBUG_OUT(4)           <= fifo_empty;\r
+--    DEBUG_OUT(5)           <= fifo_read_enable;\r
+  \r
+ -- DEBUG_OUT(2)           <= NX_FRAME_CLOCK_OUT;\r
+ -- DEBUG_OUT(3)           <= ;\r
+ -- DEBUG_OUT(5)           <= ;\r
+ -- DEBUG_OUT(6)           <= ;\r
+ -- DEBUG_OUT(7)           <= '0';\r
+  DEBUG_OUT(6)             <= NX_FRAME_CLOCK_OUT;\r
+  DEBUG_OUT(7)             <= frame_clock_ctr_inc;\r
+--   DEBUG_OUT(15 downto 8) <= NX_TIMESTAMP_OUT(7 downto 0);\r
+  --DEBUG_OUT(15 downto 8) <= NX_TIMESTAMP_IN(7 downto 0);\r
+  DEBUG_OUT(9 downto 8) <= frame_clock_ctr;\r
   \r
   -----------------------------------------------------------------------------\r
   -- Dual Clock FIFO 8bit to 32bit\r
   -----------------------------------------------------------------------------\r
 \r
-  -- First Decode\r
-  --  Gray_Decoder_1: Gray_Decoder\r
-  --   generic map (\r
-  --     WIDTH => 8)\r
-  --   port map (\r
-  --     CLK_IN     => NX_TIMESTAMP_CLK_IN,\r
-  --     RESET_IN   => RESET_IN,\r
-  --     GRAY_IN    => NX_TIMESTAMP_IN,\r
-  --     BINARY_OUT => nx_timestamp_n\r
-  --     );\r
-  nx_timestamp_n <= NX_TIMESTAMP_IN;\r
-  \r
-  \r
-  -- Second send data to FIFO\r
-  fifo_dc_8to32_1: fifo_dc_8to32\r
+  -- Send data to FIFO\r
+  fifo_dc_9to36_1: fifo_dc_9to36\r
     port map (\r
-      Data    => nx_timestamp_n,\r
-      WrClock => NX_TIMESTAMP_CLK_IN,\r
-      RdClock => CLK_IN,\r
-      WrEn    => fifo_write_enable_o,\r
-      RdEn    => fifo_read_enable_o,\r
-      Reset   => RESET_IN,\r
-      RPReset => RESET_IN,\r
-      Q       => fifo_out,\r
-      Empty   => fifo_empty_i,\r
-      Full    => fifo_full_i\r
+      Data(7 downto 0) => NX_TIMESTAMP_IN,\r
+      Data(8)          => frame_tag_o,\r
+      WrClock          => NX_TIMESTAMP_CLK_IN,\r
+      RdClock          => CLK_IN,\r
+      WrEn             => fifo_write_enable,\r
+      RdEn             => fifo_read_enable,\r
+      Reset            => RESET_IN,\r
+      RPReset          => RESET_IN,\r
+      Q                => fifo_out,\r
+      Empty            => fifo_empty,\r
+      Full             => fifo_full\r
       );\r
 \r
+  -- Write only in case FIFO is not full\r
+  fifo_write_enable <= '0' when fifo_full = '1' else '1';\r
   \r
   -----------------------------------------------------------------------------\r
   -- FIFO Input Handler\r
@@ -149,93 +145,137 @@ begin
   begin\r
     if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
       if( RESET_IN = '1' ) then\r
-        fifo_skip_write_x  <= '0';\r
-        fifo_skip_write_l  <= '0';\r
+        frame_clock_ctr_inc_x  <= '0';\r
+        frame_clock_ctr_inc_l  <= '0';\r
       else\r
-        fifo_skip_write_x <= fifo_skip_write_o;\r
-        fifo_skip_write_l <= fifo_skip_write_x;\r
+        frame_clock_ctr_inc_x <= frame_clock_ctr_inc_o;\r
+        frame_clock_ctr_inc_l <= frame_clock_ctr_inc_x;   \r
       end if;\r
     end if;\r
   end process PROC_FIFO_IN_HANDLER_SYNC;\r
 \r
-  -- Signal fifo_skip_write might 2 clocks long --> I need 1\r
+  -- Signal frame_tag_ctr_inc_l might be 2 clocks long --> I need 1\r
   level_to_pulse_1: level_to_pulse\r
     port map (\r
       CLK_IN    => NX_TIMESTAMP_CLK_IN,\r
       RESET_IN  => RESET_IN,\r
-      LEVEL_IN  => fifo_skip_write_l,\r
-      PULSE_OUT => fifo_skip_write\r
+      LEVEL_IN  => frame_clock_ctr_inc_l,\r
+      PULSE_OUT => frame_clock_ctr_inc\r
       );\r
-  \r
-  -- Write only in case FIFO is not full, skip one write cycle in case\r
-  -- fifo_skip_write is true (needed by the synchronization process\r
-  -- to genrate the NX Frame Clock which I don't have, grrrr) \r
-  PROC_FIFO_IN_HANDLER: process(NX_TIMESTAMP_CLK_IN)\r
+\r
+  PROC_FRAME_CLOCK_GENERATOR: process(NX_TIMESTAMP_CLK_IN)\r
   begin\r
     if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
       if( RESET_IN = '1' ) then\r
-        fifo_write_enable_o <= '0';\r
-        frame_clock_ctr     <= (others => '0');\r
-        fifo_write_skip_ctr <= (others => '0'); \r
+        frame_clock_ctr   <= (others => '0');\r
+        nx_frame_clock_o  <= '0';\r
+        frame_tag_o       <= '1';\r
       else\r
-        fifo_write_enable_o <= '1';\r
-\r
-        if (fifo_full_i = '1') then\r
-          fifo_write_enable_o <= '0';\r
-        elsif (fifo_skip_write = '1') then\r
-          fifo_write_skip_ctr <= fifo_write_skip_ctr + 1;\r
-          fifo_write_enable_o <= '0';\r
-        end if;\r
+        case frame_clock_ctr is\r
+\r
+          when "00" =>\r
+            nx_frame_clock_o  <= '1';\r
+            frame_tag_o       <= '1';\r
+          when "01" =>\r
+            nx_frame_clock_o  <= '1';\r
+            frame_tag_o       <= '0';\r
+          when "10" =>\r
+            nx_frame_clock_o  <= '0';\r
+            frame_tag_o       <= '0';\r
+          when "11" =>\r
+            nx_frame_clock_o  <= '0';\r
+            frame_tag_o       <= '0';\r
+          when others => null;\r
 \r
-        if (frame_clock_ctr < 2) then\r
-          nx_frame_clock_o <= '1';\r
-        else\r
-          nx_frame_clock_o <= '0';\r
-        end if;\r
+        end case;\r
 \r
-        if (fifo_skip_write = '1') then\r
-          frame_clock_ctr <= (others => '0');\r
+        if (frame_clock_ctr_inc = '1') then\r
+          frame_clock_ctr <= frame_clock_ctr + 2;\r
         else\r
           frame_clock_ctr <= frame_clock_ctr + 1;\r
         end if;\r
-        \r
+\r
       end if;\r
     end if;\r
-  end process PROC_FIFO_IN_HANDLER; \r
-\r
-  NX_FRAME_CLOCK_OUT <= nx_frame_clock_o;\r
+  end process PROC_FRAME_CLOCK_GENERATOR;\r
   \r
   -----------------------------------------------------------------------------\r
   -- FIFO Output Handler and Sync FIFO\r
   -----------------------------------------------------------------------------\r
 \r
-  -- Read only in case FIFO is not empty\r
-  PROC_FIFO_READ: process(CLK_IN)\r
-  begin\r
+  PROC_FIFO_READ_TRANSFER: process (CLK_IN)\r
+  begin \r
     if( rising_edge(CLK_IN) ) then\r
-      if( RESET_IN = '1' ) then\r
-        fifo_read_enable_o <= '0';\r
-        STATE <= IDLE;\r
+      if (RESET_IN = '1') then\r
+        fifo_read_enable    <= '0';\r
+        fifo_new_data       <= '0';\r
+        register_fifo_data  <= (others => '0');\r
+        STATE               <= S_IDLE;\r
+        register_fifo_data  <= (others => '0');\r
       else\r
-        fifo_read_enable_o <= '0';\r
-        case STATE is\r
-\r
-          when IDLE =>\r
-            if (fifo_empty_i = '1') then\r
-              STATE <= IDLE;\r
-            else\r
-              fifo_read_enable_o <= '1';\r
-              STATE <= READ_FIFO;\r
-            end if;\r
-            \r
-          when READ_FIFO =>\r
-            register_fifo_data <= fifo_out;\r
-            STATE <= IDLE;\r
-            \r
-          when others => null;\r
-        end case;\r
+        fifo_read_enable    <= fifo_read_enable_x;\r
+        fifo_new_data       <= fifo_new_data_x;\r
+        register_fifo_data  <= register_fifo_data_x;\r
+        STATE               <= NEXT_STATE;\r
       end if;\r
     end if;\r
+  end process PROC_FIFO_READ_TRANSFER;\r
+\r
+  -- Read only in case FIFO is not empty\r
+  PROC_FIFO_READ: process(STATE)\r
+\r
+    variable frame_tag : std_logic_vector(3 downto 0);\r
+\r
+  begin\r
+    fifo_read_enable_x   <= '0';\r
+    fifo_new_data_x      <= '0';\r
+    register_fifo_data_x <= register_fifo_data;\r
+\r
+    frame_tag := fifo_out(35) & fifo_out(26) &\r
+                 fifo_out(17) & fifo_out(8);\r
+    \r
+    case STATE is\r
+\r
+      when S_IDLE =>\r
+        if (fifo_empty = '1') then\r
+          NEXT_STATE <= S_IDLE;\r
+        else\r
+          fifo_read_enable_x <= '1';\r
+          NEXT_STATE         <= S_READ_FIFO;\r
+        end if;\r
+        \r
+      when S_READ_FIFO =>\r
+        fifo_new_data_x  <= '1';\r
+        case frame_tag is\r
+          when "1000" =>\r
+            register_fifo_data_x(31 downto 24) <= fifo_out(34 downto 27);\r
+            register_fifo_data_x(23 downto 16) <= fifo_out(25 downto 18);\r
+            register_fifo_data_x(15 downto 8)  <= fifo_out(16 downto  9);\r
+            register_fifo_data_x(7 downto 0)   <= fifo_out(7  downto  0);\r
+          when "0100" => \r
+            register_fifo_data_x(31 downto 24) <= fifo_out( 7 downto  0);\r
+            register_fifo_data_x(23 downto 16) <= fifo_out(34 downto 27);\r
+            register_fifo_data_x(15 downto 8)  <= fifo_out(25 downto 18);\r
+            register_fifo_data_x(7 downto 0)   <= fifo_out(16 downto  9);\r
+          when "0010" => \r
+            register_fifo_data_x(31 downto 24) <= fifo_out(16 downto  9);\r
+            register_fifo_data_x(23 downto 16) <= fifo_out(7  downto  0);\r
+            register_fifo_data_x(15 downto 8)  <= fifo_out(34 downto 27);\r
+            register_fifo_data_x(7 downto 0)   <= fifo_out(25 downto 18);\r
+          when "0001" => \r
+            register_fifo_data_x(31 downto 24) <= fifo_out(25  downto 18);\r
+            register_fifo_data_x(23 downto 16) <= fifo_out(16  downto  9);\r
+            register_fifo_data_x(15 downto 8)  <= fifo_out(7   downto  0);\r
+            register_fifo_data_x(7 downto 0)   <= fifo_out(34  downto 27);\r
+\r
+          when others =>\r
+            register_fifo_data_x <= (others => '1');\r
+            fifo_new_data_x      <= '0';\r
+        end case;\r
+        NEXT_STATE <= S_IDLE;\r
+        \r
+      when others => null;\r
+    end case;\r
   end process PROC_FIFO_READ;\r
   \r
 \r
@@ -251,57 +291,65 @@ begin
     end if;\r
   end process PROC_RS_FRAME_SYNCED;\r
 \r
-  -- Sync to NX NO_DATA FRAME \r
+  -- Sync to NX_DATA FRAME \r
   PROC_SYNC_TO_NO_DATA: process(CLK_IN)\r
+\r
+    variable fifo_tag_given : std_logic_vector(3 downto 0);\r
+  \r
   begin\r
+    fifo_tag_given := fifo_out(35) & fifo_out(26) &\r
+                      fifo_out(17) & fifo_out(8);\r
+\r
     if( rising_edge(CLK_IN) ) then\r
       if( RESET_IN = '1' ) then\r
-        rs_sync_set          <= '0';\r
-        rs_sync_reset        <= '1';\r
-        nx_frame_resync_ctr  <= (others => '0');\r
-        frame_sync_wait_ctr  <= (others => '0');\r
-        fifo_skip_write_s    <= '0';\r
-        STATE_SYNC           <= SYNC_CHECK;\r
+        rs_sync_set           <= '0';\r
+        rs_sync_reset         <= '1';\r
+        nx_frame_resync_ctr   <= (others => '0');\r
+        frame_sync_wait_ctr   <= (others => '0');\r
+        frame_clock_ctr_inc_s <= '0';\r
+        STATE_SYNC            <= S_SYNC_CHECK;\r
       else\r
-        rs_sync_set       <= '0';\r
-        rs_sync_reset     <= '0';\r
-        fifo_skip_write_s <= '0';\r
+        rs_sync_set           <= '0';\r
+        rs_sync_reset         <= '0';\r
+        frame_clock_ctr_inc_s <= '0';\r
+\r
+        DEBUG_OUT(5 downto 2) <= fifo_tag_given;\r
         \r
         case STATE_SYNC is\r
 \r
-          when SYNC_CHECK =>\r
-            case fifo_out is\r
+          when S_SYNC_CHECK =>\r
+            case register_fifo_data is\r
               when x"7f7f7f06" =>\r
                 rs_sync_set <= '1';\r
-                STATE_SYNC  <= SYNC_CHECK;\r
+                STATE_SYNC  <= S_SYNC_CHECK;\r
 \r
               when x"067f7f7f" =>\r
-                STATE_SYNC <= SYNC_RESYNC;\r
+                STATE_SYNC <= S_SYNC_RESYNC;\r
 \r
               when x"7f067f7f" =>\r
-                STATE_SYNC <= SYNC_RESYNC;\r
+                STATE_SYNC <= S_SYNC_RESYNC;\r
                 \r
               when x"7f7f067f" =>\r
-                STATE_SYNC <= SYNC_RESYNC;\r
+                STATE_SYNC <= S_SYNC_RESYNC;\r
 \r
               when others =>\r
-                STATE_SYNC <= SYNC_CHECK;\r
+                STATE_SYNC <= S_SYNC_CHECK;\r
                 \r
             end case;\r
 \r
-          when SYNC_RESYNC =>\r
-            rs_sync_reset     <= '1';\r
-            fifo_skip_write_s <= '1';\r
-            nx_frame_resync_ctr <= nx_frame_resync_ctr + 1;\r
-            frame_sync_wait_ctr <= x"ff";\r
-            STATE_SYNC <= SYNC_WAIT;\r
+          when S_SYNC_RESYNC =>\r
+            rs_sync_reset         <= '1';\r
+            frame_clock_ctr_inc_s <= '1';\r
+            nx_frame_resync_ctr   <= nx_frame_resync_ctr + 1;\r
+            frame_sync_wait_ctr   <= x"ff";\r
+            STATE_SYNC            <= S_SYNC_WAIT;\r
 \r
-          when SYNC_WAIT =>\r
+          when S_SYNC_WAIT =>\r
             if (frame_sync_wait_ctr > 0) then\r
               frame_sync_wait_ctr <= frame_sync_wait_ctr -1;\r
-              STATE_SYNC <= SYNC_WAIT;\r
+              STATE_SYNC          <= S_SYNC_WAIT;\r
             else\r
-              STATE_SYNC <= SYNC_CHECK;\r
+              STATE_SYNC          <= S_SYNC_CHECK;\r
             end if;\r
 \r
         end case;\r
@@ -311,50 +359,51 @@ begin
   end process PROC_SYNC_TO_NO_DATA;\r
 \r
   NX_FRAME_SYNC_OUT <= nx_frame_synced_o;\r
-  NX_TIMESTAMP_OUT  <= register_fifo_data;\r
-\r
--------------------------------------------------------------------------------\r
--- TRBNet Slave Bus\r
--------------------------------------------------------------------------------\r
-\r
-  -- Cross ClockDomain NX_TIMESTAMP_CLK_IN --> CLK_IN, for simplicity just\r
-  -- cross all signals, even the CLK_IN ones\r
-  PROC_SYNC_FIFO_SIGNALS: process(CLK_IN)\r
-  begin\r
-    if( rising_edge(CLK_IN) ) then\r
-      if( RESET_IN = '1' ) then\r
-        fifo_empty_x          <= '0';\r
-        fifo_empty            <= '0';\r
-\r
-        fifo_full_x           <= '0';\r
-        fifo_full             <= '0';\r
-\r
-        fifo_write_enable_x   <= '0';\r
-        fifo_write_enable     <= '0';\r
-        \r
-        fifo_read_enable_x    <= '0';\r
-        fifo_read_enable      <= '0';\r
 \r
-        fifo_write_skip_ctr_x <= (others => '0');\r
-        fifo_write_skip_ctr_o <= (others => '0');\r
-      else\r
-        fifo_empty_x        <= fifo_empty_i;\r
-        fifo_empty          <= fifo_empty_x;\r
-\r
-        fifo_full_x         <= fifo_full_i;\r
-        fifo_full           <= fifo_full_x;\r
-\r
-        fifo_write_enable_x <= fifo_write_enable_o;\r
-        fifo_write_enable   <= fifo_write_enable_x;\r
-\r
-        fifo_read_enable_x  <= fifo_read_enable_o;\r
-        fifo_read_enable    <= fifo_read_enable_x;\r
-\r
-        fifo_write_skip_ctr_x <= fifo_write_skip_ctr;\r
-        fifo_write_skip_ctr_o <= fifo_write_skip_ctr_x;\r
-      end if;\r
-    end if;\r
-  end process PROC_SYNC_FIFO_SIGNALS;\r
+-- \r
+-- -------------------------------------------------------------------------------\r
+-- -- TRBNet Slave Bus\r
+-- -------------------------------------------------------------------------------\r
+-- \r
+--   -- Cross ClockDomain NX_TIMESTAMP_CLK_IN --> CLK_IN, for simplicity just\r
+--   -- cross all signals, even the CLK_IN ones\r
+-- --   PROC_SYNC_FIFO_SIGNALS: process(CLK_IN)\r
+-- --   begin\r
+-- --     if( rising_edge(CLK_IN) ) then\r
+-- --       if( RESET_IN = '1' ) then\r
+-- --         fifo_empty_x          <= '0';\r
+-- --         fifo_empty            <= '0';\r
+-- -- \r
+-- --         fifo_full_x           <= '0';\r
+-- --         fifo_full             <= '0';\r
+-- -- \r
+-- --         fifo_write_enable_x   <= '0';\r
+-- --         fifo_write_enable     <= '0';\r
+-- --         \r
+-- --         fifo_read_enable_x    <= '0';\r
+-- --         fifo_read_enable      <= '0';\r
+-- -- \r
+-- --         fifo_write_skip_ctr_x <= (others => '0');\r
+-- --         fifo_write_skip_ctr_o <= (others => '0');\r
+-- --       else\r
+-- --         fifo_empty_x        <= fifo_empty_i;\r
+-- --         fifo_empty          <= fifo_empty_x;\r
+-- -- \r
+-- --         fifo_full_x         <= fifo_full_i;\r
+-- --         fifo_full           <= fifo_full_x;\r
+-- -- \r
+-- --         fifo_write_enable_x <= fifo_write_enable;\r
+-- --         fifo_write_enable   <= fifo_write_enable_x;\r
+-- -- \r
+-- --         fifo_read_enable_x  <= fifo_read_enable_o;\r
+-- --         fifo_read_enable    <= fifo_read_enable_x;\r
+-- -- \r
+-- --         fifo_write_skip_ctr_x <= fifo_write_skip_ctr;\r
+-- --         fifo_write_skip_ctr_o <= fifo_write_skip_ctr_x;\r
+-- --       end if;\r
+-- --     end if;\r
+-- --   end process PROC_SYNC_FIFO_SIGNALS;\r
+-- \r
 \r
   register_fifo_status(0)            <= fifo_write_enable;\r
   register_fifo_status(1)            <= fifo_full;\r
@@ -362,7 +411,7 @@ begin
   register_fifo_status(4)            <= fifo_read_enable;\r
   register_fifo_status(5)            <= fifo_empty;\r
   register_fifo_status(7 downto 6)   <= (others => '0');\r
-  register_fifo_status(15 downto 8)  <= fifo_write_skip_ctr_o;\r
+  register_fifo_status(15 downto 8)  <= (others => '0');-- fifo_write_skip_ctr;\r
   register_fifo_status(23 downto 16) <= nx_frame_resync_ctr;\r
   register_fifo_status(30 downto 24) <= (others => '0');\r
   register_fifo_status(31)           <= nx_frame_synced_o;\r
@@ -373,31 +422,31 @@ begin
   begin\r
     if( rising_edge(CLK_IN) ) then\r
       if( RESET_IN = '1' ) then\r
-        slv_data_out_o     <= (others => '0');\r
-        slv_ack_o          <= '0';\r
-        slv_unknown_addr_o <= '0';\r
-        slv_no_more_data_o <= '0';\r
-        fifo_skip_write_r  <= '0';\r
+        slv_data_out_o         <= (others => '0');\r
+        slv_ack_o              <= '0';\r
+        slv_unknown_addr_o     <= '0';\r
+        slv_no_more_data_o     <= '0';\r
+        frame_clock_ctr_inc_r  <= '0';\r
       else\r
-        slv_data_out_o     <= (others => '0');\r
-        slv_ack_o          <= '1';\r
-        slv_unknown_addr_o <= '0';\r
-        slv_no_more_data_o <= '0';\r
-        fifo_skip_write_r  <= '0';\r
+        slv_data_out_o         <= (others => '0');\r
+        slv_ack_o              <= '1';\r
+        slv_unknown_addr_o     <= '0';\r
+        slv_no_more_data_o     <= '0';\r
+        frame_clock_ctr_inc_r  <= '0';\r
 \r
         if (SLV_READ_IN  = '1') then\r
           case SLV_ADDR_IN is\r
-            when x"0000" => slv_data_out_o <= register_fifo_data;\r
-            when x"0001" => slv_data_out_o <= register_fifo_status;\r
+            when x"0000" => slv_data_out_o     <= register_fifo_data;\r
+            when x"0001" => slv_data_out_o     <= register_fifo_status;\r
             when others  => slv_unknown_addr_o <= '1';\r
-                            slv_ack_o <= '0';          \r
+                            slv_ack_o          <= '0';          \r
           end case;\r
           \r
         elsif (SLV_WRITE_IN  = '1') then\r
           case SLV_ADDR_IN is\r
-            when x"0001" => fifo_skip_write_r <= '1';\r
-            when others  => slv_unknown_addr_o <= '1';              \r
-                            slv_ack_o <= '0';\r
+            when x"0001" => frame_clock_ctr_inc_r <= '1';\r
+            when others  => slv_unknown_addr_o    <= '1';              \r
+                            slv_ack_o             <= '0';\r
           end case;                \r
         else\r
           slv_ack_o <= '0';\r
@@ -406,13 +455,15 @@ begin
     end if;\r
   end process PROC_FIFO_REGISTERS;\r
 \r
-  fifo_skip_write_o <= fifo_skip_write_r or fifo_skip_write_s;\r
+  frame_clock_ctr_inc_o <= frame_clock_ctr_inc_r or frame_clock_ctr_inc_s;\r
   \r
--- Output Signals\r
+  -- Output Signals\r
   SLV_DATA_OUT         <= slv_data_out_o;    \r
   SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
   SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
   SLV_ACK_OUT          <= slv_ack_o;\r
 \r
+  NX_FRAME_CLOCK_OUT   <= nx_frame_clock_o;\r
+  NX_TIMESTAMP_OUT     <= register_fifo_data;\r
 \r
 end Behavioral;\r

diff --git a/nxyter/source/nxyter.vhd b/nxyter/source/nxyter.vhd
index 60f07c28b41a96163eca638e9e1c0132fccc09ee..f87402aba92579e039f8aea73b046bdede13d8fa 100644 (file)
--- a/nxyter/source/nxyter.vhd
+++ b/nxyter/source/nxyter.vhd
@@ -97,6 +97,7 @@ architecture Behavioral of nXyter_FEE_board is
   signal spi_sdo              : std_logic;        
 
   -- FIFO Read
+  signal nx_ts_reset_o        : std_logic;
   signal nx_frame_clock_o     : std_logic;
   signal nx_frame_sync_o      : std_logic;
   
@@ -110,12 +111,15 @@ begin
 -------------------------------------------------------------------------------
 -- DEBUG
 -------------------------------------------------------------------------------
---   DEBUG_LINE_OUT(0)           <= CLK_IN;
---   DEBUG_LINE_OUT(1)           <= clk_256_o;
---   DEBUG_LINE_OUT(2)           <= NX_CLK128_IN;
+--   DEBUG_LINE_OUT(2)           <= CLK_IN;
+--   DEBUG_LINE_OUT(1)           <= NX_CLK256A_OUT;
+--   DEBUG_LINE_OUT(0)           <= NX_CLK128_IN;
 --   DEBUG_LINE_OUT(3)           <= nx_frame_clock_o;
 --   DEBUG_LINE_OUT(4)           <= nx_frame_sync_o;
---   DEBUG_LINE_OUT(7 downto 5)  <= (others => '0');
+--   DEBUG_LINE_OUT(5)           <= NX_RESET_OUT;
+--   DEBUG_LINE_OUT(7 downto 6)  <= (others => '0');
+--   
+--   DEBUG_LINE_OUT(15 downto 8) <= NX_TIMESTAMP_IN;
 --   DEBUG_LINE_OUT(15 downto 8) <= NX_TIMESTAMP_IN;
 --   DEBUG_LINE_OUT(8)            <= i2c_sda_o;
 --   DEBUG_LINE_OUT(9)            <= i2c_sda_i;
@@ -144,6 +148,9 @@ begin
       LOCK  => open
       );
 
+  NX_CLK256A_OUT     <= clk_256_o;
+  NX_TESTPULSE_OUT   <= '0';
+
   -- pll_25_1: pll_25
   --   port map (
   --     CLK   => CLK_IN,
@@ -152,10 +159,6 @@ begin
   --     );
   -- clk_256_o      <= CLK_128_IN;
 
-  NX_RESET_OUT       <= '0';
-  NX_CLK256A_OUT     <= clk_256_o;
-  NX_TESTPULSE_OUT   <= '0';
-
   -- TRBNet Bus Handler
   THE_BUS_HANDLER: trb_net16_regio_bus_handler
     generic map(
@@ -274,20 +277,22 @@ begin
 -------------------------------------------------------------------------------
   nxyter_registers_1: nxyter_registers
     port map (
-      CLK_IN               => CLK_IN,
-      RESET_IN             => RESET_IN,
-
-      SLV_READ_IN          => slv_read(0),
-      SLV_WRITE_IN         => slv_write(0),
-      SLV_DATA_OUT         => slv_data_rd(0*32+31 downto 0*32),
-      SLV_DATA_IN          => slv_data_wr(0*32+31 downto 0*32),
-      SLV_ADDR_IN          => slv_addr(0*16+15 downto 0*16),
-      SLV_ACK_OUT          => slv_ack(0),
-      SLV_NO_MORE_DATA_OUT => slv_no_more_data(0),
-      SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0),
-      I2C_SM_RESET_OUT     => i2c_sm_reset_o,
-      I2C_REG_RESET_OUT    => i2c_reg_reset_o,
-      DEBUG_OUT            => open
+      CLK_IN                 => CLK_IN,
+      RESET_IN               => RESET_IN,
+                             
+      SLV_READ_IN            => slv_read(0),
+      SLV_WRITE_IN           => slv_write(0),
+      SLV_DATA_OUT           => slv_data_rd(0*32+31 downto 0*32),
+      SLV_DATA_IN            => slv_data_wr(0*32+31 downto 0*32),
+      SLV_ADDR_IN            => slv_addr(0*16+15 downto 0*16),
+      SLV_ACK_OUT            => slv_ack(0),
+      SLV_NO_MORE_DATA_OUT   => slv_no_more_data(0),
+      SLV_UNKNOWN_ADDR_OUT   => slv_unknown_addr(0),
+      I2C_SM_RESET_OUT       => i2c_sm_reset_o,
+      I2C_REG_RESET_OUT      => i2c_reg_reset_o,
+      NX_TS_RESET_OUT        => nx_ts_reset_o,
+      -- DEBUG_OUT(7 downto 0)  => DEBUG_LINE_OUT(15 downto 8)
+      DEBUG_OUT              => open
       );
 
 -------------------------------------------------------------------------------
@@ -310,11 +315,8 @@ begin
       SLV_ACK_OUT           => slv_ack(1), 
       SLV_NO_MORE_DATA_OUT  => slv_no_more_data(1),
       SLV_UNKNOWN_ADDR_OUT  => slv_unknown_addr(1),
-      DEBUG_OUT(13 downto 0) => DEBUG_LINE_OUT(13 downto 0)
-      --DEBUG_OUT             => open
+      DEBUG_OUT             => open
       );
-  DEBUG_LINE_OUT(14) <= I2C_SDA_INOUT;
-  DEBUG_LINE_OUT(15) <= I2C_SCL_INOUT;
   
 -------------------------------------------------------------------------------
 -- nXyter TimeStamp Read
@@ -340,10 +342,10 @@ begin
       SLV_NO_MORE_DATA_OUT => slv_no_more_data(2),
       SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2),
 
---      DEBUG_OUT           => DEBUG_LINE_OUT(7 downto 0)
-      DEBUG_OUT           => open
+      DEBUG_OUT            => DEBUG_LINE_OUT
+      -- DEBUG_OUT           => open
       );
-
+   
 -------------------------------------------------------------------------------
 -- Data Buffer FIFO
 -------------------------------------------------------------------------------
@@ -370,6 +372,7 @@ begin
 -------------------------------------------------------------------------------
 -- nXyter Signals
 -------------------------------------------------------------------------------
+  NX_RESET_OUT      <= not nx_ts_reset_o;
   
 -------------------------------------------------------------------------------
 -- I2C Signals
@@ -377,7 +380,7 @@ begin
 
   I2C_SM_RESET_OUT  <= not i2c_sm_reset_o;
   I2C_REG_RESET_OUT <= not i2c_reg_reset_o;
-
+     
 -------------------------------------------------------------------------------
 -- END
 -------------------------------------------------------------------------------

diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd
index 5a56b94d4c32c5a31f82d3491780f444235f4645..e06c8245485b2ec2cb8d3605f837fb310793d179 100644 (file)
--- a/nxyter/source/nxyter_components.vhd
+++ b/nxyter/source/nxyter_components.vhd
@@ -78,7 +78,10 @@ component nx_i2c_master
     );
 end component;
 
-component nx_i2c_timer
+component nx_timer
+  generic (
+    CTR_WIDTH : integer
+    );
   port (
     CLK_IN         : in  std_logic;
     RESET_IN       : in  std_logic;
@@ -153,10 +156,26 @@ component nxyter_registers
     SLV_UNKNOWN_ADDR_OUT : out std_logic;
     I2C_SM_RESET_OUT     : out std_logic;
     I2C_REG_RESET_OUT    : out std_logic;
+    NX_TS_RESET_OUT      : out std_logic;
     DEBUG_OUT            : out std_logic_vector(15 downto 0)
     );
 end component;
 
+component fifo_dc_9to36
+  port (
+    Data    : in  std_logic_vector(8 downto 0);
+    WrClock : in  std_logic;
+    RdClock : in  std_logic;
+    WrEn    : in  std_logic;
+    RdEn    : in  std_logic;
+    Reset   : in  std_logic;
+    RPReset : in  std_logic;
+    Q       : out std_logic_vector(35 downto 0);
+    Empty   : out std_logic;
+    Full    : out std_logic
+    );
+end component;
+
 component fifo_dc_8to32
   port (
     Data    : in  std_logic_vector(7 downto 0);
@@ -168,7 +187,8 @@ component fifo_dc_8to32
     RPReset : in  std_logic;
     Q       : out std_logic_vector(31 downto 0);
     Empty   : out std_logic;
-    Full    : out std_logic);
+    Full    : out std_logic
+    );
 end component;
 
 component nx_timestamp_fifo_read
@@ -191,7 +211,7 @@ component nx_timestamp_fifo_read
     SLV_NO_MORE_DATA_OUT : out std_logic;
     SLV_UNKNOWN_ADDR_OUT : out std_logic;
 
-    DEBUG_OUT            : out std_logic_vector(7 downto 0)
+    DEBUG_OUT            : out std_logic_vector(15 downto 0)
     );
 end component;
 

diff --git a/nxyter/source/nxyter_registers.vhd b/nxyter/source/nxyter_registers.vhd
index c287f7cb089b797626186236874137184345ccfd..5460142471befc32b8c17c05882bd50c2c83ff34 100644 (file)
--- a/nxyter/source/nxyter_registers.vhd
+++ b/nxyter/source/nxyter_registers.vhd
@@ -24,7 +24,8 @@ entity nxyter_registers is
     -- Signals\r
     I2C_SM_RESET_OUT     : out std_logic;\r
     I2C_REG_RESET_OUT    : out std_logic;\r
-\r
+    NX_TS_RESET_OUT      : out std_logic;\r
+    \r
     DEBUG_OUT            : out std_logic_vector(15 downto 0)\r
     );\r
 end entity;\r
@@ -40,15 +41,20 @@ architecture Behavioral of nxyter_registers is
   -- I2C Reset\r
   signal i2c_sm_reset_start  : std_logic;\r
   signal i2c_reg_reset_start : std_logic;\r
-  signal wait_timer_init_x   : unsigned(7 downto 0);\r
+  signal nx_ts_reset_start   : std_logic;\r
+  \r
   signal i2c_sm_reset_o      : std_logic;\r
   signal i2c_reg_reset_o     : std_logic;\r
-  \r
+  signal nx_ts_reset_o       : std_logic;\r
+  signal wait_timer_init_x   : unsigned(7 downto 0);\r
+\r
   type STATES is (S_IDLE,\r
                   S_I2C_SM_RESET,\r
                   S_I2C_SM_RESET_WAIT,\r
                   S_I2C_REG_RESET,\r
-                  S_I2C_REG_RESET_WAIT\r
+                  S_I2C_REG_RESET_WAIT,\r
+                  S_NX_TS_RESET,\r
+                  S_NX_TS_RESET_WAIT\r
                   );\r
   \r
   signal STATE, NEXT_STATE : STATES;\r
@@ -62,16 +68,23 @@ architecture Behavioral of nxyter_registers is
   \r
 begin\r
 \r
-  DEBUG_OUT  <= reg_data(0)(15 downto 0);\r
+  DEBUG_OUT(0) <=  I2C_SM_RESET_OUT ;\r
+  DEBUG_OUT(1) <=  I2C_REG_RESET_OUT;\r
+  DEBUG_OUT(2) <=  NX_TS_RESET_OUT;\r
 \r
-  nx_i2c_timer_1: nx_i2c_timer\r
+  DEBUG_OUT(15 downto 3) <= (others => '0');\r
+  \r
+  nx_timer_1: nx_timer\r
+    generic map (\r
+      CTR_WIDTH => 8\r
+      )\r
     port map (\r
-      CLK_IN                      => CLK_IN,\r
-      RESET_IN                    => RESET_IN,\r
-      TIMER_START_IN(7 downto 0)  => wait_timer_init,\r
-      TIMER_START_IN(11 downto 8) => open,\r
-      TIMER_DONE_OUT              => wait_timer_done\r
+      CLK_IN         => CLK_IN,\r
+      RESET_IN       => RESET_IN,\r
+      TIMER_START_IN => wait_timer_init,\r
+      TIMER_DONE_OUT => wait_timer_done\r
       );\r
+  \r
   -----------------------------------------------------------------------------\r
   -- I2C SM Reset\r
   -----------------------------------------------------------------------------\r
@@ -93,6 +106,7 @@ begin
   begin\r
     i2c_sm_reset_o     <= '0';\r
     i2c_reg_reset_o    <= '0';\r
+    nx_ts_reset_o      <= '0';\r
     wait_timer_init_x  <= (others => '0');\r
     \r
     case STATE is\r
@@ -101,6 +115,8 @@ begin
           NEXT_STATE       <= S_I2C_SM_RESET;\r
         elsif (i2c_reg_reset_start = '1') then\r
           NEXT_STATE       <= S_I2C_REG_RESET;\r
+        elsif (nx_ts_reset_start = '1') then\r
+          NEXT_STATE       <= S_NX_TS_RESET;\r
         else\r
           NEXT_STATE       <= S_IDLE;\r
         end if;\r
@@ -131,6 +147,20 @@ begin
           NEXT_STATE       <= S_IDLE;\r
         end if;\r
 \r
+      when S_NX_TS_RESET =>\r
+        nx_ts_reset_o      <= '1';\r
+        wait_timer_init_x  <= x"8f";\r
+        NEXT_STATE         <= S_NX_TS_RESET_WAIT;\r
+\r
+      when S_NX_TS_RESET_WAIT =>\r
+        nx_ts_reset_o      <= '1';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE       <= S_NX_TS_RESET_WAIT;\r
+        else\r
+          NEXT_STATE       <= S_IDLE;\r
+        end if;\r
+\r
+        \r
     end case;\r
   end process PROC_I2C_SM_RESET;\r
 \r
@@ -158,6 +188,7 @@ begin
         \r
         i2c_sm_reset_start  <= '0';\r
         i2c_reg_reset_start <= '0';\r
+        nx_ts_reset_start   <= '0';\r
       else\r
         slv_ack_o <= '1';\r
         slv_unknown_addr_o  <= '0';\r
@@ -165,12 +196,13 @@ begin
         slv_data_out_o      <= (others => '0');    \r
         i2c_sm_reset_start  <= '0';\r
         i2c_reg_reset_start <= '0';\r
+        nx_ts_reset_start   <= '0';\r
 \r
         if (SLV_WRITE_IN  = '1') then\r
           case SLV_ADDR_IN is\r
-            when x"0000" => i2c_sm_reset_start <= '1';\r
+            when x"0000" => i2c_sm_reset_start  <= '1';\r
             when x"0001" => i2c_reg_reset_start <= '1';\r
-            when x"0002" => reg_data(2) <= SLV_DATA_IN;\r
+            when x"0002" => nx_ts_reset_start   <= '1';\r
             when x"0003" => reg_data(3) <= SLV_DATA_IN;\r
             when x"0004" => reg_data(4) <= SLV_DATA_IN;\r
             when x"0005" => reg_data(5) <= SLV_DATA_IN;\r
@@ -209,5 +241,6 @@ begin
 \r
   I2C_SM_RESET_OUT     <= i2c_sm_reset_o;\r
   I2C_REG_RESET_OUT    <= i2c_reg_reset_o;\r
+  NX_TS_RESET_OUT      <= nx_ts_reset_o;\r
 \r
 end Behavioral;\r