-- VHDL netlist generated by SCUBA Diamond_1.1_Production (517)
-- Module Version: 5.4
---/d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n fifo_32to64x512_dualclock -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 36 -rwidth 72 -no_enable -pe 10 -pf 940 -e
+--/d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n fifo_32to64x512_dualclock -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 2048 -width 36 -rwidth 72 -no_enable -pe 10 -pf 1780 -e
--- Thu Feb 3 10:32:26 2011
+-- Tue May 3 10:20:07 2011
library IEEE;
use IEEE.std_logic_1164.all;
attribute CSDECODE_W : string;
attribute DATA_WIDTH_R : string;
attribute DATA_WIDTH_W : string;
- attribute FULLPOINTER1 of fifo_32to64x512_dualclock_0_1 : label is "0b011111111100001";
- attribute FULLPOINTER of fifo_32to64x512_dualclock_0_1 : label is "0b011111111110001";
- attribute AFPOINTER1 of fifo_32to64x512_dualclock_0_1 : label is "0b011101010100001";
- attribute AFPOINTER of fifo_32to64x512_dualclock_0_1 : label is "0b011101010110001";
- attribute AEPOINTER1 of fifo_32to64x512_dualclock_0_1 : label is "0b000000101111111";
- attribute AEPOINTER of fifo_32to64x512_dualclock_0_1 : label is "0b000000101011111";
- attribute RESETMODE of fifo_32to64x512_dualclock_0_1 : label is "ASYNC";
- attribute REGMODE of fifo_32to64x512_dualclock_0_1 : label is "NOREG";
- attribute CSDECODE_R of fifo_32to64x512_dualclock_0_1 : label is "0b11";
- attribute CSDECODE_W of fifo_32to64x512_dualclock_0_1 : label is "0b11";
- attribute DATA_WIDTH_R of fifo_32to64x512_dualclock_0_1 : label is "36";
- attribute DATA_WIDTH_W of fifo_32to64x512_dualclock_0_1 : label is "18";
- attribute FULLPOINTER1 of fifo_32to64x512_dualclock_1_0 : label is "0b000000000000000";
- attribute FULLPOINTER of fifo_32to64x512_dualclock_1_0 : label is "0b111111111111111";
- attribute AFPOINTER1 of fifo_32to64x512_dualclock_1_0 : label is "0b000000000000000";
- attribute AFPOINTER of fifo_32to64x512_dualclock_1_0 : label is "0b111111111111111";
- attribute AEPOINTER1 of fifo_32to64x512_dualclock_1_0 : label is "0b000000000000000";
- attribute AEPOINTER of fifo_32to64x512_dualclock_1_0 : label is "0b111111111111111";
- attribute RESETMODE of fifo_32to64x512_dualclock_1_0 : label is "ASYNC";
- attribute REGMODE of fifo_32to64x512_dualclock_1_0 : label is "NOREG";
- attribute CSDECODE_R of fifo_32to64x512_dualclock_1_0 : label is "0b11";
- attribute CSDECODE_W of fifo_32to64x512_dualclock_1_0 : label is "0b11";
- attribute DATA_WIDTH_R of fifo_32to64x512_dualclock_1_0 : label is "36";
- attribute DATA_WIDTH_W of fifo_32to64x512_dualclock_1_0 : label is "18";
+ attribute FULLPOINTER1 of fifo_32to64x512_dualclock_0_3 : label is "0b011111111110001";
+ attribute FULLPOINTER of fifo_32to64x512_dualclock_0_3 : label is "0b011111111111001";
+ attribute AFPOINTER1 of fifo_32to64x512_dualclock_0_3 : label is "0b011011110010001";
+ attribute AFPOINTER of fifo_32to64x512_dualclock_0_3 : label is "0b011011110011001";
+ attribute AEPOINTER1 of fifo_32to64x512_dualclock_0_3 : label is "0b000000010111111";
+ attribute AEPOINTER of fifo_32to64x512_dualclock_0_3 : label is "0b000000010101111";
+ attribute RESETMODE of fifo_32to64x512_dualclock_0_3 : label is "ASYNC";
+ attribute REGMODE of fifo_32to64x512_dualclock_0_3 : label is "NOREG";
+ attribute CSDECODE_R of fifo_32to64x512_dualclock_0_3 : label is "0b11";
+ attribute CSDECODE_W of fifo_32to64x512_dualclock_0_3 : label is "0b11";
+ attribute DATA_WIDTH_R of fifo_32to64x512_dualclock_0_3 : label is "18";
+ attribute DATA_WIDTH_W of fifo_32to64x512_dualclock_0_3 : label is "9";
+ attribute FULLPOINTER1 of fifo_32to64x512_dualclock_1_2 : label is "0b000000000000000";
+ attribute FULLPOINTER of fifo_32to64x512_dualclock_1_2 : label is "0b111111111111111";
+ attribute AFPOINTER1 of fifo_32to64x512_dualclock_1_2 : label is "0b000000000000000";
+ attribute AFPOINTER of fifo_32to64x512_dualclock_1_2 : label is "0b111111111111111";
+ attribute AEPOINTER1 of fifo_32to64x512_dualclock_1_2 : label is "0b000000000000000";
+ attribute AEPOINTER of fifo_32to64x512_dualclock_1_2 : label is "0b111111111111111";
+ attribute RESETMODE of fifo_32to64x512_dualclock_1_2 : label is "ASYNC";
+ attribute REGMODE of fifo_32to64x512_dualclock_1_2 : label is "NOREG";
+ attribute CSDECODE_R of fifo_32to64x512_dualclock_1_2 : label is "0b11";
+ attribute CSDECODE_W of fifo_32to64x512_dualclock_1_2 : label is "0b11";
+ attribute DATA_WIDTH_R of fifo_32to64x512_dualclock_1_2 : label is "18";
+ attribute DATA_WIDTH_W of fifo_32to64x512_dualclock_1_2 : label is "9";
+ attribute FULLPOINTER1 of fifo_32to64x512_dualclock_2_1 : label is "0b000000000000000";
+ attribute FULLPOINTER of fifo_32to64x512_dualclock_2_1 : label is "0b111111111111111";
+ attribute AFPOINTER1 of fifo_32to64x512_dualclock_2_1 : label is "0b000000000000000";
+ attribute AFPOINTER of fifo_32to64x512_dualclock_2_1 : label is "0b111111111111111";
+ attribute AEPOINTER1 of fifo_32to64x512_dualclock_2_1 : label is "0b000000000000000";
+ attribute AEPOINTER of fifo_32to64x512_dualclock_2_1 : label is "0b111111111111111";
+ attribute RESETMODE of fifo_32to64x512_dualclock_2_1 : label is "ASYNC";
+ attribute REGMODE of fifo_32to64x512_dualclock_2_1 : label is "NOREG";
+ attribute CSDECODE_R of fifo_32to64x512_dualclock_2_1 : label is "0b11";
+ attribute CSDECODE_W of fifo_32to64x512_dualclock_2_1 : label is "0b11";
+ attribute DATA_WIDTH_R of fifo_32to64x512_dualclock_2_1 : label is "18";
+ attribute DATA_WIDTH_W of fifo_32to64x512_dualclock_2_1 : label is "9";
+ attribute FULLPOINTER1 of fifo_32to64x512_dualclock_3_0 : label is "0b000000000000000";
+ attribute FULLPOINTER of fifo_32to64x512_dualclock_3_0 : label is "0b111111111111111";
+ attribute AFPOINTER1 of fifo_32to64x512_dualclock_3_0 : label is "0b000000000000000";
+ attribute AFPOINTER of fifo_32to64x512_dualclock_3_0 : label is "0b111111111111111";
+ attribute AEPOINTER1 of fifo_32to64x512_dualclock_3_0 : label is "0b000000000000000";
+ attribute AEPOINTER of fifo_32to64x512_dualclock_3_0 : label is "0b111111111111111";
+ attribute RESETMODE of fifo_32to64x512_dualclock_3_0 : label is "ASYNC";
+ attribute REGMODE of fifo_32to64x512_dualclock_3_0 : label is "NOREG";
+ attribute CSDECODE_R of fifo_32to64x512_dualclock_3_0 : label is "0b11";
+ attribute CSDECODE_W of fifo_32to64x512_dualclock_3_0 : label is "0b11";
+ attribute DATA_WIDTH_R of fifo_32to64x512_dualclock_3_0 : label is "18";
+ attribute DATA_WIDTH_W of fifo_32to64x512_dualclock_3_0 : label is "9";
attribute syn_keep : boolean;
begin
-- component instantiation statements
- fifo_32to64x512_dualclock_0_1: FIFO16KA
+ fifo_32to64x512_dualclock_0_3: FIFO16KA
-- synopsys translate_off
- generic map (FULLPOINTER1=> "011111111100001", FULLPOINTER=> "011111111110001",
- AFPOINTER1=> "011101010100001", AFPOINTER=> "011101010110001",
- AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111",
+ generic map (FULLPOINTER1=> "011111111110001", FULLPOINTER=> "011111111111001",
+ AFPOINTER1=> "011011110010001", AFPOINTER=> "011011110011001",
+ AEPOINTER1=> "000000010111111", AEPOINTER=> "000000010101111",
RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11",
- CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 18)
+ CSDECODE_W=> "11", DATA_WIDTH_R=> 18, DATA_WIDTH_W=> 9)
-- synopsys translate_on
port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
- DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
- DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
- DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
- DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
- DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
- FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi,
- EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi,
- WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset,
- RPRST=>RPReset, DO0=>Q(36), DO1=>Q(37), DO2=>Q(38),
- DO3=>Q(39), DO4=>Q(40), DO5=>Q(41), DO6=>Q(42), DO7=>Q(43),
- DO8=>Q(44), DO9=>Q(45), DO10=>Q(46), DO11=>Q(47),
- DO12=>Q(48), DO13=>Q(49), DO14=>Q(50), DO15=>Q(51),
- DO16=>Q(52), DO17=>Q(53), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2),
- DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7),
- DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11),
- DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
- DO34=>Q(16), DO35=>Q(17), EF=>Empty_int, AEF=>AlmostEmpty,
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, FULLI=>Full_int, CSW0=>scuba_vhi,
+ CSW1=>scuba_vhi, EMPTYI=>Empty_int, CSR0=>scuba_vhi,
+ CSR1=>scuba_vhi, WE=>WrEn, RE=>RdEn, CLKW=>WrClock,
+ CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, DO0=>Q(0),
+ DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), DO4=>Q(4), DO5=>Q(5),
+ DO6=>Q(6), DO7=>Q(7), DO8=>Q(8), DO9=>Q(36), DO10=>Q(37),
+ DO11=>Q(38), DO12=>Q(39), DO13=>Q(40), DO14=>Q(41),
+ DO15=>Q(42), DO16=>Q(43), DO17=>Q(44), DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open, EF=>Empty_int, AEF=>AlmostEmpty,
AFF=>AlmostFull, FF=>Full_int);
+ fifo_32to64x512_dualclock_1_2: FIFO16KA
+ -- synopsys translate_off
+ generic map (FULLPOINTER1=> "000000000000000", FULLPOINTER=> "111111111111111",
+ AFPOINTER1=> "000000000000000", AFPOINTER=> "111111111111111",
+ AEPOINTER1=> "000000000000000", AEPOINTER=> "111111111111111",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11",
+ CSDECODE_W=> "11", DATA_WIDTH_R=> 18, DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, FULLI=>Full_int,
+ CSW0=>scuba_vhi, CSW1=>scuba_vhi, EMPTYI=>Empty_int,
+ CSR0=>scuba_vhi, CSR1=>scuba_vhi, WE=>WrEn, RE=>RdEn,
+ CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, RPRST=>RPReset,
+ DO0=>Q(9), DO1=>Q(10), DO2=>Q(11), DO3=>Q(12), DO4=>Q(13),
+ DO5=>Q(14), DO6=>Q(15), DO7=>Q(16), DO8=>Q(17), DO9=>Q(45),
+ DO10=>Q(46), DO11=>Q(47), DO12=>Q(48), DO13=>Q(49),
+ DO14=>Q(50), DO15=>Q(51), DO16=>Q(52), DO17=>Q(53),
+ DO18=>open, DO19=>open, DO20=>open, DO21=>open, DO22=>open,
+ DO23=>open, DO24=>open, DO25=>open, DO26=>open, DO27=>open,
+ DO28=>open, DO29=>open, DO30=>open, DO31=>open, DO32=>open,
+ DO33=>open, DO34=>open, DO35=>open, EF=>open, AEF=>open,
+ AFF=>open, FF=>open);
+
+ fifo_32to64x512_dualclock_2_1: FIFO16KA
+ -- synopsys translate_off
+ generic map (FULLPOINTER1=> "000000000000000", FULLPOINTER=> "111111111111111",
+ AFPOINTER1=> "000000000000000", AFPOINTER=> "111111111111111",
+ AEPOINTER1=> "000000000000000", AEPOINTER=> "111111111111111",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11",
+ CSDECODE_W=> "11", DATA_WIDTH_R=> 18, DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, FULLI=>Full_int,
+ CSW0=>scuba_vhi, CSW1=>scuba_vhi, EMPTYI=>Empty_int,
+ CSR0=>scuba_vhi, CSR1=>scuba_vhi, WE=>WrEn, RE=>RdEn,
+ CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, RPRST=>RPReset,
+ DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22),
+ DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(54),
+ DO10=>Q(55), DO11=>Q(56), DO12=>Q(57), DO13=>Q(58),
+ DO14=>Q(59), DO15=>Q(60), DO16=>Q(61), DO17=>Q(62),
+ DO18=>open, DO19=>open, DO20=>open, DO21=>open, DO22=>open,
+ DO23=>open, DO24=>open, DO25=>open, DO26=>open, DO27=>open,
+ DO28=>open, DO29=>open, DO30=>open, DO31=>open, DO32=>open,
+ DO33=>open, DO34=>open, DO35=>open, EF=>open, AEF=>open,
+ AFF=>open, FF=>open);
+
scuba_vhi_inst: VHI
port map (Z=>scuba_vhi);
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
- fifo_32to64x512_dualclock_1_0: FIFO16KA
+ fifo_32to64x512_dualclock_3_0: FIFO16KA
-- synopsys translate_off
generic map (FULLPOINTER1=> "000000000000000", FULLPOINTER=> "111111111111111",
AFPOINTER1=> "000000000000000", AFPOINTER=> "111111111111111",
AEPOINTER1=> "000000000000000", AEPOINTER=> "111111111111111",
RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11",
- CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 18)
+ CSDECODE_W=> "11", DATA_WIDTH_R=> 18, DATA_WIDTH_W=> 9)
-- synopsys translate_on
- port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
- DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
- DI7=>Data(25), DI8=>Data(26), DI9=>Data(27), DI10=>Data(28),
- DI11=>Data(29), DI12=>Data(30), DI13=>Data(31),
- DI14=>Data(32), DI15=>Data(33), DI16=>Data(34),
- DI17=>Data(35), DI18=>scuba_vlo, DI19=>scuba_vlo,
- DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
- DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
- DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
- DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
- DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
- DI35=>scuba_vlo, FULLI=>Full_int, CSW0=>scuba_vhi,
- CSW1=>scuba_vhi, EMPTYI=>Empty_int, CSR0=>scuba_vhi,
- CSR1=>scuba_vhi, WE=>WrEn, RE=>RdEn, CLKW=>WrClock,
- CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, DO0=>Q(54),
- DO1=>Q(55), DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59),
- DO6=>Q(60), DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64),
- DO11=>Q(65), DO12=>Q(66), DO13=>Q(67), DO14=>Q(68),
- DO15=>Q(69), DO16=>Q(70), DO17=>Q(71), DO18=>Q(18),
- DO19=>Q(19), DO20=>Q(20), DO21=>Q(21), DO22=>Q(22),
- DO23=>Q(23), DO24=>Q(24), DO25=>Q(25), DO26=>Q(26),
- DO27=>Q(27), DO28=>Q(28), DO29=>Q(29), DO30=>Q(30),
- DO31=>Q(31), DO32=>Q(32), DO33=>Q(33), DO34=>Q(34),
- DO35=>Q(35), EF=>open, AEF=>open, AFF=>open, FF=>open);
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, FULLI=>Full_int,
+ CSW0=>scuba_vhi, CSW1=>scuba_vhi, EMPTYI=>Empty_int,
+ CSR0=>scuba_vhi, CSR1=>scuba_vhi, WE=>WrEn, RE=>RdEn,
+ CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, RPRST=>RPReset,
+ DO0=>Q(27), DO1=>Q(28), DO2=>Q(29), DO3=>Q(30), DO4=>Q(31),
+ DO5=>Q(32), DO6=>Q(33), DO7=>Q(34), DO8=>Q(35), DO9=>Q(63),
+ DO10=>Q(64), DO11=>Q(65), DO12=>Q(66), DO13=>Q(67),
+ DO14=>Q(68), DO15=>Q(69), DO16=>Q(70), DO17=>Q(71),
+ DO18=>open, DO19=>open, DO20=>open, DO21=>open, DO22=>open,
+ DO23=>open, DO24=>open, DO25=>open, DO26=>open, DO27=>open,
+ DO28=>open, DO29=>open, DO30=>open, DO31=>open, DO32=>open,
+ DO33=>open, DO34=>open, DO35=>open, EF=>open, AEF=>open,
+ AFF=>open, FF=>open);
Empty <= Empty_int;
Full <= Full_int;
signal tx_length_full : std_logic := '0';
signal tx_length_almost_empty : std_logic := '0';
signal tx_length_almost_full : std_logic := '0';
- signal tx_length_data_in : std_logic_vector(8 downto 0) := (others => '0');
- signal tx_length_data_out : std_logic_vector(8 downto 0) := (others => '0');
+ signal tx_length_data_in : std_logic_vector(15 downto 0) := (others => '0');
+ signal tx_length_data_out : std_logic_vector(15 downto 0) := (others => '0');
type copy_state_t is (IDLE, RUNNING, LAST_WORD, BUFFER_FULL_WAIT, WAIT_ONE, WAIT_BUFFER);
signal copy_state : copy_state_t;
- signal copy_length : unsigned(7 downto 0) := (others => '0');
+ signal copy_length : unsigned(11 downto 0) := (others => '0');
signal current_address : unsigned(31 downto 0) := (others => '0');
signal buf_API_READ_OUT : std_logic := '0';
type send_state_t is (SEND_IDLE, SEND_CREDIT_WAIT, SEND_START, SEND_DATA);
signal send_state : send_state_t;
- signal tx_length : unsigned(7 downto 0) := (others => '0');
+ signal tx_length : unsigned(11 downto 0) := (others => '0');
signal last_words : std_logic := '0';
signal finished : std_logic := '0';
signal finished_sys : std_logic := '0';
signal buffer_full_strobe : std_logic;
signal buffer_full : std_logic;
- signal current_burst_length : unsigned(7 downto 0);
+ signal current_burst_length : unsigned(11 downto 0);
signal buffer_space_available : std_logic;
signal buffer_space_end : unsigned(31 downto 0);
signal buffer_space_afull : unsigned(31 downto 0);
+
signal credits_sys : std_logic_vector(12 downto 0);
signal rden_dma_fifo : std_logic := '0';
begin
buffer_space_end <= unsigned(dma_start_address_i) + unsigned(dma_length_i(28 downto 0)) * to_unsigned(4,3);
- buffer_space_afull <= buffer_space_end - (unsigned(DMA_CONFIG_IN(7 downto 0)) * to_unsigned(4,24));
+ buffer_space_afull <= buffer_space_end - (unsigned(DMA_CONFIG_IN(11 downto 0)) * to_unsigned(4,20));
--Enough space for full burst
if rising_edge(CLK_IN) then
if (copy_state = IDLE or copy_state = LAST_WORD or copy_state = BUFFER_FULL_WAIT or copy_state = WAIT_BUFFER) then
if busy = '0' then
buffer_space_available <= '1';
- current_burst_length <= unsigned(DMA_CONFIG_IN(7 downto 0));
+ current_burst_length <= unsigned(DMA_CONFIG_IN(11 downto 0));
elsif current_address < buffer_space_afull then
- if unsigned(DMA_CONFIG_IN(7 downto 0)) < unsigned(credits_sys(8 downto 1)) then
- current_burst_length <= unsigned(DMA_CONFIG_IN(7 downto 0));
+ if unsigned(DMA_CONFIG_IN(11 downto 0)) < unsigned(credits_sys(11 downto 0)) then
+ current_burst_length <= unsigned(DMA_CONFIG_IN(11 downto 0));
else
- current_burst_length <= unsigned(credits_sys(8 downto 1));
+ current_burst_length <= unsigned(credits_sys(11 downto 0));
end if;
buffer_space_available <= '1';
elsif current_address < buffer_space_end then
- current_burst_length <= buffer_space_end(9 downto 2) - current_address(9 downto 2);
+ if buffer_space_end(13 downto 2) - current_address(13 downto 2) < unsigned(credits_sys(11 downto 0)) then
+ current_burst_length <= buffer_space_end(13 downto 2) - current_address(13 downto 2);
+ else
+ current_burst_length <= unsigned(credits_sys(11 downto 0));
+ end if;
buffer_space_available <= '1';
else
buffer_space_available <= '0';
when LAST_WORD =>
copy_state_bits <= "10";
- tx_data_in <= (others => '0');
+ tx_data_in <= x"888888888";
tx_wr_en <= copy_length(0); --write padding
tx_fifo_padding <= x"8";
tx_length_wr_en <= '1';
end if;
end process;
- tx_length_data_in <= last_words & std_logic_vector(copy_length-to_unsigned(1,8));
+ tx_length_data_in <= last_words & "000" & std_logic_vector(copy_length-to_unsigned(1,12));
AlmostFull => tx_almost_full --at 464 words
);
-THE_TX_LENGTH_FIFO : fifo_9x512_dualclock
+THE_TX_LENGTH_FIFO : fifo_16x512_dualclock
port map (
Data => tx_length_data_in,
WrClock => CLK_IN,
when SEND_CREDIT_WAIT =>
send_state_bits <= x"1";
- if tx_length_data_out(6 downto 0) = "0000000" then --no data
- finished <= tx_length_data_out(7);
+ if tx_length_data_out(11 downto 0) = "0000000" then --no data
+ finished <= tx_length_data_out(15);
send_state <= SEND_IDLE;
elsif (TX_CA_PH_IN(8) = '1' or (unsigned(TX_CA_PH_IN(7 downto 0)) > to_unsigned(1,8)))
- and ((TX_CA_PD_IN(12 downto 8) /= "00000") or (unsigned(TX_CA_PD_IN(7 downto 0)) >= unsigned(tx_length_data_out(7 downto 0))))
+ and ((TX_CA_PD_IN(12 downto 8) /= "00000") or (unsigned(TX_CA_PD_IN(11 downto 0)) >= unsigned(tx_length_data_out(11 downto 0))))
then
tx_st_i <= '0';
tx_end_i <= '0';
'0' & --EP
"10" & --Attr
"00" & --R
- "00" & tx_length_data_out(7 downto 0) & --Length
+ tx_length_data_out(9 downto 0) & --Length
REQUESTOR_ID_IN & --Requestor ID
x"00" & -- Tag
x"FF"; --Byte Enables
tx_rd_en <= '1'; --
tx_req_i <= '1';
- tx_length <= unsigned(tx_length_data_out(7 downto 0));
+ tx_length <= unsigned(tx_length_data_out(11 downto 0));
send_state <= SEND_START;
end if;
tx_length <= tx_length - to_unsigned(1,3);
else
tx_end_i <= '1';
- finished <= tx_length_data_out(8);
+ finished <= tx_length_data_out(15);
send_state <= SEND_IDLE;
end if;
end if;
STATUS_REG_OUT(13) <= tx_length_empty;
STATUS_REG_OUT(14) <= tx_almost_full;
STATUS_REG_OUT(15) <= tx_end_i;
-STATUS_REG_OUT(23 downto 16) <= std_logic_vector(copy_length);
-STATUS_REG_OUT(24) <= buffer_full;
-STATUS_REG_OUT(31 downto 25) <= (others => '0');
+STATUS_REG_OUT(27 downto 16) <= std_logic_vector(copy_length);
+STATUS_REG_OUT(28) <= buffer_full;
+STATUS_REG_OUT(31 downto 29) <= (others => '0');
STATUS_REG_OUT(40 downto 32) <= TX_CA_PH_IN;
STATUS_REG_OUT(53 downto 41) <= credits_sys(12 downto 0); --TX_CA_PD_IN;
STATUS_REG_OUT(62 downto 54) <= TX_CA_NPH_IN;
STATUS_REG_OUT(63) <= '0';
-STATUS_REG_OUT(95 downto 64) <= std_logic_vector(current_burst_length) & "000" & tx_length_data_in & "0" & tx_length_rd_en & tx_rd_en & tx_length_data_out;
+STATUS_REG_OUT(95 downto 64) <= std_logic_vector(current_burst_length) & x"0" & tx_length_data_out;
STATUS_REG_OUT(127 downto 96)<= std_logic_vector(current_address);
DEBUG_OUT(4) <= API_RUNNING_IN;
DEBUG_OUT(5) <= rden_dma_fifo;
DEBUG_OUT(6) <= reset_dma_fifo;
- DEBUG_OUT(7) <= tx_length_data_out(8);
+ DEBUG_OUT(7) <= tx_length_data_out(15);
DEBUG_OUT(8) <= tx_st_i;
DEBUG_OUT(9) <= tx_end_i;
DEBUG_OUT(11 downto 10)<= dma_fifo_state(1 downto 0);
jspc29 / pexor.git / commitdiff