my $lm_license_file_for_synplify = "1702\@hadeb05.gsi.de"; #"27000\@lxcad01.gsi.de";
my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
-my $lattice_path = '/d/jspc29/lattice/diamond/3.4_x64';
-my $synplify_path = '/d/jspc29/lattice/synplify/J-2014.09-SP2/';
+my $lattice_path = '/d/jspc29/lattice/diamond/3.5_x64';
+my $synplify_path = '/d/jspc29/lattice/synplify/J-2015.03-SP1/';
###################################################################################
$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
-$c=qq' $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" | grep -v -e "WARNING - edif2ngd: Unsupported property" | grep -v -e "Property MEM_INIT_FILE has no value" ' ;
+$c=qq' $lattice_path/ispfpga/bin/lin64/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" | grep -v -e "WARNING - edif2ngd: Unsupported property" | grep -v -e "Property MEM_INIT_FILE has no value" ' ;
execute($c);
-$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
execute($c);
-$c=qq'$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd" | grep -v -e "^WARNING.*has no load"';
+$c=qq'$lattice_path/ispfpga/bin/lin64/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd" | grep -v -e "^WARNING.*has no load"';
execute($c);
my $tpmap = $TOPNAME . "_map" ;
system("rm $tpmap.ncd");
-$c=qq|$lattice_path/ispfpga/bin/lin/map -hier -td_pack -retime EFFORT=6 -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -xref_sig -mp "$TOPNAME.mrp"|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/map -hier -td_pack -retime EFFORT=6 -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -xref_sig -mp "$TOPNAME.mrp"|;
execute($c);
system("rm $TOPNAME.ncd");
execute($c);
# IOR IO Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
execute($c);
-$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/ltxt2ptxt $TOPNAME.ncd|;
execute($c);
-$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
execute($c);
# TWR Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -fullname -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/trce -fullname -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
execute($c);
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -fullname -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/trce -fullname -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
execute($c);
chdir "..";
constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7
--ring buffer size: 32,64,96,128,dyn
-- Include SFP power readout
- constant INCLUDE_SFP_DDM : integer range c_NO to c_YES := c_YES;
+ constant INCLUDE_SFP_DDM : integer range c_NO to c_YES := c_NO;
--use all four SFP (1-4) as downlink to other boards (only w/o CBMNET)
constant USE_4_SFP : integer range c_NO to c_YES := c_NO;
constant ETM_ID : std_logic_vector(7 downto 0);
+--output busy signal on pair 4 of Trigger RJ45?
+ constant GEN_BUSY_OUTPUT : integer := c_YES;
constant TRIGGER_COIN_COUNT : integer := 4;
constant TRIGGER_PULSER_COUNT : integer := 2;
end process;
CTS_TRG_TYPE_OUT <= trigger_type_buf_i;
+
+
+ proc_busyout : process begin
+ wait until rising_edge(CLK);
+ if td_fsm_i = TD_FSM_IDLE then
+ TRIGGER_BUSY_OUT <= '0';
+ else
+ TRIGGER_BUSY_OUT <= '1';
+ end if;
+ end process;
read_out_proc: process(CLK) is
begin
--Trigger
TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
- TRIGGER_EXT : in std_logic_vector(4 downto 2); --additional trigger from RJ45
+ TRIGGER_EXT_2 : in std_logic;
+ TRIGGER_EXT_3 : inout std_logic;
+-- TRIGGER_EXT : inout std_logic_vector(4 downto 2); --additional trigger from RJ45
TRIGGER_OUT : out std_logic; --trigger to second input of fan-out
TRIGGER_OUT2 : out std_logic;
attribute syn_keep of CLK_PCLK_RIGHT : signal is true;
attribute syn_keep of TRIGGER_LEFT : signal is true;
attribute syn_keep of TRIGGER_RIGHT : signal is true;
- attribute syn_keep of TRIGGER_EXT : signal is true;
attribute syn_keep of TRIGGER_OUT : signal is true;
attribute syn_keep of TRIGGER_OUT2 : signal is true;
attribute syn_keep of CLK_SERDES_INT_LEFT : signal is true;
);
cts_addon_triggers_in(1 downto 0) <= CLK_EXT; -- former trigger inputs
- cts_addon_triggers_in(3 downto 2) <= TRIGGER_EXT(3 downto 2); -- former trigger inputs
+ cts_addon_triggers_in(3 downto 2) <= TRIGGER_EXT_3 & TRIGGER_EXT_2; -- former trigger inputs
cts_addon_triggers_in(7 downto 4) <= ECL_IN;
cts_addon_triggers_in(11 downto 8) <= JIN1;
FPGA3_CONNECTOR <= (others => 'Z');
FPGA4_CONNECTOR <= (others => 'Z');
-
+ gen_busy_out : if GEN_BUSY_OUTPUT = 1 generate
+ TRIGGER_EXT_3 <= trigger_busy_i;
+ end generate;
+ gen_no_busy_out : if GEN_BUSY_OUTPUT = 0 generate
+ TRIGGER_EXT_3 <= 'Z';
+ end generate;
+
+
---------------------------------------------------------------------------
-- AddOn Connector
---------------------------------------------------------------------------