The upper 16 Bit are used by the software to identify the hardware before programming the Flash to prevent loading invalid designs and
have to contain one of the following values. The last digit should be used to denote the hardware revision.
\begin{description*}
- \item[9000] design is for the central FPGA
- \item[9100] design is for either of the peripheral FPGAs
- \item[9110] design is for FPGA 1 only
- \item[9120] design is for FPGA 2 only
- \item[9130] design is for FPGA 3 only
- \item[9140] design is for FPGA 4 only
+ \item[9000] design for the central FPGA
+ \item[9100] design for either of the peripheral FPGAs
+ \item[9110] design for FPGA 1 only
+ \item[9120] design for FPGA 2 only
+ \item[9130] design for FPGA 3 only
+ \item[9140] design for FPGA 4 only
\item[9200] design for CBM Rich
\item[9300] design for CBM Tof
\item[9500] design for Trb3sc
\item[9700] design for DiRich Combiner module
\item[9900] design for Munich Skyroc boards
\item[A500] design for TRB5sc
+ \item[A600] design for MDC central
+ \item[A610] design for MDC TDC
\end{description*}
The lower 16 Bit are used to identify the contents of the design and the AddOn boards they should be used with. Combine
\item 0x73 Trb3sc TDC ADA Backplane
\item 0x75 Trb3sc TDC ADA for NINO Backplane
\item 0x80 Trb5sc
+ \item 0x90 MDC central
+ \item 0x91 MDC TDC
\end{itemize*}
The initial address set with \signal{Regio\_Init\_Address} can be chosen from the following set: