--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+entity streaming_accel is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ --TRIGGER
+ -- from CTS, from IOBUF
+ CTS_TRG_INIT : in NETBUS;
+ CTS_TRG_INIT_read : out std_logic;
+ --to FEE
+ FEE_TRG_INIT : out NETBUS;
+ FEE_TRG_INIT_read : in std_logic;
+ --from FEE
+ FEE_TRG_REPLY : in NETBUS;
+ FEE_TRG_REPLY_read : out std_logic;
+ --to CTS, to IOBUF
+ CTS_TRG_REPLY : out NETBUS;
+ CTS_TRG_REPLY_read : in std_logic;
+
+ --IPU
+ -- from CTS, from IOBUF
+ CTS_DAT_INIT : in NETBUS;
+ CTS_DAT_INIT_read : out std_logic;
+ --to FEE
+ FEE_DAT_INIT : out NETBUS;
+ FEE_DAT_INIT_read : in std_logic;
+ --from FEE
+ FEE_DAT_REPLY : in NETBUS;
+ FEE_DAT_REPLY_read : out std_logic;
+ --to GBE streaming logic
+ CTS_DAT_REPLY : out NETBUS;
+ CTS_DAT_REPLY_read : in std_logic;
+
+ --CTRL
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX;
+
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
+ CTRL_SEQNR_RESET : in std_logic
+
+ );
+
+end entity;
+
+
+architecture arch of streaming_accel is
+ attribute syn_hier : string;
+ attribute syn_hier of arch : architecture is "hard, firm";
+
+ signal apl_cts_data_in : std_logic_vector(15 downto 0);
+ signal apl_cts_packet_num_in : std_logic_vector(2 downto 0);
+ signal apl_cts_dataready_in : std_logic;
+ signal apl_cts_read_out : std_logic;
+ signal apl_cts_short_transfer_in : std_logic;
+ signal apl_cts_dtype_in : std_logic_vector(3 downto 0);
+ signal apl_cts_send_in : std_logic;
+ signal apl_cts_run_out : std_logic;
+ signal apl_cts_length_in : std_logic_vector(15 downto 0);
+ signal apl_cts_target_address : std_logic_vector(15 downto 0) := x"FFFF";
+ signal apl_cts_data_out : std_logic_vector(15 downto 0);
+ signal apl_cts_packet_num_out : std_logic_vector(2 downto 0);
+ signal apl_cts_dataready_out : std_logic;
+ signal apl_cts_read_in : std_logic;
+ signal apl_cts_seqnr_out : std_logic_vector(7 downto 0);
+ signal apl_cts_error_pattern_in : std_logic_vector(31 downto 0);
+
+begin
+
+
+---------------------------------------------------------------------
+-- On trigger channel: just a passive reader, forward as-is
+---------------------------------------------------------------------
+FEE_TRG_INIT <= CTS_TRG_INIT;
+CTS_TRG_INIT_read <= FEE_TRG_INIT_read;
+CTS_TRG_REPLY <= FEE_TRG_REPLY;
+FEE_TRG_REPLY_read <= CTS_TRG_REPLY_read;
+
+---------------------------------------------------------------------
+-- Read and save trigger number, code and type
+---------------------------------------------------------------------
+
+
+
+---------------------------------------------------------------------
+-- Fifo for events waiting for read-out
+---------------------------------------------------------------------
+
+---------------------------------------------------------------------
+-- Read-out state machine
+---------------------------------------------------------------------
+--plain forwarding if inactive
+--request next event waiting in fifo
+--forward to GbE only after CTS request received
+
+
+
+-------------------------------------------------------------------------------
+-- Application Interface, receiving request from CTS
+-------------------------------------------------------------------------------
+ THE_CTS_API: trb_net16_api_base
+ generic map (
+ API_TYPE => c_API_PASSIVE,
+ FIFO_TO_INT_DEPTH => c_FIFO_BRAM,
+ FIFO_TO_APL_DEPTH => c_FIFO_BRAM,
+ FORCE_REPLY => cfg_FORCE_REPLY(1),
+ USE_VENDOR_CORES => c_YES,
+ SECURE_MODE_TO_APL => c_YES,
+ SECURE_MODE_TO_INT => c_YES,
+ APL_WRITE_ALL_WORDS=> c_YES,
+ BROADCAST_BITMASK => x"FF"
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- APL Transmitter port
+ APL_DATA_IN => apl_cts_data_in,
+ APL_PACKET_NUM_IN => apl_cts_packet_num_in,
+ APL_DATAREADY_IN => apl_cts_dataready_in,
+ APL_READ_OUT => apl_cts_read_out,
+ APL_SHORT_TRANSFER_IN => apl_cts_short_transfer_in,
+ APL_DTYPE_IN => apl_cts_dtype_in,
+ APL_ERROR_PATTERN_IN => apl_cts_error_pattern_in,
+ APL_SEND_IN => apl_cts_send_in,
+ APL_TARGET_ADDRESS_IN => apl_cts_target_address,
+ -- Receiver port
+ APL_DATA_OUT => apl_cts_data_out,
+ APL_PACKET_NUM_OUT=> apl_cts_packet_num_out,
+ APL_TYP_OUT => apl_cts_typ_out,
+ APL_DATAREADY_OUT => apl_cts_dataready_out,
+ APL_READ_IN => apl_cts_read_in,
+ -- APL Control port
+ APL_RUN_OUT => apl_cts_run_out,
+ APL_MY_ADDRESS_IN => MY_ADDRESS_IN,
+ APL_SEQNR_OUT => apl_cts_seqnr_out,
+ APL_LENGTH_IN => apl_cts_length_in,
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => CTS_DAT_REPLY.dataready,
+ INT_MASTER_DATA_OUT => CTS_DAT_REPLY.data,
+ INT_MASTER_PACKET_NUM_OUT=> CTS_DAT_REPLY.packet_num,
+ INT_MASTER_READ_IN => CTS_DAT_REPLY_read,
+ INT_MASTER_DATAREADY_IN => '0',
+ INT_MASTER_DATA_IN => (others => '0'),
+ INT_MASTER_PACKET_NUM_IN => (others => '0'),
+ INT_MASTER_READ_OUT => open,
+ INT_SLAVE_DATAREADY_OUT => open,
+ INT_SLAVE_DATA_OUT => open,
+ INT_SLAVE_PACKET_NUM_OUT => open,
+ INT_SLAVE_READ_IN => '0',
+ INT_SLAVE_DATAREADY_IN => CTS_DAT_INIT.dataready,
+ INT_SLAVE_DATA_IN => CTS_DAT_INIT.data,
+ INT_SLAVE_PACKET_NUM_IN=> CTS_DAT_INIT.packet_num,
+ INT_SLAVE_READ_OUT => CTS_DAT_INIT_read,
+ -- Status and control port
+ CTRL_SEQNR_RESET => CTRL_SEQNR_RESET,
+ STAT_FIFO_TO_INT => open,
+ STAT_FIFO_TO_APL => open
+ );
+
+
+
+end architecture;
--- /dev/null
+
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+entity trb_net16_api_ipu_streaming_accel is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+-- TRG port
+ TRG_TO_FEE_DATA_OUT : out std_logic_vector (15 downto 0);
+ TRG_TO_FEE_DATAREADY_OUT : out std_logic;
+ TRG_TO_FEE_PACKET_NUM_OUT : out std_logic_vector (2 downto 0);
+ TRG_TO_FEE_READ_IN : in std_logic;
+
+ TRG_FROM_FEE_DATA_IN : in std_logic_vector (15 downto 0);
+ TRG_FROM_FEE_DATAREADY_IN : in std_logic;
+ TRG_FROM_FEE_PACKET_NUM_IN : in std_logic_vector (2 downto 0);
+ TRG_FROM_FEE_READ_OUT : out std_logic;
+
+ TRG_FROM_CTS_DATA_IN : in std_logic_vector (15 downto 0);
+ TRG_FROM_CTS_DATAREADY_IN : in std_logic;
+ TRG_FROM_CTS_PACKET_NUM_IN : in std_logic_vector (2 downto 0);
+ TRG_FROM_CTS_READ_OUT : out std_logic;
+
+ TRG_TO_CTS_DATA_OUT : out std_logic_vector (15 downto 0);
+ TRG_TO_CTS_DATAREADY_OUT : out std_logic;
+ TRG_TO_CTS_PACKET_NUM_OUT : out std_logic_vector (2 downto 0);
+ TRG_TO_CTS_READ_IN : in std_logic;
+
+-- DATA port
+ DAT_TO_FEE_DATA_OUT : out std_logic_vector (15 downto 0);
+ DAT_TO_FEE_DATAREADY_OUT : out std_logic;
+ DAT_TO_FEE_PACKET_NUM_OUT : out std_logic_vector (2 downto 0);
+ DAT_TO_FEE_READ_IN : in std_logic;
+
+ DAT_FROM_FEE_DATA_IN : in std_logic_vector (15 downto 0);
+ DAT_FROM_FEE_DATAREADY_IN : in std_logic;
+ DAT_FROM_FEE_PACKET_NUM_IN : in std_logic_vector (2 downto 0);
+ DAT_FROM_FEE_READ_OUT : out std_logic;
+
+ DAT_FROM_CTS_DATA_IN : in std_logic_vector (15 downto 0);
+ DAT_FROM_CTS_DATAREADY_IN : in std_logic;
+ DAT_FROM_CTS_PACKET_NUM_IN : in std_logic_vector (2 downto 0);
+ DAT_FROM_CTS_READ_OUT : out std_logic;
+
+ DAT_TO_CTS_DATA_OUT : out std_logic_vector (15 downto 0);
+ DAT_TO_CTS_DATAREADY_OUT : out std_logic;
+ DAT_TO_CTS_PACKET_NUM_OUT : out std_logic_vector (2 downto 0);
+ DAT_TO_CTS_READ_IN : in std_logic;
+
+--GBE Port
+ --Event information coming from CTS
+ CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); --valid while start_readout is high
+ CTS_CODE_OUT : out std_logic_vector (7 downto 0); --valid while start_readout is high
+ CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0); --valid while start_readout is high
+ CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); --valid while start_readout is high
+ CTS_START_READOUT_OUT : out std_logic; --goes high after request is transported through hub, goes low
+ --after user send information to cts.
+
+ --Information sent to CTS
+ --status data, equipped with DHDR
+ CTS_DATA_IN : in std_logic_vector (31 downto 0);
+ CTS_DATAREADY_IN : in std_logic;
+ CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM, should be high 1 CLK cycle
+ CTS_READ_OUT : out std_logic;
+ CTS_LENGTH_IN : in std_logic_vector (15 downto 0); --valid when raising dataready for first time
+ CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0); --valid when readout_finished is high
+
+ -- Data from Frontends
+ FEE_DATA_OUT : out std_logic_vector (15 downto 0); --data from FEE
+ FEE_DATAREADY_OUT : out std_logic; --data on data_out is valid
+ FEE_READ_IN : in std_logic; --must be high always unless connected entity can not read data, otherwise you will never get a dataready
+ FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); --valid after busy is low again
+ FEE_BUSY_OUT : out std_logic; --goes high shortly after start_readout; goes low when last dataword from FEE
+ --has been read.
+--Controls
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX;
+
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
+ CTRL_SEQNR_RESET : in std_logic
+
+ );
+end entity;
+
+architecture trb_net16_api_ipu_streaming_arch of trb_net16_api_ipu_streaming_accel is
+
+ attribute syn_hier : string;
+ attribute syn_hier of trb_net16_api_ipu_streaming_arch : architecture is "hard, firm";
+
+ signal APL_CTS_DATA_OUT : std_logic_vector(15 downto 0);
+ signal APL_CTS_PACKET_NUM_OUT : std_logic_vector(2 downto 0);
+ signal APL_CTS_DATAREADY_OUT : std_logic;
+ signal APL_CTS_READ_IN : std_logic;
+ signal APL_CTS_SEQNR_OUT : std_logic_vector(7 downto 0);
+ signal APL_CTS_ERROR_PATTERN_IN : std_logic_vector(31 downto 0);
+
+ signal apl_fee_dtype_in : std_logic_vector(3 downto 0);
+ signal apl_fee_error_pattern_in : std_logic_vector(31 downto 0);
+ signal apl_fee_send_in : std_logic;
+ signal APL_FEE_DATA_OUT : std_logic_vector(15 downto 0);
+ signal APL_FEE_PACKET_NUM_OUT : std_logic_vector(2 downto 0);
+ signal APL_FEE_DATAREADY_OUT : std_logic;
+ signal APL_FEE_READ_IN : std_logic;
+ signal APL_FEE_TYP_OUT : std_logic_vector(2 downto 0);
+ signal APL_FEE_RUN_OUT : std_logic;
+ signal APL_FEE_SEQNR_OUT : std_logic_vector(7 downto 0);
+
+ signal APL_CTS_TYP_OUT : std_logic_vector(2 downto 0);
+
+
+ signal APL_CTS_DATA_IN : std_logic_vector(15 downto 0);
+ signal APL_CTS_PACKET_NUM_IN : std_logic_vector(2 downto 0);
+ signal APL_CTS_DATAREADY_IN : std_logic;
+ signal APL_CTS_READ_OUT : std_logic;
+ signal APL_CTS_SHORT_TRANSFER_IN : std_logic;
+ signal APL_CTS_DTYPE_IN : std_logic_vector(3 downto 0);
+ signal APL_CTS_SEND_IN : std_logic;
+ signal APL_CTS_RUN_OUT : std_logic;
+ signal APL_CTS_LENGTH_IN : std_logic_vector(15 downto 0);
+
+ signal buf_CTS_CODE_OUT : std_logic_vector(7 downto 0);
+ signal buf_CTS_INFORMATION_OUT : std_logic_vector(7 downto 0);
+ signal buf_CTS_READOUT_TYPE_OUT : std_logic_vector(3 downto 0);
+ signal buf_CTS_NUMBER_OUT : std_logic_vector(15 downto 0);
+ signal buf_CTS_START_READOUT_OUT : std_logic;
+ signal last_buf_CTS_START_READOUT_OUT : std_logic;
+ signal cts_start_readout_rising : std_logic;
+
+ signal end_of_data_reached : std_logic;
+ signal data_counter : signed(17 downto 0);
+ signal data_length : signed(17 downto 0);
+ signal buf_FEE_DATAREADY_OUT : std_logic;
+
+ signal cts_trg_type, fifo_trg_type : std_logic_vector (3 downto 0);
+ signal cts_trg_number, fifo_trg_number : std_logic_vector (15 downto 0);
+ signal cts_trg_code, fifo_trg_code : std_logic_vector (7 downto 0);
+ signal fifo_trg_read, fifo_trg_write : std_logic;
+ signal fifo_trg_empty, fifo_trg_full : std_logic;
+ signal fifo_trg_fill : std_logic_vector(9 downto 0);
+ signal cts_trg_received, cts_trg_release : std_logic;
+ signal fee_buffer_full,fifo_trg_buffer_full : std_logic;
+
+ signal cfg_settings : std_logic_vector(31 downto 0);
+ --0 enable
+ signal fsm_ipu_status_bits : std_logic_vector(3 downto 0);
+ signal fsm_error : std_logic_vector(7 downto 0);
+ signal buf_FEE_STATUS_BITS_OUT : std_logic_vector(31 downto 0);
+ signal fifo_trg_valid, last_fifo_trg_read : std_logic;
+ signal data_transfer_enabled : std_logic;
+
+ type fsm_state_t is (IDLE,SEND_REQUEST_OWN,WAIT_FOR_CTS_REQUEST,CHECK_CTS_INFO,DATA_TRANSFER);
+ signal ipu_fsm_state : fsm_state_t;
+
+
+begin
+
+-------------------------------------------------------------------------------
+--Direct forwarding of trigger and busy release
+-------------------------------------------------------------------------------
+ TRG_TO_FEE_DATA_OUT <= TRG_FROM_CTS_DATA_IN;
+ TRG_TO_FEE_DATAREADY_OUT <= TRG_FROM_CTS_DATAREADY_IN;
+ TRG_TO_FEE_PACKET_NUM_OUT <= TRG_FROM_CTS_PACKET_NUM_IN;
+ TRG_FROM_CTS_READ_OUT <= TRG_TO_FEE_READ_IN;
+
+ TRG_TO_CTS_DATA_OUT <= TRG_FROM_FEE_DATA_IN;
+ TRG_TO_CTS_DATAREADY_OUT <= TRG_FROM_FEE_DATAREADY_IN;
+ TRG_TO_CTS_PACKET_NUM_OUT <= TRG_FROM_FEE_PACKET_NUM_IN;
+ TRG_FROM_FEE_READ_OUT <= TRG_TO_CTS_READ_IN;
+
+
+-------------------------------------------------------------------------------
+--Read trigger information from CTS and write to FIFO
+-------------------------------------------------------------------------------
+THE_TRG_READ : trb_net16_trigger
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => '1',
+
+ INT_DATAREADY_OUT => open,
+ INT_DATA_OUT => open,
+ INT_PACKET_NUM_OUT => open,
+ INT_READ_IN => '1',
+
+ INT_DATAREADY_IN => TRG_FROM_CTS_DATAREADY_IN,
+ INT_DATA_IN => TRG_FROM_CTS_DATA_IN,
+ INT_PACKET_NUM_IN => TRG_FROM_CTS_PACKET_NUM_IN,
+ INT_READ_OUT => open,
+
+ -- Trigger information output
+ TRG_TYPE_OUT => cts_trg_type,
+ TRG_NUMBER_OUT => cts_trg_number,
+ TRG_CODE_OUT => cts_trg_code,
+ TRG_INFORMATION_OUT => open,
+ TRG_RECEIVED_OUT => cts_trg_received,
+ TRG_RELEASE_IN => cts_trg_release,
+ TRG_ERROR_PATTERN_IN => (others => '0')
+ );
+
+
+
+PROC_TRG_STORE : process begin
+ wait until rising_edge(CLK);
+
+ cts_trg_release <= '0';
+ fifo_trg_write <= '0';
+
+ if TRG_FROM_FEE_DATAREADY_IN = '1' and TRG_FROM_FEE_PACKET_NUM_IN = c_F1 and TRG_TO_CTS_READ_IN = '1' then
+ fee_buffer_full <= TRG_FROM_FEE_DATA_IN(4) ;
+ end if;
+
+ if TRG_FROM_FEE_DATAREADY_IN = '1' and TRG_FROM_FEE_PACKET_NUM_IN = c_F2 and TRG_TO_CTS_READ_IN = '1' then
+ fifo_trg_write <= cfg_settings(0); --only when enabled
+ cts_trg_release <= '1';
+ end if;
+
+end process;
+
+
+
+THE_TRG_FIFO : entity work.fifo_36x512_oreg
+ port map(
+ Data(15 downto 0) => cts_trg_number,
+ Data(19 downto 16) => cts_trg_type,
+ Data(27 downto 20) => cts_trg_code,
+ Data(28) => fee_buffer_full,
+ Data(35 downto 29) => (others => '0'),
+ Clock => CLK,
+ WrEn => fifo_trg_write,
+ RdEn => fifo_trg_read,
+ Reset => RESET,
+ AmFullThresh => (2=>'0',others => '1'),
+ Q(15 downto 0) => fifo_trg_number,
+ Q(19 downto 16) => fifo_trg_type,
+ Q(27 downto 20) => fifo_trg_code,
+ Q(28) => fifo_trg_buffer_full,
+ WCNT => fifo_trg_fill,
+ Empty => fifo_trg_empty,
+ Full => open,
+ AlmostFull => fifo_trg_full
+ );
+
+
+
+
+-------------------------------------------------------------------------------
+--Application Interface, receiving IPU request from CTS
+-------------------------------------------------------------------------------
+ THE_CTS_API: trb_net16_api_base
+ generic map (
+ API_TYPE => c_API_PASSIVE,
+ FIFO_TO_INT_DEPTH => c_FIFO_BRAM,
+ FIFO_TO_APL_DEPTH => c_FIFO_BRAM,
+ FORCE_REPLY => cfg_FORCE_REPLY(1),
+ USE_VENDOR_CORES => c_YES,
+ SECURE_MODE_TO_APL => c_YES,
+ SECURE_MODE_TO_INT => c_YES,
+ APL_WRITE_ALL_WORDS=> c_YES,
+ BROADCAST_BITMASK => x"FF"
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- APL Transmitter port
+ APL_DATA_IN => APL_CTS_DATA_IN,
+ APL_PACKET_NUM_IN => APL_CTS_PACKET_NUM_IN,
+ APL_DATAREADY_IN => APL_CTS_DATAREADY_IN,
+ APL_READ_OUT => APL_CTS_READ_OUT,
+ APL_SHORT_TRANSFER_IN => APL_CTS_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => APL_CTS_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL_CTS_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL_CTS_SEND_IN,
+ APL_TARGET_ADDRESS_IN => x"FFFF",
+ -- Receiver port
+ APL_DATA_OUT => APL_CTS_DATA_OUT,
+ APL_PACKET_NUM_OUT=> APL_CTS_PACKET_NUM_OUT,
+ APL_TYP_OUT => APL_CTS_TYP_OUT,
+ APL_DATAREADY_OUT => APL_CTS_DATAREADY_OUT,
+ APL_READ_IN => APL_CTS_READ_IN,
+ -- APL Control port
+ APL_RUN_OUT => APL_CTS_RUN_OUT,
+ APL_MY_ADDRESS_IN => MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL_CTS_SEQNR_OUT,
+ APL_LENGTH_IN => APL_CTS_LENGTH_IN,
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => DAT_TO_CTS_DATAREADY_OUT,
+ INT_MASTER_DATA_OUT => DAT_TO_CTS_DATA_OUT,
+ INT_MASTER_PACKET_NUM_OUT=> DAT_TO_CTS_PACKET_NUM_OUT,
+ INT_MASTER_READ_IN => DAT_TO_CTS_READ_IN,
+ INT_MASTER_DATAREADY_IN => '0',
+ INT_MASTER_DATA_IN => (others => '0'),
+ INT_MASTER_PACKET_NUM_IN => (others => '0'),
+ INT_MASTER_READ_OUT => open,
+ INT_SLAVE_DATAREADY_OUT => open,
+ INT_SLAVE_DATA_OUT => open,
+ INT_SLAVE_PACKET_NUM_OUT => open,
+ INT_SLAVE_READ_IN => '0',
+ INT_SLAVE_DATAREADY_IN => DAT_FROM_CTS_DATAREADY_IN,
+ INT_SLAVE_DATA_IN => DAT_FROM_CTS_DATA_IN,
+ INT_SLAVE_PACKET_NUM_IN=> DAT_FROM_CTS_PACKET_NUM_IN,
+ INT_SLAVE_READ_OUT => DAT_FROM_CTS_READ_OUT,
+ -- Status and control port
+ CTRL_SEQNR_RESET => CTRL_SEQNR_RESET,
+ STAT_FIFO_TO_INT => open,
+ STAT_FIFO_TO_APL => open
+ );
+
+
+-------------------------------------------------------------------------------
+--Reading CTS IPU request
+-------------------------------------------------------------------------------
+
+ THE_IPUDATA : trb_net16_ipudata
+ generic map(
+ DO_CHECKS => c_NO
+ )
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => '1',
+ -- Port to API
+ API_DATA_OUT => APL_CTS_DATA_IN,
+ API_PACKET_NUM_OUT => APL_CTS_PACKET_NUM_IN,
+ API_DATAREADY_OUT => APL_CTS_DATAREADY_IN,
+ API_READ_IN => APL_CTS_READ_OUT,
+ API_SHORT_TRANSFER_OUT => APL_CTS_SHORT_TRANSFER_IN,
+ API_DTYPE_OUT => APL_CTS_DTYPE_IN,
+ API_ERROR_PATTERN_OUT => APL_CTS_ERROR_PATTERN_IN,
+ API_SEND_OUT => APL_CTS_SEND_IN,
+ -- Receiver port
+ API_DATA_IN => APL_CTS_DATA_OUT,
+ API_PACKET_NUM_IN => APL_CTS_PACKET_NUM_OUT,
+ API_TYP_IN => APL_CTS_TYP_OUT,
+ API_DATAREADY_IN => APL_CTS_DATAREADY_OUT,
+ API_READ_OUT => APL_CTS_READ_IN,
+ -- APL Control port
+ API_RUN_IN => APL_CTS_RUN_OUT,
+ API_SEQNR_IN => APL_CTS_SEQNR_OUT,
+ API_LENGTH_OUT => APL_CTS_LENGTH_IN,
+ MY_ADDRESS_IN => MY_ADDRESS_IN,
+
+ --Information received with request
+ IPU_NUMBER_OUT => buf_CTS_NUMBER_OUT,
+ IPU_INFORMATION_OUT => buf_CTS_INFORMATION_OUT,
+ IPU_READOUT_TYPE_OUT => buf_CTS_READOUT_TYPE_OUT,
+ IPU_CODE_OUT => buf_CTS_CODE_OUT,
+ --start strobe
+ IPU_START_READOUT_OUT => buf_CTS_START_READOUT_OUT,
+ --detector data, equipped with DHDR
+ IPU_DATA_IN => CTS_DATA_IN,
+ IPU_DATAREADY_IN => CTS_DATAREADY_IN,
+ --no more data, end transfer, send TRM
+ IPU_READOUT_FINISHED_IN => CTS_READOUT_FINISHED_IN,
+ --will be low every second cycle due to 32bit -> 16bit conversion
+ IPU_READ_OUT => CTS_READ_OUT,
+ IPU_LENGTH_IN => CTS_LENGTH_IN,
+ IPU_ERROR_PATTERN_IN => CTS_STATUS_BITS_IN,
+
+ STAT_DEBUG => open
+ );
+
+ --TODO
+ --store information from CTS in registers
+ --push to fifo 52bit when busy release is received TRG_FROM_FEE_DATAREADY_IN=1
+ --store buffer bits from release
+
+
+ --IPU state machine
+ --fetch word from fifo
+ --sent request to FEE
+ --block dataready from FEE
+ --wait for request from CTS buf_CTS_START_READOUT_OUT=1
+ --calculate mismatch bit (internal vs. CTS request) and add to error pattern later (PROC_IPU_STATUS_BITS)
+ --wait few cycles
+ --unblock dataready
+ --wait for APL_FEE_RUN_OUT=0
+
+THE_IPU_FSM : process begin
+ wait until rising_edge(CLK);
+ apl_fee_send_in <= '0';
+ fifo_trg_read <= '0';
+ last_fifo_trg_read <= fifo_trg_read;
+ fifo_trg_valid <= last_fifo_trg_read;
+
+ case ipu_fsm_state is
+ when IDLE =>
+ fsm_ipu_status_bits <= x"0";
+ if fifo_trg_empty = '0' then
+ fifo_trg_read <= '1';
+ ipu_fsm_state <= SEND_REQUEST_OWN;
+ end if;
+ if buf_CTS_START_READOUT_OUT = '1' then
+ apl_fee_send_in <= '1';
+ apl_fee_error_pattern_in(15 downto 0) <= buf_CTS_NUMBER_OUT;
+ apl_fee_error_pattern_in(23 downto 16) <= buf_CTS_CODE_OUT;
+ apl_fee_error_pattern_in(31 downto 24) <= buf_CTS_INFORMATION_OUT;
+ apl_fee_dtype_in <= buf_CTS_READOUT_TYPE_OUT;
+ ipu_fsm_state <= DATA_TRANSFER;
+ end if;
+
+
+ when SEND_REQUEST_OWN =>
+ fsm_ipu_status_bits <= x"a";
+
+ data_transfer_enabled <= '0';
+ if fifo_trg_valid = '1' then
+ apl_fee_send_in <= '1';
+ apl_fee_error_pattern_in(15 downto 0) <= fifo_trg_number;
+ apl_fee_error_pattern_in(23 downto 16) <= fifo_trg_code;
+ apl_fee_error_pattern_in(31 downto 24) <= x"00";
+ apl_fee_dtype_in <= fifo_trg_type;
+ ipu_fsm_state <= WAIT_FOR_CTS_REQUEST;
+ end if;
+
+ when WAIT_FOR_CTS_REQUEST =>
+ fsm_ipu_status_bits <= x"b";
+ if buf_CTS_START_READOUT_OUT = '1' then
+ ipu_fsm_state <= CHECK_CTS_INFO;
+ end if;
+
+ when CHECK_CTS_INFO =>
+ fsm_ipu_status_bits <= x"c";
+ ipu_fsm_state <= DATA_TRANSFER;
+ fsm_error <= x"00";
+ if fifo_trg_number /= buf_CTS_NUMBER_OUT then
+ fsm_error(0) <= '1';
+ end if;
+ if fifo_trg_code /= buf_CTS_CODE_OUT then
+ fsm_error(1) <= '1';
+ end if;
+
+ when DATA_TRANSFER =>
+ fsm_ipu_status_bits <= x"d";
+
+ data_transfer_enabled <= '1';
+ if buf_CTS_START_READOUT_OUT = '0' then
+ ipu_fsm_state <= IDLE;
+ end if;
+
+ end case;
+
+
+end process;
+
+
+
+
+-- --to be driven by state machine
+-- --Signals to FEE
+-- APL_FEE_DTYPE_IN,
+-- APL_FEE_ERROR_PATTERN_IN,
+-- APL_FEE_SEND_IN,
+-- APL_FEE_RUN_OUT,
+-- (CTS_STATUS_BITS_IN)
+-- fifo_trg_read
+--
+-- -- to be read by state machine
+-- --Signals from the CTS:
+-- buf_CTS_NUMBER_OUT,
+-- buf_CTS_INFORMATION_OUT,
+-- buf_CTS_READOUT_TYPE_OUT,
+-- buf_CTS_CODE_OUT,
+-- buf_CTS_START_READOUT_OUT,
+--
+-- CTS_READOUT_FINISHED_IN -GBE finished
+--
+-- fifo_trg_number,
+-- fifo_trg_type,
+-- fifo_trg_code,
+-- fifo_trg_buffer_full,
+-- fifo_trg_empty,
+--
+
+
+-------------------------------------------------------------------------------
+--Application Interface, sending IPU request to FEE
+-------------------------------------------------------------------------------
+
+ THE_FEE_API: trb_net16_api_base
+ generic map (
+ API_TYPE => c_API_ACTIVE,
+ FIFO_TO_INT_DEPTH => c_FIFO_BRAM,
+ FIFO_TO_APL_DEPTH => c_FIFO_BRAM,
+ FORCE_REPLY => cfg_FORCE_REPLY(1),
+ USE_VENDOR_CORES => c_YES,
+ SECURE_MODE_TO_APL => c_YES,
+ SECURE_MODE_TO_INT => c_YES,
+ APL_WRITE_ALL_WORDS=> c_NO,
+ BROADCAST_BITMASK => x"FF"
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- APL Transmitter port
+ APL_DATA_IN => (others => '0'),
+ APL_PACKET_NUM_IN => (others => '0'),
+ APL_DATAREADY_IN => '0',
+ APL_READ_OUT => open,
+ APL_SHORT_TRANSFER_IN => '1',
+ APL_DTYPE_IN => apl_fee_dtype_in,
+ APL_ERROR_PATTERN_IN => apl_fee_error_pattern_in,
+ APL_SEND_IN => apl_fee_send_in,
+ APL_TARGET_ADDRESS_IN => (others => '1'),
+ -- Receiver port
+ APL_DATA_OUT => APL_FEE_DATA_OUT,
+ APL_PACKET_NUM_OUT=> APL_FEE_PACKET_NUM_OUT,
+ APL_TYP_OUT => APL_FEE_TYP_OUT,
+ APL_DATAREADY_OUT => APL_FEE_DATAREADY_OUT,
+ APL_READ_IN => APL_FEE_READ_IN,
+ -- APL Control port
+ APL_RUN_OUT => APL_FEE_RUN_OUT,
+ APL_MY_ADDRESS_IN => MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL_FEE_SEQNR_OUT,
+ APL_LENGTH_IN => x"0000",
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => DAT_TO_FEE_DATAREADY_OUT,
+ INT_MASTER_DATA_OUT => DAT_TO_FEE_DATA_OUT,
+ INT_MASTER_PACKET_NUM_OUT=> DAT_TO_FEE_PACKET_NUM_OUT,
+ INT_MASTER_READ_IN => DAT_TO_FEE_READ_IN,
+ INT_MASTER_DATAREADY_IN => '0',
+ INT_MASTER_DATA_IN => (others => '0'),
+ INT_MASTER_PACKET_NUM_IN => (others => '0'),
+ INT_MASTER_READ_OUT => open,
+ INT_SLAVE_DATAREADY_OUT => open,
+ INT_SLAVE_DATA_OUT => open,
+ INT_SLAVE_PACKET_NUM_OUT => open,
+ INT_SLAVE_READ_IN => '0',
+ INT_SLAVE_DATAREADY_IN => DAT_FROM_FEE_DATAREADY_IN,
+ INT_SLAVE_DATA_IN => DAT_FROM_FEE_DATA_IN,
+ INT_SLAVE_PACKET_NUM_IN=> DAT_FROM_FEE_PACKET_NUM_IN,
+ INT_SLAVE_READ_OUT => DAT_FROM_FEE_READ_OUT,
+ -- Status and control port
+ CTRL_SEQNR_RESET => CTRL_SEQNR_RESET,
+ STAT_FIFO_TO_INT => open,
+ STAT_FIFO_TO_APL => open
+ );
+
+
+---------------------------------------------------------------------
+--Forward CTS request to FEE & Put Information to Output
+---------------------------------------------------------------------
+
+
+-- PROC_START_READOUT_RISING : process(CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- last_buf_CTS_START_READOUT_OUT <= buf_CTS_START_READOUT_OUT;
+-- cts_start_readout_rising <= buf_CTS_START_READOUT_OUT and not last_buf_CTS_START_READOUT_OUT;
+-- end if;
+-- end process;
+
+ APL_FEE_READ_IN <= '1' when (FEE_READ_IN = '1' or (APL_FEE_TYP_OUT /= TYPE_DAT) or end_of_data_reached = '1') and data_transfer_enabled = '1' else '0';
+ buf_FEE_DATAREADY_OUT <= APL_FEE_DATAREADY_OUT when APL_FEE_TYP_OUT = TYPE_DAT and end_of_data_reached = '0' and data_transfer_enabled = '1' else '0';
+ FEE_DATAREADY_OUT <= buf_FEE_DATAREADY_OUT;
+ FEE_DATA_OUT <= APL_FEE_DATA_OUT;
+ FEE_BUSY_OUT <= APL_FEE_RUN_OUT;
+
+-- APL_FEE_SEND_IN <= cts_start_readout_rising;
+-- APL_FEE_ERROR_PATTERN_IN(15 downto 0) <= buf_CTS_NUMBER_OUT;
+-- APL_FEE_ERROR_PATTERN_IN(23 downto 16) <= buf_CTS_CODE_OUT;
+-- APL_FEE_ERROR_PATTERN_IN(31 downto 24) <= buf_CTS_INFORMATION_OUT;
+-- APL_FEE_DTYPE_IN <= buf_CTS_READOUT_TYPE_OUT;
+
+ CTS_NUMBER_OUT <= buf_CTS_NUMBER_OUT;
+ CTS_INFORMATION_OUT <= buf_CTS_INFORMATION_OUT;
+ CTS_READOUT_TYPE_OUT <= buf_CTS_READOUT_TYPE_OUT;
+ CTS_CODE_OUT <= buf_CTS_CODE_OUT;
+ CTS_START_READOUT_OUT <= buf_CTS_START_READOUT_OUT;
+
+---------------------------------------------------------------------
+-- Find end of data
+---------------------------------------------------------------------
+ PROC_COUNT_DATA : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or APL_FEE_RUN_OUT = '0' then
+ data_counter <= to_signed(-3,18);
+ end_of_data_reached <= '0';
+ elsif APL_FEE_READ_IN = '1' and buf_FEE_DATAREADY_OUT = '1' then
+ data_counter <= data_counter + 1;
+ if data_counter = data_length then
+ end_of_data_reached <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ PROC_EOD : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or APL_FEE_RUN_OUT = '0' then
+ data_length <= to_signed(0,18);
+ elsif buf_FEE_DATAREADY_OUT = '1' and data_counter = to_signed(-1,18) then
+ data_length <= signed('0' & APL_FEE_DATA_OUT & '0');
+ end if;
+ end if;
+ end process;
+
+---------------------------------------------------------------------
+-- Handle incoming error pattern from FEE
+---------------------------------------------------------------------
+
+ PROC_IPU_STATUS_BITS : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if APL_FEE_PACKET_NUM_OUT = c_F1 and APL_FEE_TYP_OUT = TYPE_TRM then
+ buf_FEE_STATUS_BITS_OUT(31 downto 16) <= APL_FEE_DATA_OUT or (x"00" & fsm_error);
+ elsif APL_FEE_PACKET_NUM_OUT = c_F2 and APL_FEE_TYP_OUT = TYPE_TRM then
+ buf_FEE_STATUS_BITS_OUT(15 downto 0) <= APL_FEE_DATA_OUT;
+ end if;
+ end if;
+ end process;
+ FEE_STATUS_BITS_OUT <= buf_FEE_STATUS_BITS_OUT;
+
+---------------------------------------------------------------------
+-- Registers
+---------------------------------------------------------------------
+THE_REGS : process begin
+ wait until rising_edge(CLK);
+ BUS_TX.ack <= '0';
+ BUS_TX.nack <= '0';
+ BUS_TX.unknown <= '0';
+
+ if BUS_RX.write = '1' then
+ BUS_TX.ack <= '1';
+ if BUS_RX.addr = x"0000" then
+ cfg_settings <= BUS_RX.data(31 downto 0);
+ else
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+ end if;
+ elsif BUS_RX.read = '1' then
+ BUS_TX.data <= (others => '0');
+ BUS_TX.ack <= '1';
+ if BUS_RX.addr = x"0000" then
+ BUS_TX.data(31 downto 0) <= cfg_settings;
+ elsif BUS_RX.addr = x"0010" then
+ BUS_TX.data(11 downto 0) <= fifo_trg_empty & fifo_trg_full & fifo_trg_fill;
+ BUS_TX.data(19 downto 12) <= cts_trg_number(7 downto 0);
+ BUS_TX.data(27 downto 20) <= fifo_trg_number(7 downto 0);
+ BUS_TX.data(28) <= fifo_trg_buffer_full;
+ BUS_TX.data(31 downto 29) <= (others => '0');
+ elsif BUS_RX.addr = x"0011" then
+ BUS_TX.data(31 downto 0) <= buf_FEE_STATUS_BITS_OUT(31 downto 0);
+ elsif BUS_RX.addr = x"0012" then
+ BUS_TX.data(7 downto 0) <= fsm_error;
+ BUS_TX.data(11 downto 8) <= fsm_ipu_status_bits;
+ else
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+ end if;
+ end if;
+end process;
+
+
+end architecture;
signal hub_init_packet_num_in : std_logic_vector(12 downto 0);
signal hub_reply_packet_num_in : std_logic_vector(12 downto 0);
-signal cts_init_data_out : std_logic_vector(15 downto 0);
-signal cts_init_dataready_out : std_logic;
-signal cts_init_packet_num_out : std_logic_vector(2 downto 0);
-signal cts_init_read_in : std_logic;
+signal cts_trg_init_data_out , cts_init_data_out : std_logic_vector(15 downto 0);
+signal cts_trg_init_dataready_out , cts_init_dataready_out : std_logic;
+signal cts_trg_init_packet_num_out, cts_init_packet_num_out : std_logic_vector(2 downto 0);
+signal cts_trg_init_read_in , cts_init_read_in : std_logic;
-signal cts_reply_data_in : std_logic_vector(15 downto 0);
-signal cts_reply_dataready_in : std_logic;
-signal cts_reply_packet_num_in : std_logic_vector(2 downto 0);
-signal cts_reply_read_out : std_logic;
+signal cts_trg_reply_data_in , cts_reply_data_in : std_logic_vector(15 downto 0);
+signal cts_trg_reply_dataready_in , cts_reply_dataready_in : std_logic;
+signal cts_trg_reply_packet_num_in, cts_reply_packet_num_in : std_logic_vector(2 downto 0);
+signal cts_trg_reply_read_out , cts_reply_read_out : std_logic;
signal common_ctrl : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
signal common_stat : std_logic_vector(std_COMSTATREG*32-1 downto 0);
signal med_ctrl_op : std_logic_vector (mii*16-1 downto 0);
signal rdack, wrack : std_logic;
+signal hubbus_rx, intbus_rx : CTRLBUS_RX;
+signal hubbus_tx, intbus_tx : CTRLBUS_TX;
+
begin
---------------------------------------------------------------------
INT_REPLY_PACKET_NUM_IN => hub_reply_packet_num_in,
INT_REPLY_READ_OUT => hub_reply_read_out,
--REGIO INTERFACE
- REGIO_ADDR_OUT => BUS_RX.addr,
- REGIO_READ_ENABLE_OUT => BUS_RX.read,
- REGIO_WRITE_ENABLE_OUT => BUS_RX.write,
- REGIO_DATA_OUT => BUS_RX.data,
- REGIO_DATA_IN => BUS_TX.data,
+ REGIO_ADDR_OUT => hubbus_rx.addr,
+ REGIO_READ_ENABLE_OUT => hubbus_rx.read,
+ REGIO_WRITE_ENABLE_OUT => hubbus_rx.write,
+ REGIO_DATA_OUT => hubbus_rx.data,
+ REGIO_DATA_IN => hubbus_tx.data,
REGIO_DATAREADY_IN => rdack,
- REGIO_NO_MORE_DATA_IN => BUS_TX.nack,
+ REGIO_NO_MORE_DATA_IN => hubbus_tx.nack,
REGIO_WRITE_ACK_IN => wrack,
- REGIO_UNKNOWN_ADDR_IN => BUS_TX.unknown,
- REGIO_TIMEOUT_OUT => BUS_RX.timeout,
+ REGIO_UNKNOWN_ADDR_IN => hubbus_tx.unknown,
+ REGIO_TIMEOUT_OUT => hubbus_rx.timeout,
TIMER_TICKS_OUT(0) => TIMER.tick_us,
TIMER_TICKS_OUT(1) => TIMER.tick_ms,
HUB_STAT_GEN => buf_HUB_STAT_GEN
);
- rdack <= BUS_TX.ack or BUS_TX.rack;
- wrack <= BUS_TX.ack or BUS_TX.wack;
+ rdack <= hubbus_tx.ack or hubbus_tx.rack;
+ wrack <= hubbus_tx.ack or hubbus_tx.wack;
hub_ctrl_debug(2 downto 0) <= not io_error_in;
hub_ctrl_debug(31 downto 3) <= (others => '0');
MED_ERROR_IN => io_error_in,
-- Internal direction port
+ INT_INIT_DATAREADY_OUT => cts_trg_init_dataready_out,
+ INT_INIT_DATA_OUT => cts_trg_init_data_out,
+ INT_INIT_PACKET_NUM_OUT => cts_trg_init_packet_num_out,
+ INT_INIT_READ_IN => cts_trg_init_read_in,
- INT_INIT_DATAREADY_OUT => hub_init_dataready_in(0),
- INT_INIT_DATA_OUT => hub_init_data_in(15 downto 0),
- INT_INIT_PACKET_NUM_OUT => hub_init_packet_num_in(2 downto 0),
- INT_INIT_READ_IN => hub_init_read_out(0),
-
- INT_INIT_DATAREADY_IN => hub_init_dataready_out(0),
- INT_INIT_DATA_IN => hub_init_data_out(15 downto 0),
- INT_INIT_PACKET_NUM_IN => hub_init_packet_num_out(2 downto 0),
- INT_INIT_READ_OUT => hub_init_read_in(0),
+ INT_INIT_DATAREADY_IN => '0',
+ INT_INIT_DATA_IN => (others => '0'),
+ INT_INIT_PACKET_NUM_IN => (others => '0'),
+ INT_INIT_READ_OUT => open,
- INT_REPLY_DATAREADY_OUT => hub_reply_dataready_in(0),
- INT_REPLY_DATA_OUT => hub_reply_data_in(15 downto 0),
- INT_REPLY_PACKET_NUM_OUT => hub_reply_packet_num_in(2 downto 0),
- INT_REPLY_READ_IN => hub_reply_read_out(0),
+ INT_REPLY_DATAREADY_OUT => open,
+ INT_REPLY_DATA_OUT => open,
+ INT_REPLY_PACKET_NUM_OUT => open,
+ INT_REPLY_READ_IN => '1',
- INT_REPLY_DATAREADY_IN => hub_reply_dataready_out(0),
- INT_REPLY_DATA_IN => hub_reply_data_out(15 downto 0),
- INT_REPLY_PACKET_NUM_IN => hub_reply_packet_num_out(2 downto 0),
- INT_REPLY_READ_OUT => hub_reply_read_in(0),
+ INT_REPLY_DATAREADY_IN => cts_trg_reply_dataready_in,
+ INT_REPLY_DATA_IN => cts_trg_reply_data_in,
+ INT_REPLY_PACKET_NUM_IN => cts_trg_reply_packet_num_in,
+ INT_REPLY_READ_OUT => cts_trg_reply_read_out,
-- Status and control port
STAT_GEN => open,
io_error_in <= MEDIA_MED2INT(mii).stat_op(2 downto 0);
-- med_stat_op(mii*16+15 downto mii*16) <= MEDIA_MED2INT(mii).stat_op;
---------------------------------------------------------------------
--- IPU Channel
+-- Streaming Channels
---------------------------------------------------------------------
+ hub_reply_data_in(15 downto 0) <= (others => '0');
+ hub_reply_packet_num_in(2 downto 0) <= (others => '0');
+ hub_reply_dataready_in(0) <= '0';
+ hub_init_read_in(0) <= '1';
hub_reply_data_in(31 downto 16) <= (others => '0');
hub_reply_packet_num_in(5 downto 3) <= (others => '0');
hub_reply_dataready_in(1) <= '0';
hub_init_read_in(1) <= '1';
- THE_STREAMING : trb_net16_api_ipu_streaming
+ THE_STREAMING : entity work.trb_net16_api_ipu_streaming_accel
port map(
CLK => CLK,
RESET => reset_i,
CLK_EN => CLK_EN,
-
- -- Internal direction port
-
- FEE_INIT_DATA_OUT => hub_init_data_in(31 downto 16),
- FEE_INIT_DATAREADY_OUT => hub_init_dataready_in(1),
- FEE_INIT_PACKET_NUM_OUT => hub_init_packet_num_in(5 downto 3),
- FEE_INIT_READ_IN => hub_init_read_out(1),
-
- FEE_REPLY_DATA_IN => hub_reply_data_out(31 downto 16),
- FEE_REPLY_DATAREADY_IN => hub_reply_dataready_out(1),
- FEE_REPLY_PACKET_NUM_IN => hub_reply_packet_num_out(5 downto 3),
- FEE_REPLY_READ_OUT => hub_reply_read_in(1),
-
- CTS_INIT_DATA_IN => cts_init_data_out,
- CTS_INIT_DATAREADY_IN => cts_init_dataready_out,
- CTS_INIT_PACKET_NUM_IN => cts_init_packet_num_out,
- CTS_INIT_READ_OUT => cts_init_read_in,
-
- CTS_REPLY_DATA_OUT => cts_reply_data_in,
- CTS_REPLY_DATAREADY_OUT => cts_reply_dataready_in,
- CTS_REPLY_PACKET_NUM_OUT => cts_reply_packet_num_in,
- CTS_REPLY_READ_IN => cts_reply_read_out,
-
+-- TRG port
+ TRG_TO_FEE_DATA_OUT => hub_init_data_in(15 downto 0),
+ TRG_TO_FEE_DATAREADY_OUT => hub_init_dataready_in(0),
+ TRG_TO_FEE_PACKET_NUM_OUT => hub_init_packet_num_in(2 downto 0),
+ TRG_TO_FEE_READ_IN => hub_init_read_out(0),
+
+ TRG_FROM_FEE_DATA_IN => hub_reply_data_out(15 downto 0),
+ TRG_FROM_FEE_DATAREADY_IN => hub_reply_dataready_out(0),
+ TRG_FROM_FEE_PACKET_NUM_IN => hub_reply_packet_num_out(2 downto 0),
+ TRG_FROM_FEE_READ_OUT => hub_reply_read_in(0),
+
+ TRG_FROM_CTS_DATA_IN => cts_trg_init_data_out,
+ TRG_FROM_CTS_DATAREADY_IN => cts_trg_init_dataready_out,
+ TRG_FROM_CTS_PACKET_NUM_IN => cts_trg_init_packet_num_out,
+ TRG_FROM_CTS_READ_OUT => cts_trg_init_read_in,
+
+ TRG_TO_CTS_DATA_OUT => cts_trg_reply_data_in,
+ TRG_TO_CTS_DATAREADY_OUT => cts_trg_reply_dataready_in,
+ TRG_TO_CTS_PACKET_NUM_OUT => cts_trg_reply_packet_num_in,
+ TRG_TO_CTS_READ_IN => cts_trg_reply_read_out,
+
+-- DATA port
+ DAT_TO_FEE_DATA_OUT => hub_init_data_in(31 downto 16),
+ DAT_TO_FEE_DATAREADY_OUT => hub_init_dataready_in(1),
+ DAT_TO_FEE_PACKET_NUM_OUT => hub_init_packet_num_in(5 downto 3),
+ DAT_TO_FEE_READ_IN => hub_init_read_out(1),
+
+ DAT_FROM_FEE_DATA_IN => hub_reply_data_out(31 downto 16),
+ DAT_FROM_FEE_DATAREADY_IN => hub_reply_dataready_out(1),
+ DAT_FROM_FEE_PACKET_NUM_IN => hub_reply_packet_num_out(5 downto 3),
+ DAT_FROM_FEE_READ_OUT => hub_reply_read_in(1),
+
+ DAT_FROM_CTS_DATA_IN => cts_init_data_out,
+ DAT_FROM_CTS_DATAREADY_IN => cts_init_dataready_out,
+ DAT_FROM_CTS_PACKET_NUM_IN => cts_init_packet_num_out,
+ DAT_FROM_CTS_READ_OUT => cts_init_read_in,
+
+ DAT_TO_CTS_DATA_OUT => cts_reply_data_in,
+ DAT_TO_CTS_DATAREADY_OUT => cts_reply_dataready_in,
+ DAT_TO_CTS_PACKET_NUM_OUT => cts_reply_packet_num_in,
+ DAT_TO_CTS_READ_IN => cts_reply_read_out,
+
+--GBE Port
--Event information coming from CTS
CTS_NUMBER_OUT => CTS_NUMBER_OUT,
CTS_CODE_OUT => CTS_CODE_OUT,
CTS_READOUT_TYPE_OUT => CTS_READOUT_TYPE_OUT,
CTS_START_READOUT_OUT => CTS_START_READOUT_OUT,
- --Information sent to CTS
--status data, equipped with DHDR
CTS_DATA_IN => CTS_DATA_IN,
CTS_DATAREADY_IN => CTS_DATAREADY_IN,
FEE_STATUS_BITS_OUT => FEE_STATUS_BITS_OUT,
FEE_BUSY_OUT => FEE_BUSY_OUT,
+--Controls
+ BUS_RX => intbus_rx,
+ BUS_TX => intbus_tx,
+
MY_ADDRESS_IN => MY_ADDRESS_IN,
CTRL_SEQNR_RESET => common_ctrl(10)
);
+-------------------------------------------------------------------------------
+--Bus Handler
+-------------------------------------------------------------------------------
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+ generic map(
+ PORT_NUMBER => 2,
+ PORT_MASK_ENABLE => c_YES,
+ PORT_ADDRESSES => (0 => x"0000", 1 => x"4100", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 16, 1 => 8, others => 0)
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+
+ REGIO_RX => hubbus_rx,
+ REGIO_TX => hubbus_tx,
+
+ BUS_RX(0) => BUS_RX,
+ BUS_RX(1) => intbus_rx,
+
+ BUS_TX(0) => BUS_TX,
+ BUS_TX(1) => intbus_tx
+ );
---------------------------------------------------------------------
-- Slowcontrol injection via GbE
jspc29 / trbnet.git / commitdiff