assert (FIFO_DEPTH >= 8 and FIFO_DEPTH <= 15 and FIFO_WIDTH = 36)
or (FIFO_DEPTH >= 8 and FIFO_DEPTH <= 11 and FIFO_WIDTH = 18)
- report "Selected data buffer size not implemented" severity error;
+ report "Selected data buffer size not implemented: depth - "&integer'image(FIFO_DEPTH)& ", width + 4 : " &integer'image(FIFO_WIDTH) severity error;
gen_36_256 : if FIFO_WIDTH = 36 and FIFO_DEPTH = 8 generate
THE_FIFO : fifo_36x256_oreg
BLOCK ASYNCPATHS ;
BLOCK RD_DURING_WR_PATHS ;
- FREQUENCY PORT CLK_100_IN 100.000000 MHz ;
- FREQUENCY PORT CLK_125_IN 125.000000 MHz ;
-
- FREQUENCY PORT "ADCCLK_OUT_1" 20.000000 MHz ;
- FREQUENCY PORT "ADCCLK_OUT_2" 20.000000 MHz ;
- FREQUENCY PORT "ADCCLK_OUT_3" 20.000000 MHz ;
- FREQUENCY PORT "ADCCLK_OUT_4" 20.000000 MHz ;
- FREQUENCY PORT "ADCCLK_OUT_5" 20.000000 MHz ;
- FREQUENCY PORT "ADCCLK_OUT_6" 20.000000 MHz ;
-
- FREQUENCY PORT "DCO_IN_1" 100.000000 MHz ;
- FREQUENCY PORT "DCO_IN_2" 100.000000 MHz ;
- FREQUENCY PORT "DCO_IN_3" 100.000000 MHz ;
- FREQUENCY PORT "DCO_IN_4" 100.000000 MHz ;
- FREQUENCY PORT "DCO_IN_5" 100.000000 MHz ;
- FREQUENCY PORT "DCO_IN_6" 100.000000 MHz ;
-