-# Call . /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
-
TARGET=adcmv3
-FAMILYNAME=LatticeECP3
-DEVICENAME=LFE3-150EA
-PACKAGE=FPBGA672
-SPEEDGRADE=8
+FAMILYNAME=LATTICEECP2M
+DEVICENAME=LFE2M100E
+PACKAGE=FPBGA900
+SPEEDGRADE=6
TIMESTAMP=$(shell date '+%s')
VERSION=$(shell cat version-major-minor.txt)
.PHONY: clean
clean:
rm -rf workdir/*
+ rm -f workdir/.[a-z,A-Z]*
.PHONY: distclean
distclean:
# Bitgen
workdir/$(TARGET).bit: workdir/$(TARGET).ncd
+ @$(MAKE) report
+
@echo ""
@echo "----------------------------------------------------------------------"
@echo "-------------- Bitgen ------------------------------------------------"
cd workdir && \
bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $(TARGET).ncd \
$(TARGET).bit $(TARGET).prf
- @$(MAKE) report
+
@$(MAKE) error
# Place and Route (multipar)
cd workdir && \
par -f ../$(TARGET).p2t $(TARGET)_map.ncd $(TARGET).dir $(TARGET).prf
cp workdir/$(TARGET).dir/*.ncd workdir/$(TARGET).ncd
+ #
+ # Multipar geht gerade nicht
+ #par $(TARGET)_map.ncd $(TARGET).prf
+ #mv $(TARGET).prf.ncd $(TARGET).ncd
+ # par -f ../$(TARGET).p2t $(TARGET)_map.ncd $(TARGET).dir $(TARGET).prf
+ #cp workdir/$(TARGET).dir/*.ncd workdir/$(TARGET).ncd
+
# Mapper
workdir/$(TARGET)_map.ncd: workdir/$(TARGET).ngd $(TARGET).lpf
@echo "----------------------------------------------------------------------"
@echo "--------------- VHDL Compiler ----------------------------------------"
@echo "----------------------------------------------------------------------"
+
+ #$(SYNPLIFY)/bin/synplify_premier_dp -batch $TOPNAME.prj || \
+ # (grep "@E" workdir/$(TARGET).srr && exit 2)
synpwrap -prj $(TARGET).prj || \
(grep "@E" workdir/$(TARGET).srr && exit 2)
@echo "-------------- Setup Workdir -----------------------------------------"
@echo "----------------------------------------------------------------------"
mkdir -p workdir
- cd workdir && ../../base/linkdesignfiles.sh
+ #cd workdir && ../../base/linkdesignfiles.sh
cp $(TARGET).lpf workdir/$(TARGET).lpf
-# cat $(TARGET)_constraints.lpf >> workdir/$(TARGET).lpf
+ cat $(TARGET)_constraints.lpf >> workdir/$(TARGET).lpf
cp nodelist.txt workdir/
# Timing Report
LOCATE COMP "BP_SECTOR_1" SITE "AF13" ; # was "AF12"\r
IOBUF PORT "BP_SECTOR_1" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
LOCATE COMP "BP_SECTOR_0" SITE "AF15" ; # was "AF11"\r
-IOBUF PORT "BP_MODULE_0 IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+IOBUF PORT "BP_MODULE_0" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
\r
LOCATE COMP "BP_LED" SITE "AE8" ;\r
IOBUF PORT "BP_LED" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 ;\r
# alternative, if needed\r
# LOCATE COMP "EXT_IN_0" SITE "P28" ;\r
IOBUF PORT "EXT_IN_0" IO_TYPE=LVTTL33 ;\r
-LOCATE COMP "DBG_EXP_41" SITE "T27" ;\r
-LOCATE COMP "DBG_EXP_39" SITE "T26" ;\r
-LOCATE COMP "DBG_EXP_37" SITE "U26" ;\r
-LOCATE COMP "DBG_EXP_35" SITE "V25" ;\r
-LOCATE COMP "DBG_EXP_33" SITE "W25" ;\r
-LOCATE COMP "DBG_EXP_31" SITE "W26" ;\r
-LOCATE COMP "DBG_EXP_29" SITE "Y26" ;\r
-LOCATE COMP "DBG_EXP_27" SITE "Y27" ;\r
-LOCATE COMP "DBG_EXP_25" SITE "AB26" ;\r
-LOCATE COMP "DBG_EXP_23" SITE "AC27" ;\r
-LOCATE COMP "DBG_EXP_21" SITE "U25" ;\r
-LOCATE COMP "DBG_EXP_19" SITE "U28" ;\r
-LOCATE COMP "DBG_EXP_17" SITE "U27" ;\r
-LOCATE COMP "DBG_EXP_5" SITE "R28" ;\r
-LOCATE COMP "DBG_EXP_3" SITE "R27" ;\r
-LOCATE COMP "DBG_EXP_1" SITE "T28" ;\r
+# LOCATE COMP "DBG_EXP_41" SITE "T27" ;\r
+# LOCATE COMP "DBG_EXP_39" SITE "T26" ;\r
+# LOCATE COMP "DBG_EXP_37" SITE "U26" ;\r
+# LOCATE COMP "DBG_EXP_35" SITE "V25" ;\r
+# LOCATE COMP "DBG_EXP_33" SITE "W25" ;\r
+# LOCATE COMP "DBG_EXP_31" SITE "W26" ;\r
+# LOCATE COMP "DBG_EXP_29" SITE "Y26" ;\r
+# LOCATE COMP "DBG_EXP_27" SITE "Y27" ;\r
+# LOCATE COMP "DBG_EXP_25" SITE "AB26" ;\r
+# LOCATE COMP "DBG_EXP_23" SITE "AC27" ;\r
+# LOCATE COMP "DBG_EXP_21" SITE "U25" ;\r
+# LOCATE COMP "DBG_EXP_19" SITE "U28" ;\r
+# LOCATE COMP "DBG_EXP_17" SITE "U27" ;\r
+# LOCATE COMP "DBG_EXP_5" SITE "R28" ;\r
+# LOCATE COMP "DBG_EXP_3" SITE "R27" ;\r
+# LOCATE COMP "DBG_EXP_1" SITE "T28" ;\r
LOCATE COMP "UC_REBOOT" SITE "Y28" ; # was UC_FPGA3\r
IOBUF PORT "UC_REBOOT" IO_TYPE=LVTTL33 ;\r
# LOCATE COMP "UC_FPGA_2" SITE "W27" ;\r
# I/O bank 2 - 3.30V\r
# SFP control, LEDs, 1Wire ID, debug pins (SMC50)\r
######################################################################\r
-LOCATE COMP "DBG_EXP_43" SITE "R26" ;\r
-LOCATE COMP "DBG_EXP_42" SITE "P25" ;\r
-LOCATE COMP "DBG_EXP_40" SITE "P26" ;\r
-LOCATE COMP "DBG_EXP_38" SITE "N25" ;\r
-LOCATE COMP "DBG_EXP_36" SITE "M25" ;\r
-LOCATE COMP "DBG_EXP_34" SITE "M26" ;\r
-LOCATE COMP "DBG_EXP_32" SITE "L25" ;\r
-LOCATE COMP "DBG_EXP_30" SITE "L26" ;\r
-LOCATE COMP "DBG_EXP_28" SITE "K25" ;\r
-LOCATE COMP "DBG_EXP_26" SITE "J26" ;\r
-LOCATE COMP "DBG_EXP_24" SITE "H25" ;\r
-LOCATE COMP "DBG_EXP_22" SITE "H26" ;\r
-LOCATE COMP "DBG_EXP_20" SITE "H24" ;\r
-LOCATE COMP "DBG_EXP_18" SITE "G26" ;\r
-LOCATE COMP "DBG_EXP_16" SITE "G25" ;\r
-LOCATE COMP "DBG_EXP_15" SITE "L27" ;\r
-LOCATE COMP "DBG_EXP_14" SITE "L28" ;\r
-LOCATE COMP "DBG_EXP_13" SITE "M28" ;\r
-LOCATE COMP "DBG_EXP_12" SITE "K24" ;\r
-LOCATE COMP "DBG_EXP_11" SITE "M27" ;\r
-LOCATE COMP "DBG_EXP_10" SITE "M30" ;\r
-LOCATE COMP "DBG_EXP_9" SITE "N26" ;\r
-LOCATE COMP "DBG_EXP_8" SITE "M29" ;\r
-LOCATE COMP "DBG_EXP_7" SITE "P27" ;\r
-LOCATE COMP "DBG_EXP_6" SITE "L30" ;\r
-LOCATE COMP "DBG_EXP_4" SITE "L29" ;\r
-LOCATE COMP "DBG_EXP_2" SITE "K30" ;\r
-LOCATE COMP "DBG_EXP_0" SITE "K29" ;\r
+# LOCATE COMP "DBG_EXP_43" SITE "R26" ;\r
+# LOCATE COMP "DBG_EXP_42" SITE "P25" ;\r
+# LOCATE COMP "DBG_EXP_40" SITE "P26" ;\r
+# LOCATE COMP "DBG_EXP_38" SITE "N25" ;\r
+# LOCATE COMP "DBG_EXP_36" SITE "M25" ;\r
+# LOCATE COMP "DBG_EXP_34" SITE "M26" ;\r
+# LOCATE COMP "DBG_EXP_32" SITE "L25" ;\r
+# LOCATE COMP "DBG_EXP_30" SITE "L26" ;\r
+# LOCATE COMP "DBG_EXP_28" SITE "K25" ;\r
+# LOCATE COMP "DBG_EXP_26" SITE "J26" ;\r
+# LOCATE COMP "DBG_EXP_24" SITE "H25" ;\r
+# LOCATE COMP "DBG_EXP_22" SITE "H26" ;\r
+# LOCATE COMP "DBG_EXP_20" SITE "H24" ;\r
+# LOCATE COMP "DBG_EXP_18" SITE "G26" ;\r
+# LOCATE COMP "DBG_EXP_16" SITE "G25" ;\r
+# LOCATE COMP "DBG_EXP_15" SITE "L27" ;\r
+# LOCATE COMP "DBG_EXP_14" SITE "L28" ;\r
+# LOCATE COMP "DBG_EXP_13" SITE "M28" ;\r
+# LOCATE COMP "DBG_EXP_12" SITE "K24" ;\r
+# LOCATE COMP "DBG_EXP_11" SITE "M27" ;\r
+# LOCATE COMP "DBG_EXP_10" SITE "M30" ;\r
+# LOCATE COMP "DBG_EXP_9" SITE "N26" ;\r
+# LOCATE COMP "DBG_EXP_8" SITE "M29" ;\r
+# LOCATE COMP "DBG_EXP_7" SITE "P27" ;\r
+# LOCATE COMP "DBG_EXP_6" SITE "L30" ;\r
+# LOCATE COMP "DBG_EXP_4" SITE "L29" ;\r
+# LOCATE COMP "DBG_EXP_2" SITE "K30" ;\r
+# LOCATE COMP "DBG_EXP_0" SITE "K29" ;\r
LOCATE COMP "FPGA_LED_6" SITE "G28" ;\r
IOBUF PORT "FPGA_LED_6" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
LOCATE COMP "FPGA_LED_5" SITE "G27" ;\r
# simplify IO definitions\r
######################################################################\r
# Debug header (50pin SMC connector)\r
-DEFINE PORT GROUP "debug_header_group" "DBG_EXP_{0:43}" ;\r
-IOBUF GROUP "debug_header_group" IO_TYPE=LVCMOS33 PULLMODE=DOWN SLEWRATE=FAST ;\r
+# DEFINE PORT GROUP "debug_header_group" "DBG_EXP_{0:43}" ;\r
+# IOBUF GROUP "debug_header_group" IO_TYPE=LVCMOS33 PULLMODE=DOWN DRIVE=4 SLEWRATE=FAST ;\r
\r
# LED drivers\r
# DEFINE PORT GROUP "led_output_group" "FPGA_LED*" ;\r
--- /dev/null
+-w
+-i 2
+-l 5
+-n 2
+-t 10
+-s 1
+-c 1
+-e 2
+-stopzero
+-m nodelist.txt
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
# add_file options
add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib work "source/adcmv3_components.vhd"
-add_file -vhdl -lib work "source/adcmv3_components2.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "design/adcmv3_components.vhd"
# ADCMv3 design files
-# Top level entity
-add_file -vhdl -lib work "adcmv3.vhd"
-
-add_file -vhdl -lib work "source/dbg_reg.vhd"
-add_file -vhdl -lib work "source/reset_handler.vhd"
-add_file -vhdl -lib work "source/reboot_handler.vhd"
-add_file -vhdl -lib work "source/pulse_sync.vhd"
-add_file -vhdl -lib work "source/state_sync.vhd"
-add_file -vhdl -lib work "source/apv_sync_handler.vhd"
-add_file -vhdl -lib work "source/apv_trg_handler.vhd"
-add_file -vhdl -lib work "source/eds_buf.vhd"
-add_file -vhdl -lib work "source/max_data.vhd"
-add_file -vhdl -lib work "source/real_trg_handler.vhd"
-add_file -vhdl -lib work "source/pulse_stretch.vhd"
-add_file -vhdl -lib work "source/apv_trgctrl.vhd"
-add_file -vhdl -lib work "source/adc_channel_select.vhd"
-add_file -vhdl -lib work "source/adc_crossover.vhd"
-add_file -vhdl -lib work "source/adc_twochannels.vhd"
-add_file -vhdl -lib work "source/adc_data_handler.vhd"
-add_file -vhdl -lib work "source/apv_raw_buffer.vhd"
-add_file -vhdl -lib work "source/apv_lock_sm.vhd"
-add_file -vhdl -lib work "source/apv_digital.vhd"
-add_file -vhdl -lib work "source/apv_locker.vhd"
-add_file -vhdl -lib work "source/raw_buf_stage.vhd"
-add_file -vhdl -lib work "source/apv_pc_nc_alu.vhd"
-add_file -vhdl -lib work "source/buf_toc.vhd"
-add_file -vhdl -lib work "source/ref_row_sel.vhd"
-add_file -vhdl -lib work "source/frmctr_check.vhd"
-add_file -vhdl -lib work "source/ped_corr_ctrl.vhd"
-add_file -vhdl -lib work "source/ipu_fifo_stage.vhd"
-add_file -vhdl -lib work "source/slv_register.vhd"
-add_file -vhdl -lib work "source/slv_adc_snoop.vhd"
-add_file -vhdl -lib work "source/slv_half_register.vhd"
-add_file -vhdl -lib work "source/slv_status.vhd"
-add_file -vhdl -lib work "source/slv_status_bank.vhd"
-add_file -vhdl -lib work "source/slv_register_bank.vhd"
-add_file -vhdl -lib work "source/spi_real_slim.vhd"
-add_file -vhdl -lib work "source/spi_adc_master.vhd"
-add_file -vhdl -lib work "source/onewire_master.vhd"
-add_file -vhdl -lib work "source/slv_onewire_memory.vhd"
-add_file -vhdl -lib work "source/i2c_gstart.vhd"
-add_file -vhdl -lib work "source/i2c_sendb.vhd"
-add_file -vhdl -lib work "source/i2c_slim.vhd"
-add_file -vhdl -lib work "source/i2c_master.vhd"
-add_file -vhdl -lib work "source/slv_ped_thr_mem.vhd"
-add_file -vhdl -lib work "source/slave_bus.vhd"
-add_file -vhdl -lib work "source/rich_trb.vhd"
-
-# Addons
-add_file -vhdl -lib work "source/debug_multiplexer.vhd"
-
-# Core files
-add_file -vhdl -lib work "cores/adc_ch_in.vhd"
-add_file -vhdl -lib work "cores/eds_buffer_dpram.vhd"
-add_file -vhdl -lib work "cores/crossover.vhd"
-add_file -vhdl -lib work "cores/frame_status_mem.vhd"
-add_file -vhdl -lib work "cores/input_bram.vhd"
-add_file -vhdl -lib work "cores/decoder_8bit.vhd"
-add_file -vhdl -lib work "cores/adc_apv_map_mem.vhd"
-add_file -vhdl -lib work "cores/fifo_1kx18.vhd"
-add_file -vhdl -lib work "cores/fifo_2kx27.vhd"
-add_file -vhdl -lib work "cores/adc_snoop_mem.vhd"
-add_file -vhdl -lib work "cores/apv_adc_map_mem.vhd"
-add_file -vhdl -lib work "cores/onewire_spare_one.vhd"
-add_file -vhdl -lib work "cores/adc_onewire_map_mem.vhd"
-add_file -vhdl -lib work "cores/ped_thr_true.vhd"
-add_file -vhdl -lib work "cores/sync_pll_40m.vhd"
-add_file -vhdl -lib work "cores/dll_100m.vhd"
-add_file -vhdl -lib work "cores/pll_40m.vhd"
-add_file -vhdl -lib work "cores/slv_onewire_dpram.vhd"
+add_file -vhdl -lib work "design/adcmv3.vhd"
+add_file -vhdl -lib work "design/dbg_reg.vhd"
+add_file -vhdl -lib work "design/reset_handler.vhd"
+add_file -vhdl -lib work "design/reboot_handler.vhd"
+add_file -vhdl -lib work "design/pulse_sync.vhd"
+add_file -vhdl -lib work "design/adc_ch_in.vhd"
+add_file -vhdl -lib work "design/state_sync.vhd"
+add_file -vhdl -lib work "design/apv_sync_handler.vhd"
+add_file -vhdl -lib work "design/apv_trg_handler.vhd"
+add_file -vhdl -lib work "design/eds_buffer_dpram.vhd"
+add_file -vhdl -lib work "design/eds_buf.vhd"
+add_file -vhdl -lib work "design/max_data.vhd"
+add_file -vhdl -lib work "design/real_trg_handler.vhd"
+add_file -vhdl -lib work "design/pulse_stretch.vhd"
+add_file -vhdl -lib work "design/apv_trgctrl.vhd"
+add_file -vhdl -lib work "design/adc_channel_select.vhd"
+add_file -vhdl -lib work "design/crossover.vhd"
+add_file -vhdl -lib work "design/adc_crossover.vhd"
+add_file -vhdl -lib work "design/adc_twochannels.vhd"
+add_file -vhdl -lib work "design/adc_data_handler.vhd"
+add_file -vhdl -lib work "design/frame_status_mem.vhd"
+add_file -vhdl -lib work "design/input_bram.vhd"
+add_file -vhdl -lib work "design/apv_raw_buffer.vhd"
+add_file -vhdl -lib work "design/apv_lock_sm.vhd"
+add_file -vhdl -lib work "design/apv_digital.vhd"
+add_file -vhdl -lib work "design/apv_locker.vhd"
+add_file -vhdl -lib work "design/raw_buf_stage.vhd"
+add_file -vhdl -lib work "design/decoder_8bit.vhd"
+add_file -vhdl -lib work "design/apv_pc_nc_alu.vhd"
+add_file -vhdl -lib work "design/buf_toc.vhd"
+add_file -vhdl -lib work "design/ref_row_sel.vhd"
+add_file -vhdl -lib work "design/frmctr_check.vhd"
+add_file -vhdl -lib work "design/ped_corr_ctrl.vhd"
+add_file -vhdl -lib work "design/adc_apv_map_mem.vhd"
+add_file -vhdl -lib work "design/fifo_1kx18.vhd"
+add_file -vhdl -lib work "design/fifo_2kx27.vhd"
+add_file -vhdl -lib work "design/ipu_fifo_stage.vhd"
+add_file -vhdl -lib work "design/slv_register.vhd"
+add_file -vhdl -lib work "design/adc_snoop_mem.vhd"
+add_file -vhdl -lib work "design/slv_adc_snoop.vhd"
+add_file -vhdl -lib work "design/slv_half_register.vhd"
+add_file -vhdl -lib work "design/slv_status.vhd"
+add_file -vhdl -lib work "design/slv_status_bank.vhd"
+add_file -vhdl -lib work "design/apv_adc_map_mem.vhd"
+add_file -vhdl -lib work "design/slv_register_bank.vhd"
+add_file -vhdl -lib work "design/spi_real_slim.vhd"
+add_file -vhdl -lib work "design/spi_adc_master.vhd"
+add_file -vhdl -lib work "design/slv_onewire_dpram.vhd"
+add_file -vhdl -lib work "design/onewire_master.vhd"
+add_file -vhdl -lib work "design/onewire_spare_one.vhd"
+add_file -vhdl -lib work "design/adc_onewire_map_mem.vhd"
+add_file -vhdl -lib work "design/slv_onewire_memory.vhd"
+add_file -vhdl -lib work "design/i2c_gstart.vhd"
+add_file -vhdl -lib work "design/i2c_sendb.vhd"
+add_file -vhdl -lib work "design/i2c_slim.vhd"
+add_file -vhdl -lib work "design/i2c_master.vhd"
+add_file -vhdl -lib work "design/ped_thr_true.vhd"
+add_file -vhdl -lib work "design/slv_ped_thr_mem.vhd"
+add_file -vhdl -lib work "design/slave_bus.vhd"
+add_file -vhdl -lib work "design/rich_trb.vhd"
+add_file -vhdl -lib work "design/sync_pll_40m.vhd"
+add_file -vhdl -lib work "design/dll_100m.vhd"
+add_file -vhdl -lib work "design/pll_40m.vhd"
# TrbNet design files
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd"
-# add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd"
-# add_file -vhdl -lib work "source/sfp_rx_handler.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd"
+add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
+add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd"
+
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd"
+# add_file -vhdl -lib work "design/sfp_rx_handler.vhd"
# implementation: "workdir"
impl -add workdir -type fpga
+
# device options
set_option -technology LATTICE-ECP2M
set_option -part LFE2M100E
set_option -vlog_std v2001
set_option -project_relative_includes 1
impl -active "workdir"
-
+++ /dev/null
-#!/bin/sh
-TOPNAME=adcmv3
-
-rm -f workdir/${TOPNAME}.alt
-rm -f workdir/${TOPNAME}.bgn
-rm -f workdir/${TOPNAME}.bit
-rm -f workdir/${TOPNAME}.edf
-rm -f workdir/${TOPNAME}.fse
-rm -f workdir/${TOPNAME}.mrp
-rm -f workdir/${TOPNAME}.ncd
-rm -f workdir/${TOPNAME}.ngd
-rm -f workdir/${TOPNAME}.ngo
-rm -f workdir/${TOPNAME}.ngy
-rm -f workdir/${TOPNAME}.pad
-rm -f workdir/${TOPNAME}.par
-rm -f workdir/${TOPNAME}.sr?
-rm -f workdir/${TOPNAME}.tlg
-rm -f workdir/${TOPNAME}.twr*
--- /dev/null
+#!/usr/bin/perl
+###########################################
+# Script file to run the flow
+###########################################
+
+# You need the tunnels before!
+
+use Data::Dumper;
+use warnings;
+use strict;
+
+# Path settings for ispLEVER tools
+my $lattice_path = '/usr/local/opt/synplify/8/isptools';
+
+# Path settings for SynplifyPRO
+my $synplify_path = '/usr/local/opt/synplify/premier';
+# my $synplify_path = '/scratch/rich/synplify/D-2009.12';
+
+use FileHandle;
+
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}="27000\@localhost";
+
+# Design top level entity
+my $TOPNAME="adcmv3";
+
+# FPGA chip description
+my $FAMILYNAME="LATTICEECP2M";
+my $DEVICENAME="LFE2M100E";
+my $PACKAGE="FPBGA900";
+my $SPEEDGRADE="6";
+
+# benchmarking
+my $CTIME_String = localtime(time);
+print "Script started: $CTIME_String\n";
+system("echo $CTIME_String > workdir/benchmark.txt");
+
+# cleanup in workdir
+system("rm workdir/$TOPNAME.alt");
+system("rm workdir/$TOPNAME.bgn");
+system("rm workdir/$TOPNAME.bit");
+system("rm workdir/$TOPNAME.edf");
+system("rm workdir/$TOPNAME.fse");
+system("rm workdir/$TOPNAME.mrp");
+system("rm workdir/$TOPNAME.ncd");
+system("rm workdir/$TOPNAME.ngd");
+system("rm workdir/$TOPNAME.ngo");
+system("rm workdir/$TOPNAME.ngy");
+system("rm workdir/$TOPNAME.pad");
+system("rm workdir/$TOPNAME.par");
+system("rm workdir/$TOPNAME.sr?");
+system("rm workdir/$TOPNAME.tlg");
+system("rm workdir/$TOPNAME.twr*");
+
+# Create full lpf file
+system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf");
+system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");
+
+# Generate timestamp for slowcontrol readback
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+ constant VERSION_NUMBER_TIME : integer := $t;
+
+end package version;
+EOF
+$fh->close;
+
+# Run Synplify on the design
+system("env| grep LM_");
+my $r = "";
+my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME".".prj";
+$r=execute($c, "do_not_exit" );
+
+# Check for errors
+chdir "workdir";
+$fh = new FileHandle("<$TOPNAME".".srr");
+my @a = <$fh>;
+$fh -> close;
+
+foreach (@a)
+{
+ if(/\@E:/)
+ {
+ $c="cat $TOPNAME.srr";
+ system($c);
+ print "ERROR_ERROR_ERROR_ERROR_ERROR\n";
+ exit 129;
+ }
+}
+
+# ispLEVER design flow starts here
+# new license file must be given
+$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de";
+
+# EDIF2NGD
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+execute($c);
+
+# NGDBUILD
+$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+execute($c);
+
+# MAP
+my $tpmap = $TOPNAME . "_map" ;
+$c=qq|$lattice_path/ispfpga/bin/lin/map -noinferGSR -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf" -tdm -td_pack|;
+execute($c);
+
+system("rm $TOPNAME.ncd");
+
+# MULTIPAR
+
+my $fh2 = new FileHandle(">$TOPNAME.p2t");
+die "could not open file" if (! defined $fh2);
+print $fh2 <<EOF;
+
+-w
+-i 5
+-l 5
+-n 8
+-t 1
+-s 1
+-c 1
+-e 2
+-m nodelist.txt
+-exp parCDP=1
+-exp parCDR=1
+-exp parPlcInLimit=0
+-exp parPlcInNeighborSize=1
+-exp parPathBased=ON
+-exp parHold=ON
+
+EOF
+$fh2->close;
+
+######################################################################
+# -w # overwrite files
+# -i 15 # maximum number of routing attempts
+# -l 5 # effort level (1-5)
+# -n 1 # starting cost table (n=0 loop)
+# -y # delay summary report
+# -s 12 # number of best results to save
+# -t 1 # start placement with cost table X
+# -c 1 # number of cost-based cleanup passes of the router
+# -e 2 # number of delay-based cleanup passes of the router
+# -m nodelist.txt #
+# -exp parCDP=1 #
+# -exp parCDR=1 #
+# -exp parPlcInLimit=0 #
+# -exp parPlcInNeighborSize=1 #
+# -exp parPathBased=ON #
+# -exp parHold=ON #
+# -exp parHoldLimit=10000 #
+# -exp paruseNBR=1 #
+######################################################################
+
+# real multipar
+$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
+execute($c);
+
+# IOR IO Timing Report
+#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+#execute($c);
+
+# TWR Timing Report (setup)
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+# TWR Timing Report (hold)
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+# BitGen
+#$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+chdir "..";
+
+$CTIME_String = localtime(time);
+print "Script ended: $CTIME_String\n";
+system("echo $CTIME_String >> workdir/benchmark.txt");
+
+exit;
+
+sub execute {
+ my ($c, $op) = @_;
+ #print "option: $op \n";
+ $op = "" if(!$op);
+ print "\n\ncommand to execute: $c \n";
+ $r=system($c);
+ if($r) {
+ print "$!";
+ if($op ne "do_not_exit") {
+ exit;
+ }
+ }
+
+ return $r;
+
+}
U_SPI_CS : out std_logic; -- OK -- chip select for SPI boot FlashROM\r
U_SPI_SCK : out std_logic; -- OK -- clock\r
U_SPI_SDI : out std_logic; -- OK -- connects to SI on the FlashROM\r
- U_SPI_SDO : in std_logic; -- OK -- connects to SO on the FlashROM\r
+ U_SPI_SDO : in std_logic -- OK -- connects to SO on the FlashROM\r
-- Debug connections\r
- DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header\r
+-- DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header\r
);\r
end;\r
\r
signal adc_ctrl_reg : reg_16bit_t;\r
signal adc_stat_reg : reg_16bit_t;\r
signal raw_buf_dbg : reg_16bit_t;\r
+\r
+--signal debug : std_logic_vector(42 downto 0);\r
+--signal debug_q : std_logic_vector(42 downto 0);\r
+--signal debug_qq : std_logic_vector(42 downto 0);\r
+--signal debug_clk : std_logic;\r
\r
-- LVL1 application interface\r
signal lvl1_trg_type : std_logic_vector(3 downto 0);\r
\r
signal tick_10s : std_logic;\r
\r
--- Debug Multiplexer\r
-signal debug_o : std_logic_vector(33 downto 0);\r
-\r
begin\r
\r
\r
--------------------------------------------------------------------------------\r
--- Debug Out \r
--------------------------------------------------------------------------------\r
- \r
- DEBUG: for I in 0 to 15 generate\r
- debug_o(2 * I) <= sysclk;\r
- debug_o(2 * I + 1) <= not sysclk;\r
- end generate DEBUG;\r
- debug_o(32) <= sysclk;\r
- debug_o(33) <= not sysclk;\r
- \r
- DBG_EXP(31 downto 0) <= debug_o(31 downto 0);\r
- DBG_EXP(37 downto 32) <= (others => '0');\r
- DBG_EXP(38) <= debug_o(32);\r
- DBG_EXP(41 downto 49) <= (others => '0');\r
- DBG_EXP(42) <= debug_o(33);\r
- DBG_EXP(43) <= '0';\r
- \r
----------------------------------------\r
-- Async reset assignment --\r
----------------------------------------\r
GEN_ADC_LVDS_ON: for i in 0 to 15 generate\r
adc_on(i) <= adc_ctrl_reg(i)(0);\r
lvds_on(i) <= adc_ctrl_reg(i)(1);\r
+-- adc_stat_reg(i) <= raw_buf_dbg(i);\r
adc_stat_reg(i) <= buf_data(i)(37 downto 30) & raw_buf_debug(i*4+3 downto i*4+0) & std_logic_vector(to_unsigned(i,4));\r
broken_buf(i) <= buf_data(i)(36); -- BUF_BROKEN bit\r
apv_error(i) <= buf_data(i)(26); -- APV error frame bit\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+--use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.adcmv3_components.all;\r
+\r
+library ecp2m;\r
+use ecp2m.components.all;\r
+\r
+entity adcmv3 is\r
+port( \r
+ CLK100M : in std_logic; -- OK -- 100MHz LVDS clock \r
+ -- trigger inputs\r
+ EXT_IN : in std_logic_vector(3 downto 0); -- OK -- external triggers\r
+ -- APV stuff\r
+ APV0A_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock \r
+ APV0B_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock \r
+ APV0A_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out\r
+ APV0B_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out\r
+ APV0_RST : out std_logic; -- OK -- APV bank 0: reset signal, low active\r
+ APV0_SDA : inout std_logic; -- OK -- APV bank 0: I2C bus SDA\r
+ APV0_SCL : inout std_logic; -- OK -- APV bank 0: I2C bus SCL\r
+ ENA_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers\r
+ APV1A_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock\r
+ APV1B_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock\r
+ APV1A_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out\r
+ APV1B_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out\r
+ APV1_RST : out std_logic; -- OK -- APV bank 1: reset signal, low active\r
+ APV1_SDA : inout std_logic; -- OK -- APV bank 1: I2C bus SDA\r
+ APV1_SCL : inout std_logic; -- OK -- APV bank 1: I2C bus SCL\r
+ ENB_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers\r
+ -- ADC0 stuff\r
+ ADC0_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL\r
+ ADC0_RST : out std_logic; -- OK -- ADC reset signal\r
+ ADC0_PD : out std_logic; -- OK -- ADC powerdown signal\r
+ ADC0_CS : out std_logic; -- OK -- ADC /CS signal\r
+ ADC0_SDI : out std_logic; -- OK -- ADC serial data in\r
+ ADC0_SCK : out std_logic; -- OK -- ADC serial clock\r
+ ADC0_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock\r
+ ADC0_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock\r
+ ADC0_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams\r
+ -- ADC1 stuff\r
+ ADC1_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL\r
+ ADC1_RST : out std_logic; -- OK -- ADC reset signal\r
+ ADC1_PD : out std_logic; -- OK -- ADC powerdown signal\r
+ ADC1_CS : out std_logic; -- OK -- ADC /CS signal\r
+ ADC1_SDI : out std_logic; -- OK -- ADC serial data in\r
+ ADC1_SCK : out std_logic; -- OK -- ADC serial clock\r
+ ADC1_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock\r
+ ADC1_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock\r
+ ADC1_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams\r
+ -- uC connections\r
+ UC_RESET : in std_logic; -- OK -- uC reset, high active\r
+ UC_REBOOT : out std_logic; -- OK -- was UC_FPGA(3), requests FPGA reboot\r
+ -- SerDes pins \r
+ HDINN2 : in std_logic; -- highspeed INPUT\r
+ HDINP2 : in std_logic; --\r
+ HDOUTN2 : out std_logic; -- highspeed OUTPUT\r
+ HDOUTP2 : out std_logic; -- \r
+ SD_PRESENT : in std_logic; -- OK -- Present signal from SFP\r
+ SD_LOS : in std_logic; -- OK -- Loss Of Signal from SFP\r
+ SD_TXDIS : out std_logic; -- OK -- SFP transmitter disable\r
+ ADCM_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on ADCM\r
+ -- Backplane sense wires\r
+ BP_MODULE : in std_logic_vector(3 downto 0); -- OK -- module number input from backplane\r
+ BP_SECTOR : in std_logic_vector(3 downto 0); -- OK -- sector number input from backplane\r
+ BP_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on backplane \r
+ BP_LED : out std_logic; -- OK -- backplane LED \r
+ -- LEDs\r
+ FPGA_LED : out std_logic_vector(6 downto 3); -- OK -- general purpose LEDS\r
+ FPGA_LED_RXD : out std_logic; -- OK -- FPGA_LED(2)\r
+ FPGA_LED_TXD : out std_logic; -- OK -- FPGA_LED(1)\r
+ FPGA_LED_LINK : out std_logic; -- OK -- FPGA_LED(0)\r
+ FPGA_LED_PLL : out std_logic; -- OK -- PLL locked \r
+ FPGA_LED_ADC : out std_logic_vector(1 downto 0); -- OK -- ADCx OK LED \r
+ -- 1Wire chips on APV FEs\r
+ APV0_1W : inout std_logic_vector(7 downto 0);\r
+ APV1_1W : inout std_logic_vector(7 downto 0);\r
+ -- SPI FlashROM connections\r
+ U_SPI_CS : out std_logic; -- OK -- chip select for SPI boot FlashROM\r
+ U_SPI_SCK : out std_logic; -- OK -- clock\r
+ U_SPI_SDI : out std_logic; -- OK -- connects to SI on the FlashROM\r
+ U_SPI_SDO : in std_logic -- OK -- connects to SO on the FlashROM\r
+ -- Debug connections\r
+-- DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header\r
+);\r
+end;\r
+\r
+architecture adcmv3 of adcmv3 is\r
+\r
+-- Signals\r
+-- Clock related signals\r
+signal clk100m_locked : std_logic; -- not needed at the moment\r
+signal sysclk : std_logic; -- clean 100MHz for distribution\r
+\r
+signal adc0_ce : std_logic;\r
+signal adc0_valid : std_logic;\r
+signal adc0_swap : std_logic;\r
+signal adc0_reset : std_logic;\r
+signal adc0_powerdown : std_logic;\r
+signal adc1_ce : std_logic;\r
+signal adc1_valid : std_logic;\r
+signal adc1_swap : std_logic;\r
+signal adc1_reset : std_logic;\r
+signal adc1_powerdown : std_logic;\r
+\r
+signal clk_adc : std_logic; -- 40MHz for ADC operation\r
+signal clk_apv : std_logic; -- 40MHz for APV operation (phase shiftable!)\r
+signal clk40m_locked : std_logic;\r
+signal clk40m_reset : std_logic;\r
+\r
+signal async_reset : std_logic;\r
+\r
+-- APV related signals\r
+signal apv_sda_out : std_logic; -- APV SDA\r
+signal apv_sda_in : std_logic;\r
+signal apv_scl_out : std_logic; -- APV SCL\r
+signal apv_scl_in : std_logic;\r
+signal apv_trg : std_logic; -- real APV trigger signal\r
+signal apv_sync : std_logic; -- artificial signal\r
+signal apv_frame_reqd : std_logic; -- one 100MHz pulse per requested frame\r
+signal apv0_reset : std_logic;\r
+signal apv1_reset : std_logic;\r
+signal frontend_reset : std_logic;\r
+signal apv_reset : std_logic;\r
+signal adc_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8]\r
+signal lvds_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8]\r
+\r
+-- Control signals\r
+signal ctrl_pll : std_logic_vector(15 downto 0); -- PLL control register\r
+signal status_pll : std_logic_vector(15 downto 0); -- PLL status register\r
+signal ctrl_trg : std_logic_vector(31 downto 0); -- TRG control register\r
+signal ctrl_lvl : std_logic_vector(31 downto 0); -- LVL control register\r
+ \r
+signal ctrl_bitlow : std_logic_vector(11 downto 0); -- BIT_LOW setting for APV digital header\r
+signal ctrl_bithigh : std_logic_vector(11 downto 0); -- BIT_HIGH setting for APV digital header\r
+signal ctrl_flatlow : std_logic_vector(11 downto 0); -- FLAT_LOW setting\r
+signal ctrl_flathigh : std_logic_vector(11 downto 0); -- FLAT_HIGH setting\r
+\r
+signal maximum_trg : std_logic_vector(3 downto 0);\r
+\r
+signal raw_buf_full : std_logic;\r
+signal eds_buf_full : std_logic;\r
+signal eds_buf_level : std_logic_vector(4 downto 0);\r
+\r
+-- regIO data bus\r
+signal regio_addr : std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);\r
+signal regio_read_enable : std_logic;\r
+signal regio_write_enable : std_logic;\r
+signal regio_data_wr : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
+signal regio_data_rd : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
+signal regio_dataready : std_logic;\r
+signal regio_no_more_data : std_logic;\r
+signal regio_write_ack : std_logic;\r
+signal regio_unknown_addr : std_logic;\r
+signal regio_timeout : std_logic;\r
+\r
+-- common status / control registers from RegIO\r
+signal common_stat_reg : std_logic_vector(63 downto 0);\r
+signal common_ctrl_reg : std_logic_vector(95 downto 0);\r
+\r
+-- user defined "quick'n'dirty" registers\r
+signal simple_status : std_logic_vector(127 downto 0);\r
+signal simple_control : std_logic_vector(63 downto 0);\r
+\r
+-- debug signals\r
+signal test_reg : std_logic_vector(31 downto 0);\r
+signal trgctrl_debug : std_logic_vector(63 downto 0);\r
+signal raw_buf_debug : std_logic_vector(63 downto 0);\r
+--signal trbrich_debug : std_logic_vector(63 downto 0);\r
+--signal slave_debug : std_logic_vector(63 downto 0);\r
+--signal fifo_debug : std_logic_vector(63 downto 0);\r
+\r
+-- EDS / BUFFER signals (raw buf -> ped corr)\r
+signal eds_data : std_logic_vector(39 downto 0);\r
+signal eds_avail : std_logic;\r
+signal eds_done : std_logic;\r
+signal buf_addr : std_logic_vector(6 downto 0);\r
+signal buf_done : std_logic;\r
+signal buf_tick : std_logic_vector(15 downto 0);\r
+signal buf_start : std_logic_vector(15 downto 0);\r
+signal buf_ready : std_logic_vector(15 downto 0); -- just for debugging!\r
+\r
+type reg_38bit_t is array (0 to 15) of std_logic_vector(37 downto 0);\r
+signal buf_data : reg_38bit_t;\r
+\r
+signal thr_addr : std_logic_vector(6 downto 0);\r
+type reg_18bit_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
+signal thr_data : reg_18bit_t;\r
+signal ped_data : reg_18bit_t;\r
+\r
+-- FIFO / DHDR signals (ped corr -> ipu stage)\r
+signal dhdr_data : std_logic_vector(31 downto 0);\r
+signal dhdr_length : std_logic_vector(15 downto 0);\r
+signal dhdr_store : std_logic;\r
+signal dhdr_buf_full : std_logic;\r
+\r
+signal fifo_start : std_logic;\r
+signal fifo_done : std_logic;\r
+signal fifo_we : std_logic_vector(15 downto 0);\r
+signal fifo_space_req : std_logic_vector(11 downto 0);\r
+type reg_40bit_t is array (0 to 15) of std_logic_vector(39 downto 0);\r
+signal fifo_data : reg_40bit_t;\r
+type reg_32bit_t is array (0 to 15) of std_logic_vector(31 downto 0);\r
+signal fifo_status : reg_32bit_t;\r
+\r
+signal ipu_handler_status : std_logic_vector(31 downto 0);\r
+signal lvl1_release_status : std_logic_vector(31 downto 0);\r
+\r
+-- APV control / status signals\r
+type reg_16bit_t is array (0 to 15) of std_logic_vector(15 downto 0);\r
+signal adc_ctrl_reg : reg_16bit_t;\r
+signal adc_stat_reg : reg_16bit_t;\r
+\r
+--signal debug : std_logic_vector(42 downto 0);\r
+--signal debug_q : std_logic_vector(42 downto 0);\r
+--signal debug_qq : std_logic_vector(42 downto 0);\r
+--signal debug_clk : std_logic;\r
+ \r
+-- LVL1 application interface\r
+signal lvl1_trg_type : std_logic_vector(3 downto 0);\r
+signal lvl1_trg_received : std_logic;\r
+signal lvl1_trg_number : std_logic_vector(15 downto 0);\r
+signal lvl1_trg_code : std_logic_vector(7 downto 0);\r
+signal lvl1_trg_information : std_logic_vector(23 downto 0);\r
+signal lvl1_error_pattern : std_logic_vector(31 downto 0);\r
+signal lvl1_trg_release : std_logic;\r
+signal lvl1_trg_missing : std_logic;\r
+signal lvl1_int_trg_number : std_logic_vector(15 downto 0);\r
+signal lvl1_int_trg_update : std_logic;\r
+signal timing_trg_found : std_logic;\r
+signal timing_trg_too_long : std_logic;\r
+\r
+-- IPU application interface\r
+signal ipu_number : std_logic_vector(15 downto 0);\r
+signal ipu_information : std_logic_vector(7 downto 0);\r
+signal ipu_start_readout : std_logic;\r
+signal ipu_data : std_logic_vector(31 downto 0);\r
+signal ipu_dataready : std_logic;\r
+signal ipu_readout_finished : std_logic;\r
+signal ipu_read : std_logic;\r
+signal ipu_length : std_logic_vector(15 downto 0);\r
+signal ipu_error_pattern : std_logic_vector(31 downto 0);\r
+signal ipu_last_num : std_logic_vector(31 downto 0);\r
+\r
+signal local_lvl1_counter : std_logic_vector(15 downto 0);\r
+signal local_lvl2_counter : std_logic_vector(15 downto 0);\r
+\r
+-- ADC signals\r
+type reg_12bit_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
+signal adc_raw_data : reg_12bit_t; -- ADC specific clock domain\r
+signal adc_data : reg_12bit_t; -- common APV clock domain\r
+\r
+signal adc1_testdata : std_logic_vector(11 downto 0);\r
+signal adc0_testdata : std_logic_vector(11 downto 0);\r
+signal adc1_select : std_logic_vector(2 downto 0);\r
+signal adc0_select : std_logic_vector(2 downto 0);\r
+\r
+-- input synchronizing\r
+signal bp_sector_q : std_logic_vector(3 downto 0);\r
+signal bp_sector_qq : std_logic_vector(3 downto 0);\r
+signal bp_module_q : std_logic_vector(3 downto 0);\r
+signal bp_module_qq : std_logic_vector(3 downto 0);\r
+\r
+signal lsm_state_bits : std_logic_vector(3 downto 0);\r
+signal reset_by_trb : std_logic;\r
+signal global_sync_reset : std_logic;\r
+\r
+signal adc0_iodelay : std_logic_vector(3 downto 0);\r
+signal adc1_iodelay : std_logic_vector(3 downto 0);\r
+\r
+signal cts_clk40m : std_logic;\r
+signal cts_clk40m_locked : std_logic;\r
+signal test_reg40m : std_logic;\r
+\r
+signal serious_error_flag : std_logic;\r
+signal error_flag : std_logic;\r
+signal warning_flag : std_logic;\r
+signal note_flag : std_logic;\r
+\r
+signal broken_buf : std_logic_vector(15 downto 0);\r
+signal next_not_configured : std_logic;\r
+signal not_configured : std_logic;\r
+\r
+signal apv_error : std_logic_vector(15 downto 0);\r
+signal next_fe_error : std_logic;\r
+signal fe_error : std_logic;\r
+\r
+signal tick_10s : std_logic;\r
+\r
+begin\r
+\r
+\r
+----------------------------------------\r
+-- Async reset assignment --\r
+----------------------------------------\r
+async_reset <= uc_reset; -- uC reset pin\r
+\r
+\r
+----------------------------------------\r
+-- Reset handler / spike surpression --\r
+----------------------------------------\r
+THE_RESET_HANDLER: reset_handler \r
+generic map (\r
+ RESET_DELAY => x"00ff"\r
+)\r
+port map (\r
+ CLEAR_IN => async_reset,\r
+ CLEAR_N_IN => '1', -- unused\r
+ CLK_IN => clk100m,\r
+ SYSCLK_IN => sysclk,\r
+ PLL_LOCKED_IN => clk100m_locked,\r
+ RESET_IN => common_ctrl_reg(3),\r
+ TRB_RESET_IN => reset_by_trb,\r
+ CLEAR_OUT => open,\r
+ RESET_OUT => global_sync_reset,\r
+ DEBUG_OUT => open\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- Reboot handler (pulse triggered) --\r
+----------------------------------------\r
+THE_REBOOT_HANDLER: reboot_handler\r
+port map( \r
+ RESET_IN => reset_by_trb,\r
+ CLK_IN => sysclk,\r
+ START_IN => common_ctrl_reg(15),\r
+ REBOOT_OUT => uc_reboot,\r
+ DEBUG_OUT => open\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- 100MHz PLL -> 40MHz / 100MHz --\r
+----------------------------------------\r
+-- 100MHz PLL, generating 40MHz and phase shifted 40MHz\r
+THE_40M_PLL: PLL_40M\r
+port map( \r
+ CLK => clk100m,\r
+ RESET => clk40m_reset,\r
+ DPAMODE => '1', -- dynamic control \r
+ DPHASE0 => ctrl_pll(0),\r
+ DPHASE1 => ctrl_pll(1),\r
+ DPHASE2 => ctrl_pll(2),\r
+ DPHASE3 => ctrl_pll(3),\r
+ CLKOP => clk_apv, -- fixed phase, used for logic \r
+ CLKOS => clk_adc, -- phase adjustable, for ODDRXC only\r
+ LOCK => clk40m_locked\r
+);\r
+clk40m_reset <= ctrl_pll(7);\r
+\r
+-- 100MHz DLL, used for clock injection delay removal\r
+THE_100M_DLL: dll_100m\r
+port map( \r
+ CLK => clk100m,\r
+ RESETN => '1',\r
+ ALUHOLD => '0',\r
+ CLKOP => sysclk,\r
+ CLKOS => open,\r
+ LOCK => clk100m_locked\r
+);\r
+\r
+-- 40MHz PLL, takes central clock distributed by CTS\r
+THE_SYNC_PLL: sync_pll_40m\r
+port map(\r
+ CLK => ext_in(3),\r
+ RESET => ctrl_pll(4),\r
+ CLKOP => cts_clk40m,\r
+ LOCK => cts_clk40m_locked\r
+);\r
+\r
+THE_TEST_REG: process( cts_clk40m, cts_clk40m_locked )\r
+begin\r
+ if( cts_clk40m_locked = '0' ) then\r
+ test_reg40m <= '0';\r
+ else\r
+ if( rising_edge(cts_clk40m) ) then\r
+ test_reg40m <= not test_reg40m;\r
+ end if;\r
+ end if;\r
+end process THE_TEST_REG;\r
+\r
+----------------------------------------\r
+-- TRB endpoint --\r
+----------------------------------------\r
+THE_RICH_TRB: rich_trb\r
+port map( \r
+ CLK100M_IN => clk100m, -- SerDes exclusive clock\r
+ SYSCLK_IN => sysclk, -- fabric clock\r
+ RESET_IN => global_sync_reset,\r
+ SD_RXD_P_IN => hdinp2,\r
+ SD_RXD_N_IN => hdinn2,\r
+ SD_TXD_P_OUT => hdoutp2, \r
+ SD_TXD_N_OUT => hdoutn2,\r
+ SD_PRESENT_IN => sd_present,\r
+ SD_TXDIS_OUT => sd_txdis,\r
+ SD_LOS_IN => sd_los,\r
+ ONEWIRE_INOUT => adcm_onewire,\r
+ -- common regIO status / control registers\r
+ COMMON_STAT_REG_IN => common_stat_reg,\r
+ COMMON_CTRL_REG_OUT => common_ctrl_reg,\r
+ -- status register input to regIO / control register output from regIO\r
+ CONTROL_OUT => simple_control,\r
+ STATUS_IN => simple_status,\r
+ -- LVL1 signals\r
+ LVL1_TRG_TYPE_OUT => lvl1_trg_type,\r
+ LVL1_TRG_RECEIVED_OUT => lvl1_trg_received,\r
+ LVL1_TRG_NUMBER_OUT => lvl1_trg_number,\r
+ LVL1_TRG_CODE_OUT => lvl1_trg_code,\r
+ LVL1_TRG_INFORMATION_OUT => lvl1_trg_information,\r
+ LVL1_ERROR_PATTERN_IN => lvl1_error_pattern,\r
+ LVL1_TRG_RELEASE_IN => lvl1_trg_release,\r
+ LVL1_INT_TRG_NUMBER_OUT => lvl1_int_trg_number, -- internal trigger counter\r
+ LVL1_INT_TRG_UPDATE_OUT => lvl1_int_trg_update, -- update on internal trigger counter\r
+ TIMING_TRG_FOUND_IN => timing_trg_found,\r
+ -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-)\r
+ IPU_NUMBER_OUT => ipu_number,\r
+ IPU_INFORMATION_OUT => ipu_information,\r
+ IPU_START_READOUT_OUT => ipu_start_readout,\r
+ IPU_DATA_IN => ipu_data,\r
+ IPU_DATAREADY_IN => ipu_dataready,\r
+ IPU_READOUT_FINISHED_IN => ipu_readout_finished,\r
+ IPU_READ_OUT => ipu_read,\r
+ IPU_LENGTH_IN => ipu_length,\r
+ IPU_ERROR_PATTERN_IN => ipu_error_pattern,\r
+ -- regIO bus\r
+ REGIO_ADDR_OUT => regio_addr,\r
+ REGIO_READ_ENABLE_OUT => regio_read_enable,\r
+ REGIO_WRITE_ENABLE_OUT => regio_write_enable,\r
+ REGIO_DATA_OUT => regio_data_wr,\r
+ REGIO_DATA_IN => regio_data_rd,\r
+ REGIO_DATAREADY_IN => regio_dataready,\r
+ REGIO_NO_MORE_DATA_IN => regio_no_more_data,\r
+ REGIO_WRITE_ACK_IN => regio_write_ack,\r
+ REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr,\r
+ REGIO_TIMEOUT_OUT => regio_timeout,\r
+ -- status LEDs\r
+ LED_LINK_STAT => fpga_led_link,\r
+ LED_LINK_TXD => fpga_led_txd,\r
+ LED_LINK_RXD => fpga_led_rxd,\r
+ LINK_BSM_OUT => lsm_state_bits, -- LinkStateMachine bits\r
+ RESET_OUT => reset_by_trb,\r
+ TICK_10S_OUT => tick_10s,\r
+ -- Debug\r
+ DEBUG => open --trbrich_debug \r
+);\r
+\r
+-- common control register bit definitions\r
+-- [31:24] ---\r
+-- [23:16] fake timing trigger\r
+-- [15] reboot FPGA\r
+-- [14:11] --- \r
+-- [10] reset sequence counter\r
+-- [9:4] ---\r
+-- [3] master reset, reset the whole endpoint\r
+-- [2] empty IPU chain, reset IPU logic\r
+-- [1] reset trigger logic\r
+-- [0] reset frontends\r
+\r
+-- LVL1 error pattern, to be sent back to CTS with each trigger\r
+lvl1_error_pattern(31 downto 24) <= (others => '0'); -- reserved\r
+lvl1_error_pattern(23) <= fe_error; -- frontend error\r
+lvl1_error_pattern(22) <= not_configured; -- not configured\r
+lvl1_error_pattern(21) <= '0'; -- buffers almost full\r
+lvl1_error_pattern(20) <= '0'; -- buffers half full\r
+lvl1_error_pattern(19 downto 18) <= (others => '0'); -- reserved\r
+lvl1_error_pattern(17) <= lvl1_trg_missing; -- missing timing trigger (done by Jan)\r
+lvl1_error_pattern(16) <= '0'; -- LVL1 tag mismatch with local counters (done by Jan)\r
+lvl1_error_pattern(15 downto 0) <= (others => '0'); -- reserved for common status bits\r
+\r
+\r
+----------------------------------------------\r
+-- mixed status and control bit definitions --\r
+----------------------------------------------\r
+\r
+-- Common status register \r
+-- CSR1\r
+common_stat_reg(63 downto 48) <= ipu_last_num(15 downto 0); -- LVL2 counter\r
+common_stat_reg(47 downto 32) <= local_lvl1_counter; -- LVL1 counter\r
+-- CSR0\r
+common_stat_reg(31 downto 20) <= x"000"; -- reserved for temp sensor\r
+common_stat_reg(19 downto 14) <= (others => '0'); -- was (19 downto 13)\r
+common_stat_reg(13) <= timing_trg_too_long; -- NOT STANDARDIZED!!!!\r
+common_stat_reg(12) <= '0'; -- IPU: single broken event\r
+common_stat_reg(11) <= '0'; -- IPU: severe problem\r
+common_stat_reg(10) <= '0'; -- IPU: partially not found\r
+common_stat_reg(9) <= ipu_error_pattern(20); -- IPU: not found\r
+common_stat_reg(8) <= lvl1_trg_missing; -- LVL1: timing trigger missing\r
+common_stat_reg(7) <= fe_error; -- LVL1: frontend error\r
+common_stat_reg(6) <= not_configured; -- LVL1: not configured\r
+common_stat_reg(5) <= '0'; -- LVL2 counter mismatch (not implemented)\r
+common_stat_reg(4) <= '0'; -- LVL1 trigger counter mismatch (reserved)\r
+common_stat_reg(3) <= note_flag; -- note flag\r
+common_stat_reg(2) <= warning_flag; -- warning flag\r
+common_stat_reg(1) <= error_flag; -- error flag\r
+common_stat_reg(0) <= serious_error_flag; -- serious error flag\r
+\r
+serious_error_flag <= lvl1_trg_missing or fe_error or not_configured;\r
+error_flag <= ipu_error_pattern(20);\r
+warning_flag <= '0';\r
+note_flag <= '0';\r
+\r
+-- Control register bit padding\r
+ctrl_bithigh <= ctrl_lvl(31 downto 24) & x"0";\r
+ctrl_bitlow <= ctrl_lvl(23 downto 16) & x"0";\r
+ctrl_flathigh <= ctrl_lvl(15 downto 8) & x"0";\r
+ctrl_flatlow <= ctrl_lvl(7 downto 0) & x"0";\r
+\r
+-- LVDS driver enable\r
+ena_lvds(0) <= adc_on(4) or lvds_on(4); \r
+ena_lvds(1) <= adc_on(3) or lvds_on(3);\r
+ena_lvds(2) <= adc_on(5) or lvds_on(5);\r
+ena_lvds(3) <= adc_on(2) or lvds_on(2);\r
+ena_lvds(4) <= adc_on(6) or lvds_on(6);\r
+ena_lvds(5) <= adc_on(1) or lvds_on(1);\r
+ena_lvds(6) <= adc_on(7) or lvds_on(7);\r
+ena_lvds(7) <= adc_on(0) or lvds_on(0);\r
+ \r
+enb_lvds(0) <= adc_on(13) or lvds_on(13);\r
+enb_lvds(1) <= adc_on(10) or lvds_on(10);\r
+enb_lvds(2) <= adc_on(12) or lvds_on(12);\r
+enb_lvds(3) <= adc_on(11) or lvds_on(11);\r
+enb_lvds(4) <= adc_on(15) or lvds_on(15);\r
+enb_lvds(5) <= adc_on(8) or lvds_on(8);\r
+enb_lvds(6) <= adc_on(14) or lvds_on(14);\r
+enb_lvds(7) <= adc_on(9) or lvds_on(9);\r
+\r
+bp_led <= cts_clk40m_locked; -- LED is against GND!\r
+\r
+\r
+----------------------------------------\r
+-- internal slave bus -> slow control --\r
+----------------------------------------\r
+THE_SLAVE_BUS: slave_bus\r
+port map( \r
+ CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ -- RegIO signals\r
+ REGIO_ADDR_IN => regio_addr,\r
+ REGIO_DATA_IN => regio_data_wr,\r
+ REGIO_DATA_OUT => regio_data_rd,\r
+ REGIO_READ_ENABLE_IN => regio_read_enable,\r
+ REGIO_WRITE_ENABLE_IN => regio_write_enable,\r
+ REGIO_TIMEOUT_IN => regio_timeout,\r
+ REGIO_DATAREADY_OUT => regio_dataready,\r
+ REGIO_WRITE_ACK_OUT => regio_write_ack,\r
+ REGIO_NO_MORE_DATA_OUT => regio_no_more_data,\r
+ REGIO_UNKNOWN_ADDR_OUT => regio_unknown_addr,\r
+ -- I2C connections\r
+ SDA_IN => apv_sda_in,\r
+ SDA_OUT => apv_sda_out,\r
+ SCL_IN => apv_scl_in,\r
+ SCL_OUT => apv_scl_out,\r
+ -- 1Wire connections\r
+ ONEWIRE_START_IN => '0', -- not used yet\r
+ ONEWIRE_INOUT(15 downto 8) => apv1_1w(7 downto 0),\r
+ ONEWIRE_INOUT(7 downto 0) => apv0_1w(7 downto 0),\r
+ BP_ONEWIRE_INOUT => bp_onewire,\r
+ -- SPI connections\r
+ SPI_CS_OUT => u_spi_cs,\r
+ SPI_SCK_OUT => u_spi_sck,\r
+ SPI_SDI_IN => u_spi_sdo,\r
+ SPI_SDO_OUT => u_spi_sdi,\r
+ -- ADC 0 SPI connections\r
+ SPI_ADC0_CS_OUT => adc0_cs,\r
+ SPI_ADC0_SCK_OUT => adc0_sck,\r
+ SPI_ADC0_SDO_OUT => adc0_sdi,\r
+ ADC0_PLL_LOCKED_IN => adc0_valid,\r
+ ADC0_PD_OUT => adc0_powerdown,\r
+ ADC0_RST_OUT => adc0_reset,\r
+ ADC0_DEL_OUT => adc0_iodelay,\r
+ ADC0_CLK_IN => clk_apv,\r
+ ADC0_DATA_IN => adc0_testdata,\r
+ ADC0_SEL_OUT => adc0_select,\r
+ APV0_RST_OUT => apv0_reset,\r
+ -- ADC 0 SPI connections\r
+ SPI_ADC1_CS_OUT => adc1_cs,\r
+ SPI_ADC1_SCK_OUT => adc1_sck,\r
+ SPI_ADC1_SDO_OUT => adc1_sdi,\r
+ ADC1_PLL_LOCKED_IN => adc1_valid,\r
+ ADC1_PD_OUT => adc1_powerdown,\r
+ ADC1_RST_OUT => adc1_reset,\r
+ ADC1_DEL_OUT => adc1_iodelay,\r
+ ADC1_CLK_IN => clk_apv,\r
+ ADC1_DATA_IN => adc1_testdata,\r
+ ADC1_SEL_OUT => adc1_select,\r
+ APV1_RST_OUT => apv1_reset,\r
+ -- backplane identifier\r
+ BACKPLANE_IN => bp_module_qq(2 downto 0),\r
+ -- pedestal interface\r
+ PED_ADDR_IN => buf_addr,\r
+ PED_DATA_0_OUT => ped_data(0),\r
+ PED_DATA_1_OUT => ped_data(1),\r
+ PED_DATA_2_OUT => ped_data(2),\r
+ PED_DATA_3_OUT => ped_data(3),\r
+ PED_DATA_4_OUT => ped_data(4),\r
+ PED_DATA_5_OUT => ped_data(5),\r
+ PED_DATA_6_OUT => ped_data(6),\r
+ PED_DATA_7_OUT => ped_data(7),\r
+ PED_DATA_8_OUT => ped_data(8),\r
+ PED_DATA_9_OUT => ped_data(9),\r
+ PED_DATA_10_OUT => ped_data(10),\r
+ PED_DATA_11_OUT => ped_data(11),\r
+ PED_DATA_12_OUT => ped_data(12),\r
+ PED_DATA_13_OUT => ped_data(13),\r
+ PED_DATA_14_OUT => ped_data(14),\r
+ PED_DATA_15_OUT => ped_data(15),\r
+ -- threshold interface\r
+ THR_ADDR_IN => thr_addr,\r
+ THR_DATA_0_OUT => thr_data(0),\r
+ THR_DATA_1_OUT => thr_data(1),\r
+ THR_DATA_2_OUT => thr_data(2),\r
+ THR_DATA_3_OUT => thr_data(3),\r
+ THR_DATA_4_OUT => thr_data(4),\r
+ THR_DATA_5_OUT => thr_data(5),\r
+ THR_DATA_6_OUT => thr_data(6),\r
+ THR_DATA_7_OUT => thr_data(7),\r
+ THR_DATA_8_OUT => thr_data(8),\r
+ THR_DATA_9_OUT => thr_data(9),\r
+ THR_DATA_10_OUT => thr_data(10),\r
+ THR_DATA_11_OUT => thr_data(11),\r
+ THR_DATA_12_OUT => thr_data(12),\r
+ THR_DATA_13_OUT => thr_data(13),\r
+ THR_DATA_14_OUT => thr_data(14),\r
+ THR_DATA_15_OUT => thr_data(15),\r
+ -- APV control / status\r
+ CTRL_0_OUT => adc_ctrl_reg(0),\r
+ CTRL_1_OUT => adc_ctrl_reg(1),\r
+ CTRL_2_OUT => adc_ctrl_reg(2),\r
+ CTRL_3_OUT => adc_ctrl_reg(3),\r
+ CTRL_4_OUT => adc_ctrl_reg(4),\r
+ CTRL_5_OUT => adc_ctrl_reg(5),\r
+ CTRL_6_OUT => adc_ctrl_reg(6),\r
+ CTRL_7_OUT => adc_ctrl_reg(7),\r
+ CTRL_8_OUT => adc_ctrl_reg(8),\r
+ CTRL_9_OUT => adc_ctrl_reg(9),\r
+ CTRL_10_OUT => adc_ctrl_reg(10),\r
+ CTRL_11_OUT => adc_ctrl_reg(11),\r
+ CTRL_12_OUT => adc_ctrl_reg(12),\r
+ CTRL_13_OUT => adc_ctrl_reg(13),\r
+ CTRL_14_OUT => adc_ctrl_reg(14),\r
+ CTRL_15_OUT => adc_ctrl_reg(15),\r
+ STAT_0_IN => adc_stat_reg(0),\r
+ STAT_1_IN => adc_stat_reg(1),\r
+ STAT_2_IN => adc_stat_reg(2),\r
+ STAT_3_IN => adc_stat_reg(3),\r
+ STAT_4_IN => adc_stat_reg(4),\r
+ STAT_5_IN => adc_stat_reg(5),\r
+ STAT_6_IN => adc_stat_reg(6),\r
+ STAT_7_IN => adc_stat_reg(7),\r
+ STAT_8_IN => adc_stat_reg(8),\r
+ STAT_9_IN => adc_stat_reg(9),\r
+ STAT_10_IN => adc_stat_reg(10),\r
+ STAT_11_IN => adc_stat_reg(11),\r
+ STAT_12_IN => adc_stat_reg(12),\r
+ STAT_13_IN => adc_stat_reg(13),\r
+ STAT_14_IN => adc_stat_reg(14),\r
+ STAT_15_IN => adc_stat_reg(15),\r
+ -- FIFO status\r
+ FIFO_STATUS_0_IN => fifo_status(0),\r
+ FIFO_STATUS_1_IN => fifo_status(1),\r
+ FIFO_STATUS_2_IN => fifo_status(2),\r
+ FIFO_STATUS_3_IN => fifo_status(3),\r
+ FIFO_STATUS_4_IN => fifo_status(4),\r
+ FIFO_STATUS_5_IN => fifo_status(5),\r
+ FIFO_STATUS_6_IN => fifo_status(6),\r
+ FIFO_STATUS_7_IN => fifo_status(7),\r
+ FIFO_STATUS_8_IN => fifo_status(8),\r
+ FIFO_STATUS_9_IN => fifo_status(9),\r
+ FIFO_STATUS_10_IN => fifo_status(10),\r
+ FIFO_STATUS_11_IN => fifo_status(11),\r
+ FIFO_STATUS_12_IN => fifo_status(12),\r
+ FIFO_STATUS_13_IN => fifo_status(13),\r
+ FIFO_STATUS_14_IN => fifo_status(14),\r
+ FIFO_STATUS_15_IN => fifo_status(15),\r
+ IPU_STATUS_IN => ipu_handler_status,\r
+ RELEASE_STATUS_IN => lvl1_release_status,\r
+ -- some control signals\r
+ CTRL_LVL_OUT => ctrl_lvl,\r
+ CTRL_TRG_OUT => ctrl_trg,\r
+ CTRL_PLL_OUT => ctrl_pll,\r
+ STATUS_PLL_IN => status_pll,\r
+ -- temporary stuff \r
+ TEST_REG_IN => test_reg, -- short cut \r
+ TEST_REG_OUT => test_reg,\r
+ -- Debug \r
+ DEBUG_OUT => open, --slave_debug,\r
+ STAT => open\r
+); \r
+\r
+-- PLL status register \r
+status_pll(15) <= clk100m_locked;\r
+status_pll(14) <= clk40m_locked;\r
+status_pll(13) <= adc1_valid;\r
+status_pll(12) <= adc0_valid;\r
+status_pll(11) <= adc1_swap;\r
+status_pll(10) <= adc0_swap;\r
+status_pll(9) <= test_reg40m; --'0';\r
+status_pll(8) <= cts_clk40m_locked;\r
+status_pll(7) <= '0'; -- make it human readable\r
+status_pll(6 downto 4) <= bp_sector_qq(2 downto 0); -- given by backplane DIP switch, for readback only\r
+status_pll(3) <= '0'; -- make it human readable\r
+status_pll(2 downto 0) <= bp_module_qq(2 downto 0); -- given by backplane DIP switch, for readback only\r
+\r
+-- Common status register, do not use.\r
+simple_status(127 downto 104) <= (others => '0');\r
+simple_status(103 downto 96) <= trgctrl_debug(39 downto 32);\r
+simple_status(95 downto 64) <= trgctrl_debug(31 downto 0);\r
+simple_status(63 downto 32) <= (others => '0');\r
+simple_status(31 downto 16) <= local_lvl2_counter;\r
+simple_status(15 downto 0) <= local_lvl1_counter;\r
+\r
+-- all APVs are reset together, including the common FE reset\r
+THE_APV_PULSE_STRETCH: pulse_stretch\r
+port map(\r
+ CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ START_IN => common_ctrl_reg(0),\r
+ PULSE_OUT => frontend_reset,\r
+ DEBUG_OUT => open\r
+);\r
+\r
+apv_reset <= apv0_reset or apv1_reset or frontend_reset;\r
+\r
+-- APV status registers\r
+-- "ADC on" bits\r
+-- "LVDS ON" bits \r
+GEN_ADC_LVDS_ON: for i in 0 to 15 generate\r
+ adc_on(i) <= adc_ctrl_reg(i)(0);\r
+ lvds_on(i) <= adc_ctrl_reg(i)(1);\r
+ adc_stat_reg(i) <= buf_data(i)(37 downto 30) & raw_buf_debug(i*4+3 downto i*4+0) & std_logic_vector(to_unsigned(i,4));\r
+ broken_buf(i) <= buf_data(i)(36); -- BUF_BROKEN bit\r
+ apv_error(i) <= buf_data(i)(26); -- APV error frame bit\r
+end generate GEN_ADC_LVDS_ON;\r
+\r
+next_not_configured <= '1' when (broken_buf /= x"0000") else '0';\r
+next_fe_error <= '1' when (apv_error /= x"0000") else '0';\r
+\r
+----------------------------------------\r
+-- IPU endpoint for data transport --\r
+----------------------------------------\r
+THE_IPU_STAGE: ipu_fifo_stage \r
+port map( \r
+ CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ IPU_RESET_IN => common_ctrl_reg(2),\r
+ -- Slow control signals \r
+ SECTOR_IN => bp_sector_qq(2 downto 0), \r
+ MODULE_IN => bp_module_qq(2 downto 0), \r
+ -- IPU channel connections \r
+ IPU_NUMBER_IN => ipu_number,\r
+ IPU_INFORMATION_IN => ipu_information,\r
+ IPU_START_READOUT_IN => ipu_start_readout,\r
+ IPU_DATA_OUT => ipu_data,\r
+ IPU_DATAREADY_OUT => ipu_dataready,\r
+ IPU_READOUT_FINISHED_OUT => ipu_readout_finished,\r
+ IPU_READ_IN => ipu_read,\r
+ IPU_LENGTH_OUT => ipu_length,\r
+ IPU_ERROR_PATTERN_OUT => ipu_error_pattern,\r
+ IPU_LAST_NUM_OUT => ipu_last_num,\r
+ LVL2_COUNTER_OUT => local_lvl2_counter,\r
+ -- DHDR buffer input \r
+ DHDR_DATA_IN => dhdr_data,\r
+ DHDR_LENGTH_IN => dhdr_length,\r
+ DHDR_STORE_IN => dhdr_store,\r
+ DHDR_BUF_FULL_OUT => dhdr_buf_full,\r
+ -- processed data input\r
+ FIFO_SPACE_REQ_IN => fifo_space_req,\r
+ FIFO_START_IN => fifo_start,\r
+ FIFO_0_DATA_IN => fifo_data(0),\r
+ FIFO_1_DATA_IN => fifo_data(1),\r
+ FIFO_2_DATA_IN => fifo_data(2),\r
+ FIFO_3_DATA_IN => fifo_data(3),\r
+ FIFO_4_DATA_IN => fifo_data(4),\r
+ FIFO_5_DATA_IN => fifo_data(5),\r
+ FIFO_6_DATA_IN => fifo_data(6),\r
+ FIFO_7_DATA_IN => fifo_data(7),\r
+ FIFO_8_DATA_IN => fifo_data(8),\r
+ FIFO_9_DATA_IN => fifo_data(9),\r
+ FIFO_10_DATA_IN => fifo_data(10),\r
+ FIFO_11_DATA_IN => fifo_data(11),\r
+ FIFO_12_DATA_IN => fifo_data(12),\r
+ FIFO_13_DATA_IN => fifo_data(13),\r
+ FIFO_14_DATA_IN => fifo_data(14),\r
+ FIFO_15_DATA_IN => fifo_data(15),\r
+ FIFO_WE_IN => fifo_we,\r
+ FIFO_DONE_IN => fifo_done,\r
+ FIFO_0_STATUS_OUT => fifo_status(0),\r
+ FIFO_1_STATUS_OUT => fifo_status(1),\r
+ FIFO_2_STATUS_OUT => fifo_status(2),\r
+ FIFO_3_STATUS_OUT => fifo_status(3),\r
+ FIFO_4_STATUS_OUT => fifo_status(4),\r
+ FIFO_5_STATUS_OUT => fifo_status(5),\r
+ FIFO_6_STATUS_OUT => fifo_status(6),\r
+ FIFO_7_STATUS_OUT => fifo_status(7),\r
+ FIFO_8_STATUS_OUT => fifo_status(8),\r
+ FIFO_9_STATUS_OUT => fifo_status(9),\r
+ FIFO_10_STATUS_OUT => fifo_status(10),\r
+ FIFO_11_STATUS_OUT => fifo_status(11),\r
+ FIFO_12_STATUS_OUT => fifo_status(12),\r
+ FIFO_13_STATUS_OUT => fifo_status(13),\r
+ FIFO_14_STATUS_OUT => fifo_status(14),\r
+ FIFO_15_STATUS_OUT => fifo_status(15),\r
+ IPU_STATUS_OUT => ipu_handler_status,\r
+ RELEASE_STATUS_OUT => lvl1_release_status,\r
+ -- Debug signals\r
+ DBG_BSM_OUT => open,\r
+ DBG_OUT => open --fifo_debug\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- Data processing unit --\r
+----------------------------------------\r
+THE_PED_CORR_STAGE: ped_corr_ctrl\r
+port map( \r
+ CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ VERBOSE_IN => common_ctrl_reg(94), -- CCR2-30\r
+ EDS_DATA_IN => eds_data,\r
+ EDS_AVAIL_IN => eds_avail,\r
+ EDS_DONE_OUT => eds_done,\r
+ -- DHDR information -- to next stage\r
+ DHDR_DATA_OUT => dhdr_data,\r
+ DHDR_LENGTH_OUT => dhdr_length,\r
+ DHDR_STORE_OUT => dhdr_store,\r
+ DHDR_BUF_FULL_IN => dhdr_buf_full,\r
+ FIFO_SPACE_REQ_OUT => fifo_space_req, \r
+ -- data buffers -- from raw_buf_stage\r
+ BUF_ADDR_OUT => buf_addr,\r
+ BUF_DONE_OUT => buf_done,\r
+ BUF_TICK_IN => buf_tick,\r
+ BUF_START_IN => buf_start,\r
+ -- raw data\r
+ BUF_0_DATA_IN => buf_data(0),\r
+ BUF_1_DATA_IN => buf_data(1),\r
+ BUF_2_DATA_IN => buf_data(2),\r
+ BUF_3_DATA_IN => buf_data(3),\r
+ BUF_4_DATA_IN => buf_data(4),\r
+ BUF_5_DATA_IN => buf_data(5),\r
+ BUF_6_DATA_IN => buf_data(6),\r
+ BUF_7_DATA_IN => buf_data(7),\r
+ BUF_8_DATA_IN => buf_data(8),\r
+ BUF_9_DATA_IN => buf_data(9),\r
+ BUF_10_DATA_IN => buf_data(10),\r
+ BUF_11_DATA_IN => buf_data(11),\r
+ BUF_12_DATA_IN => buf_data(12),\r
+ BUF_13_DATA_IN => buf_data(13),\r
+ BUF_14_DATA_IN => buf_data(14),\r
+ BUF_15_DATA_IN => buf_data(15),\r
+ -- Pedestal data \r
+ PED_ADDR_OUT => open, -- BUGBUGBUG\r
+ PED_0_DATA_IN => ped_data(0),\r
+ PED_1_DATA_IN => ped_data(1),\r
+ PED_2_DATA_IN => ped_data(2),\r
+ PED_3_DATA_IN => ped_data(3),\r
+ PED_4_DATA_IN => ped_data(4),\r
+ PED_5_DATA_IN => ped_data(5),\r
+ PED_6_DATA_IN => ped_data(6),\r
+ PED_7_DATA_IN => ped_data(7),\r
+ PED_8_DATA_IN => ped_data(8),\r
+ PED_9_DATA_IN => ped_data(9),\r
+ PED_10_DATA_IN => ped_data(10),\r
+ PED_11_DATA_IN => ped_data(11),\r
+ PED_12_DATA_IN => ped_data(12),\r
+ PED_13_DATA_IN => ped_data(13),\r
+ PED_14_DATA_IN => ped_data(14),\r
+ PED_15_DATA_IN => ped_data(15),\r
+ -- Threshold data\r
+ THR_ADDR_OUT => thr_addr,\r
+ THR_0_DATA_IN => thr_data(0),\r
+ THR_1_DATA_IN => thr_data(1),\r
+ THR_2_DATA_IN => thr_data(2),\r
+ THR_3_DATA_IN => thr_data(3),\r
+ THR_4_DATA_IN => thr_data(4),\r
+ THR_5_DATA_IN => thr_data(5),\r
+ THR_6_DATA_IN => thr_data(6),\r
+ THR_7_DATA_IN => thr_data(7),\r
+ THR_8_DATA_IN => thr_data(8),\r
+ THR_9_DATA_IN => thr_data(9),\r
+ THR_10_DATA_IN => thr_data(10),\r
+ THR_11_DATA_IN => thr_data(11),\r
+ THR_12_DATA_IN => thr_data(12),\r
+ THR_13_DATA_IN => thr_data(13),\r
+ THR_14_DATA_IN => thr_data(14),\r
+ THR_15_DATA_IN => thr_data(15),\r
+ -- processed data\r
+ FIFO_START_OUT => fifo_start,\r
+ FIFO_0_DATA_OUT => fifo_data(0),\r
+ FIFO_1_DATA_OUT => fifo_data(1),\r
+ FIFO_2_DATA_OUT => fifo_data(2),\r
+ FIFO_3_DATA_OUT => fifo_data(3),\r
+ FIFO_4_DATA_OUT => fifo_data(4),\r
+ FIFO_5_DATA_OUT => fifo_data(5),\r
+ FIFO_6_DATA_OUT => fifo_data(6),\r
+ FIFO_7_DATA_OUT => fifo_data(7),\r
+ FIFO_8_DATA_OUT => fifo_data(8),\r
+ FIFO_9_DATA_OUT => fifo_data(9),\r
+ FIFO_10_DATA_OUT => fifo_data(10),\r
+ FIFO_11_DATA_OUT => fifo_data(11),\r
+ FIFO_12_DATA_OUT => fifo_data(12),\r
+ FIFO_13_DATA_OUT => fifo_data(13),\r
+ FIFO_14_DATA_OUT => fifo_data(14),\r
+ FIFO_15_DATA_OUT => fifo_data(15),\r
+ FIFO_WE_OUT => fifo_we,\r
+ FIFO_DONE_OUT => fifo_done,\r
+ -- Debug signals\r
+ DBG_BSM_OUT => open,\r
+ DBG_OUT => open\r
+);\r
+\r
+\r
+------------------------------------------\r
+-- Raw data processing and storage unit --\r
+------------------------------------------\r
+THE_RAW_BUF_STAGE: raw_buf_stage\r
+port map( \r
+ CLK_IN => sysclk,\r
+ CLK_APV_IN => clk_apv,\r
+ RESET_IN => reset_by_trb,\r
+ -- trigger related signals\r
+ APV_RESET_IN => apv_reset, -- (100MHz clock)\r
+ APV_SYNC_IN => apv_sync, -- (40MHz APV clock)\r
+ APV_FRAME_REQD_IN => apv_frame_reqd, -- (100MHz clock)\r
+ -- ADC0 signals\r
+ ADC0_VALID_IN => adc0_valid,\r
+ ADC0_0_DATA_IN => adc_data(0),\r
+ ADC0_1_DATA_IN => adc_data(1),\r
+ ADC0_2_DATA_IN => adc_data(2),\r
+ ADC0_3_DATA_IN => adc_data(3),\r
+ ADC0_4_DATA_IN => adc_data(4),\r
+ ADC0_5_DATA_IN => adc_data(5),\r
+ ADC0_6_DATA_IN => adc_data(6),\r
+ ADC0_7_DATA_IN => adc_data(7),\r
+ -- ADC1 signals\r
+ ADC1_VALID_IN => adc1_valid,\r
+ ADC1_0_DATA_IN => adc_data(8),\r
+ ADC1_1_DATA_IN => adc_data(9),\r
+ ADC1_2_DATA_IN => adc_data(10),\r
+ ADC1_3_DATA_IN => adc_data(11),\r
+ ADC1_4_DATA_IN => adc_data(12),\r
+ ADC1_5_DATA_IN => adc_data(13),\r
+ ADC1_6_DATA_IN => adc_data(14),\r
+ ADC1_7_DATA_IN => adc_data(15),\r
+ -- Slow control registers\r
+ MAX_TRG_NUM_IN => maximum_trg, -- automatically determined\r
+ BIT_LOW_IN => ctrl_bitlow, -- from slow control\r
+ BIT_HIGH_IN => ctrl_bithigh, -- from slow control\r
+ FL_LOW_IN => ctrl_flatlow, -- from slow control\r
+ FL_HIGH_IN => ctrl_flathigh, -- from slow control\r
+ APV_ON_IN => adc_on,\r
+ -- 100MHZ synchronous interface\r
+ -- APV raw buffers\r
+ BUF_FULL_OUT => raw_buf_full, -- NEW NEW NEW\r
+ BUF_ADDR_IN => buf_addr, -- from ped_corr_ctrl\r
+ BUF_DONE_IN => buf_done, -- from ped_corr_ctrl\r
+ BUF_TICK_OUT => buf_tick,\r
+ BUF_START_OUT => buf_start,\r
+ BUF_READY_OUT => buf_ready,\r
+ BUF_0_DATA_OUT => buf_data(0), -- to ped_corr_ctrl \r
+ BUF_1_DATA_OUT => buf_data(1), -- to ped_corr_ctrl\r
+ BUF_2_DATA_OUT => buf_data(2), -- to ped_corr_ctrl\r
+ BUF_3_DATA_OUT => buf_data(3), -- to ped_corr_ctrl\r
+ BUF_4_DATA_OUT => buf_data(4), -- to ped_corr_ctrl\r
+ BUF_5_DATA_OUT => buf_data(5), -- to ped_corr_ctrl\r
+ BUF_6_DATA_OUT => buf_data(6), -- to ped_corr_ctrl\r
+ BUF_7_DATA_OUT => buf_data(7), -- to ped_corr_ctrl\r
+ BUF_8_DATA_OUT => buf_data(8), -- to ped_corr_ctrl\r
+ BUF_9_DATA_OUT => buf_data(9), -- to ped_corr_ctrl\r
+ BUF_10_DATA_OUT => buf_data(10), -- to ped_corr_ctrl\r
+ BUF_11_DATA_OUT => buf_data(11), -- to ped_corr_ctrl\r
+ BUF_12_DATA_OUT => buf_data(12), -- to ped_corr_ctrl\r
+ BUF_13_DATA_OUT => buf_data(13), -- to ped_corr_ctrl\r
+ BUF_14_DATA_OUT => buf_data(14), -- to ped_corr_ctrl\r
+ BUF_15_DATA_OUT => buf_data(15), -- to ped_corr_ctrl\r
+ -- Debug signals\r
+ DEBUG_OUT => raw_buf_debug --open\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- ADC1 data handler --\r
+----------------------------------------\r
+THE_ADC1_HANDLER: adc_data_handler \r
+port map( \r
+ RESET_IN => reset_by_trb,\r
+ ADC_LCLK_IN => adc1_lclk,\r
+ ADC_ADCLK_IN => adc1_adclk,\r
+ ADC_CHNL_IN => adc1_out,\r
+ PLL_CTRL_IN => adc1_iodelay,\r
+ ADC_DATA7_OUT => adc_raw_data(15),\r
+ ADC_DATA6_OUT => adc_raw_data(14),\r
+ ADC_DATA5_OUT => adc_raw_data(13),\r
+ ADC_DATA4_OUT => adc_raw_data(12),\r
+ ADC_DATA3_OUT => adc_raw_data(11),\r
+ ADC_DATA2_OUT => adc_raw_data(10),\r
+ ADC_DATA1_OUT => adc_raw_data(9),\r
+ ADC_DATA0_OUT => adc_raw_data(8),\r
+ ADC_CE_OUT => adc1_ce,\r
+ ADC_VALID_OUT => adc1_valid,\r
+ ADC_SWAP_OUT => adc1_swap,\r
+ DEBUG_OUT => open\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- ADC1 clock domain crossover --\r
+----------------------------------------\r
+THE_ADC1_CROSSOVER: adc_crossover\r
+port map( \r
+ CLK_APV_IN => clk_apv,\r
+ RESET_IN => global_sync_reset,\r
+ -- ADC clock domain signals\r
+ ADC_CLK_IN => adc1_lclk,\r
+ ADC_CE_IN => adc1_ce,\r
+ ADC_DATA_VALID_IN => adc1_valid,\r
+ ADC_DATA_7_IN => adc_raw_data(15),\r
+ ADC_DATA_6_IN => adc_raw_data(14),\r
+ ADC_DATA_5_IN => adc_raw_data(13),\r
+ ADC_DATA_4_IN => adc_raw_data(12),\r
+ ADC_DATA_3_IN => adc_raw_data(11),\r
+ ADC_DATA_2_IN => adc_raw_data(10),\r
+ ADC_DATA_1_IN => adc_raw_data(9),\r
+ ADC_DATA_0_IN => adc_raw_data(8),\r
+ LEVEL_WR_OUT => open,\r
+ -- APV clock domain signals\r
+ APV_DATA_7_OUT => adc_data(15),\r
+ APV_DATA_6_OUT => adc_data(14),\r
+ APV_DATA_5_OUT => adc_data(13),\r
+ APV_DATA_4_OUT => adc_data(12),\r
+ APV_DATA_3_OUT => adc_data(11),\r
+ APV_DATA_2_OUT => adc_data(10),\r
+ APV_DATA_1_OUT => adc_data(9),\r
+ APV_DATA_0_OUT => adc_data(8),\r
+ APV_DATA_VALID_OUT => open,\r
+ LEVEL_RD_OUT => open,\r
+ -- Debug signals\r
+ DEBUG_OUT => open\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- ADC1 test data multiplexer --\r
+----------------------------------------\r
+THE_ADC_1_SELECT: adc_channel_select\r
+port map( \r
+ RESET_IN => reset_by_trb,\r
+ ADC_CLK_IN => clk_apv,\r
+ ADC_SEL_IN => adc1_select,\r
+ ADC_7_IN => adc_data(15),\r
+ ADC_6_IN => adc_data(14),\r
+ ADC_5_IN => adc_data(13),\r
+ ADC_4_IN => adc_data(12),\r
+ ADC_3_IN => adc_data(11),\r
+ ADC_2_IN => adc_data(10),\r
+ ADC_1_IN => adc_data(9),\r
+ ADC_0_IN => adc_data(8),\r
+ ADC_CH_OUT => adc1_testdata,\r
+ DEBUG_OUT => open\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- ADC0 data handler --\r
+----------------------------------------\r
+THE_ADC0_HANDLER: adc_data_handler \r
+port map( \r
+ RESET_IN => reset_by_trb,\r
+ ADC_LCLK_IN => adc0_lclk,\r
+ ADC_ADCLK_IN => adc0_adclk,\r
+ ADC_CHNL_IN => adc0_out,\r
+ PLL_CTRL_IN => adc0_iodelay,\r
+ ADC_DATA7_OUT => adc_raw_data(7),\r
+ ADC_DATA6_OUT => adc_raw_data(6),\r
+ ADC_DATA5_OUT => adc_raw_data(5),\r
+ ADC_DATA4_OUT => adc_raw_data(4),\r
+ ADC_DATA3_OUT => adc_raw_data(3),\r
+ ADC_DATA2_OUT => adc_raw_data(2),\r
+ ADC_DATA1_OUT => adc_raw_data(1),\r
+ ADC_DATA0_OUT => adc_raw_data(0),\r
+ ADC_CE_OUT => adc0_ce,\r
+ ADC_VALID_OUT => adc0_valid,\r
+ ADC_SWAP_OUT => adc0_swap,\r
+ DEBUG_OUT => open\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- ADC0 clock domain crossover --\r
+----------------------------------------\r
+THE_ADC0_CROSSOVER: adc_crossover\r
+port map( \r
+ CLK_APV_IN => clk_apv,\r
+ RESET_IN => global_sync_reset,\r
+ -- ADC clock domain signals\r
+ ADC_CLK_IN => adc0_lclk,\r
+ ADC_CE_IN => adc0_ce,\r
+ ADC_DATA_VALID_IN => adc0_valid,\r
+ ADC_DATA_7_IN => adc_raw_data(7),\r
+ ADC_DATA_6_IN => adc_raw_data(6),\r
+ ADC_DATA_5_IN => adc_raw_data(5),\r
+ ADC_DATA_4_IN => adc_raw_data(4),\r
+ ADC_DATA_3_IN => adc_raw_data(3),\r
+ ADC_DATA_2_IN => adc_raw_data(2),\r
+ ADC_DATA_1_IN => adc_raw_data(1),\r
+ ADC_DATA_0_IN => adc_raw_data(0),\r
+ LEVEL_WR_OUT => open,\r
+ -- APV clock domain signals\r
+ APV_DATA_7_OUT => adc_data(7),\r
+ APV_DATA_6_OUT => adc_data(6),\r
+ APV_DATA_5_OUT => adc_data(5),\r
+ APV_DATA_4_OUT => adc_data(4),\r
+ APV_DATA_3_OUT => adc_data(3),\r
+ APV_DATA_2_OUT => adc_data(2),\r
+ APV_DATA_1_OUT => adc_data(1),\r
+ APV_DATA_0_OUT => adc_data(0),\r
+ APV_DATA_VALID_OUT => open,\r
+ LEVEL_RD_OUT => open,\r
+ -- Debug signals\r
+ DEBUG_OUT => open\r
+);\r
+\r
+ \r
+----------------------------------------\r
+-- ADC0 test data multiplexer --\r
+----------------------------------------\r
+THE_ADC_0_SELECT: adc_channel_select\r
+port map( \r
+ RESET_IN => reset_by_trb,\r
+ ADC_CLK_IN => clk_apv,\r
+ ADC_SEL_IN => adc0_select,\r
+ ADC_7_IN => adc_data(7),\r
+ ADC_6_IN => adc_data(6),\r
+ ADC_5_IN => adc_data(5),\r
+ ADC_4_IN => adc_data(4),\r
+ ADC_3_IN => adc_data(3),\r
+ ADC_2_IN => adc_data(2),\r
+ ADC_1_IN => adc_data(1),\r
+ ADC_0_IN => adc_data(0),\r
+ ADC_CH_OUT => adc0_testdata,\r
+ DEBUG_OUT => open\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- Trigger handler (APV specific) --\r
+----------------------------------------\r
+THE_APV_TRGCTRL: apv_trgctrl\r
+port map( \r
+ CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ CLK_APV_IN => clk_apv,\r
+ -- Triggers\r
+ SYNC_TRG_IN => common_ctrl_reg(31), -- slow control pulse\r
+ TIME_TRG_IN => ext_in, -- external trigger inputs\r
+ TRB_TRG_IN => common_ctrl_reg(19 downto 16), -- slow control triggers\r
+ STILL_BUSY_IN => raw_buf_full, -- if no more frames are free in first stage buffer we must cease triggers.\r
+ TRG_FOUND_OUT => timing_trg_found, -- to TRB LVL1 endpoint\r
+ TRG_TOO_LONG_OUT => timing_trg_too_long, -- only for TRG0 channel\r
+ SECTOR_IN => bp_sector_qq(2 downto 0), \r
+ -- slow control settings\r
+ TRG_MAX_OUT => maximum_trg,\r
+ TRG_3_TODO_IN => ctrl_trg(31 downto 28), -- from slow control\r
+ TRG_3_DELAY_IN => ctrl_trg(27 downto 24), -- from slow control\r
+ TRG_2_TODO_IN => ctrl_trg(23 downto 20), -- from slow control\r
+ TRG_2_DELAY_IN => ctrl_trg(19 downto 16), -- from slow control\r
+ TRG_1_TODO_IN => ctrl_trg(15 downto 12), -- from slow control\r
+ TRG_1_DELAY_IN => ctrl_trg(11 downto 8), -- from slow control\r
+ TRG_0_TODO_IN => ctrl_trg(7 downto 4), -- from slow control\r
+ TRG_0_DELAY_IN => ctrl_trg(3 downto 0), -- from slow control\r
+ TRG_SETUP_IN => ctrl_pll(15 downto 8), -- from slow control\r
+ -- TRB LVL1 signals\r
+ TRB_TTAG_IN => lvl1_trg_number, -- from TRB LVL1 endpoint\r
+ TRB_TRND_IN => lvl1_trg_code, -- from TRB LVL1 endpoint\r
+ TRB_TTYPE_IN => lvl1_trg_type, -- from TRB LVL1 endpoint\r
+ TRB_TINFO_IN => lvl1_trg_information, -- from TRB LVL1 endpoint\r
+ TRB_TRGRCVD_IN => lvl1_trg_received, -- from TRB LVL1 endpoint\r
+ TRB_MISSING_OUT => lvl1_trg_missing, -- missing timing trigger\r
+ TRB_RELEASE_OUT => lvl1_trg_release, -- to TRB LVL1 endpoint\r
+ TRB_COUNTER_OUT => local_lvl1_counter, -- own trigger counter\r
+ TRB_COUNTER_IN => lvl1_int_trg_number, -- official TRB trigger counter\r
+ TRB_LD_COUNTER_IN => lvl1_int_trg_update, -- load TRB counter value\r
+ -- EDS signals\r
+ EDS_DATA_OUT => eds_data, -- to ped_corr_stage\r
+ EDS_AVAIL_OUT => eds_avail, -- to ped_corr_stage\r
+ EDS_DONE_IN => eds_done, -- from ped_corr_stage\r
+ EDS_FULL_OUT => eds_buf_full,\r
+ EDS_LEVEL_OUT => eds_buf_level,\r
+ FRM_REQD_OUT => apv_frame_reqd, -- to raw_buf_stage (100MHz clock)\r
+ -- APV signals \r
+ APV_TRG_OUT => apv_trg, -- to APV frontends (40MHz APV clock)\r
+ APV_SYNC_OUT => apv_sync, -- to raw_buf_stage (40MHz APV clock)\r
+ DEBUG_OUT => trgctrl_debug\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- ADC signals --\r
+----------------------------------------\r
+adc1_rst <= adc1_reset;\r
+adc1_pd <= adc1_powerdown;\r
+\r
+THE_ADC1CLK_OUT: ODDRXC\r
+port map( \r
+ DA => '1',\r
+ DB => '0',\r
+ CLK => clk_adc,\r
+ RST => '0',\r
+ Q => adc1_clk\r
+);\r
+\r
+adc0_rst <= adc0_reset;\r
+adc0_pd <= adc0_powerdown;\r
+\r
+THE_ADC0CLK_OUT: ODDRXC\r
+port map( \r
+ DA => '1',\r
+ DB => '0',\r
+ CLK => clk_adc,\r
+ RST => '0',\r
+ Q => adc0_clk\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- APV signals --\r
+----------------------------------------\r
+-- SDA line output\r
+apv0_sda <= '0' when (apv_sda_out = '0') else 'Z';\r
+apv1_sda <= '0' when (apv_sda_out = '0') else 'Z';\r
+-- SDA line input (wired OR negative logic)\r
+apv_sda_in <= apv0_sda and apv1_sda;\r
+\r
+-- SCL line output\r
+apv0_scl <= '0' when (apv_scl_out = '0') else 'Z';\r
+apv1_scl <= '0' when (apv_scl_out = '0') else 'Z';\r
+-- SCL line input (wired OR negative logic)\r
+apv_scl_in <= apv0_scl and apv1_scl;\r
+\r
+-- Reset signal with correct polarity\r
+apv0_rst <= not apv_reset;\r
+apv1_rst <= not apv_reset;\r
+\r
+-- CLK and TRG signal\r
+-- CLK is shifted to meet timing constraints of APV\r
+THE_APV0ACLK_OUT: ODDRXC\r
+port map( \r
+ DA => '0', \r
+ DB => '1', \r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv0a_clk\r
+);\r
+\r
+THE_APV0BCLK_OUT: ODDRXC\r
+port map( \r
+ DA => '0',\r
+ DB => '1',\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv0b_clk\r
+);\r
+\r
+THE_APV1ACLK_OUT: ODDRXC\r
+port map( \r
+ DA => '0',\r
+ DB => '1',\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv1a_clk\r
+);\r
+\r
+THE_APV1BCLK_OUT: ODDRXC\r
+port map( \r
+ DA => '0',\r
+ DB => '1',\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv1b_clk\r
+);\r
+\r
+THE_APV0ATRG_OUT: ODDRXC\r
+port map( \r
+ DA => apv_trg,\r
+ DB => apv_trg,\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv0a_trg\r
+);\r
+THE_APV0BTRG_OUT: ODDRXC\r
+port map( \r
+ DA => apv_trg,\r
+ DB => apv_trg,\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv0b_trg\r
+);\r
+THE_APV1ATRG_OUT: ODDRXC\r
+port map( \r
+ DA => apv_trg,\r
+ DB => apv_trg,\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv1a_trg\r
+);\r
+THE_APV1BTRG_OUT: ODDRXC\r
+port map( \r
+ DA => apv_trg,\r
+ DB => apv_trg,\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv1b_trg\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- DIP switch input registers --\r
+----------------------------------------\r
+-- switch "OFF" => '1', switch "ON" => '0'; so invert it\r
+THE_SYNC_PROC: process( sysclk )\r
+begin\r
+ if( rising_edge(sysclk) ) then\r
+ bp_module_qq <= bp_module_q;\r
+ bp_module_q <= not bp_module;\r
+ bp_sector_qq <= bp_sector_q;\r
+ bp_sector_q <= not bp_sector;\r
+ not_configured <= next_not_configured; -- status bit\r
+ fe_error <= next_fe_error; -- status bit\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+\r
+----------------------------------------\r
+-- LED drivers --\r
+----------------------------------------\r
+fpga_led_adc(1) <= not adc1_valid; \r
+fpga_led_adc(0) <= not adc0_valid;\r
+fpga_led(6) <= not lsm_state_bits(0); -- LED "0"\r
+fpga_led(5) <= not lsm_state_bits(1); -- LED "1"\r
+fpga_led(4) <= not lsm_state_bits(2); -- LED "2"\r
+fpga_led(3) <= not lsm_state_bits(3); -- LED "3"\r
+fpga_led_pll <= not clk40m_locked;\r
+\r
+\r
+----------------------------------------\r
+-- FPGA debug header driver --\r
+----------------------------------------\r
+\r
+-- NOT USED, USE EPIC EDITOR INSTEAD!\r
+\r
+------------------------------------------------------------------\r
+-- ORIGINAL STUFF\r
+------------------------------------------------------------------\r
+--debug(42 downto 39) <= (others => '0'); \r
+---- IPU signals\r
+--debug(38 downto 35) <= ipu_number(3 downto 0);\r
+--debug(34) <= ipu_start_readout;\r
+--debug(33) <= ipu_dataready;\r
+--debug(32) <= ipu_read;\r
+--debug(31) <= ipu_readout_finished;\r
+---- FIFO signals\r
+--debug(30) <= fifo_start; -- ped_corr_ctrl -> ipu_stage => data procession starts (unused in ipu_stage)\r
+--debug(29) <= fifo_we(0); -- ped_corr_ctrl -> ipu_stage => transfer processed data into data FIFO (0)\r
+--debug(28) <= fifo_done; -- ped_corr_ctrl -> ipu_stage => store length count data in small FIFOs\r
+--debug(27) <= dhdr_store; -- ped_corr_ctrl -> ipu_stage => store DHDR information for IPU\r
+--debug(26) <= dhdr_buf_full; -- ipu_stage ->\r
+---- EventDataSheet / buffer signals\r
+--debug(25) <= buf_done; -- ped_corr_ctrl -> raw_buf_stage => raw data has been processed\r
+--debug(24) <= buf_tick(0); -- raw_buf_stage -> ped_corr_ctrl => synced tickmarks\r
+--debug(23) <= buf_ready(0); -- raw_buf_stage => adc_last\r
+--debug(22) <= buf_start(0); -- raw_buf_stage -> ped_corr_ctrl => adc_start\r
+--debug(21 downto 17) <= buf_data(0)(34 downto 30);\r
+--debug(16) <= raw_buf_full; -- raw_buf_stage -> apv_trgctrl => at least one raw buffer is full\r
+--debug(15) <= eds_done; -- ped_corr_ctrl -> apv_trgctrl => EDS data has been transfered, release buffer entry\r
+--debug(14) <= eds_avail; -- apv_trgctrl -> ped_corr_ctrl => at least one EDS is available\r
+--debug(13) <= eds_buf_full; -- apv_trgctrl => EDS buffer is full\r
+--debug(12 downto 8) <= eds_buf_level; \r
+---- timing trigger signals\r
+--debug(7) <= timing_trg_found; -- apv_trgctrl -> endpoint => timing trigger has arrived\r
+--debug(6) <= lvl1_trg_received; -- endpoint -> apv_trgctrl => LVL1 trigger packet has arrived\r
+--debug(5) <= lvl1_trg_missing; -- apv_trgctrl -> endpoint => two consecutive timing triggers found\r
+--debug(4) <= lvl1_trg_release; -- apv_trgctrl -> endpoint => release LVL1 busy \r
+--debug(3 downto 0) <= lvl1_trg_number(3 downto 0);\r
+\r
+\r
+----------------------------------------\r
+-- "unused" pins --\r
+----------------------------------------\r
+\r
+end adcmv3;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use IEEE.numeric_std.ALL;\r
+--use IEEE.numeric_std.ALL;\r
+--use IEEE.std_logic_UNSIGNED.ALL;\r
+\r
+\r
+package adcmv3_components is\r
+\r
+component dbg_reg is\r
+generic(\r
+ WIDTH : integer := 1\r
+);\r
+port(\r
+ DEBUG_IN : in std_logic_vector(WIDTH-1 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(WIDTH-1 downto 0)\r
+);\r
+end component dbg_reg;\r
+\r
+component reset_handler is\r
+generic(\r
+ RESET_DELAY : std_logic_vector(15 downto 0) := x"1fff"\r
+);\r
+port( \r
+ CLEAR_IN : in std_logic; -- reset input (high active, async)\r
+ CLEAR_N_IN : in std_logic; -- reset input (low active, async)\r
+ CLK_IN : in std_logic; -- raw master clock, NOT from PLL/DLL!\r
+ SYSCLK_IN : in std_logic; -- PLL/DLL remastered clock\r
+ PLL_LOCKED_IN : in std_logic; -- master PLL lock signal (async)\r
+ RESET_IN : in std_logic; -- general reset signal (SYSCLK)\r
+ TRB_RESET_IN : in std_logic; -- TRBnet reset signal (SYSCLK)\r
+ CLEAR_OUT : out std_logic; -- async reset out, USE WITH CARE!\r
+ RESET_OUT : out std_logic; -- synchronous reset out (SYSCLK)\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component reset_handler;\r
+\r
+component sync_pll_40m is\r
+port(\r
+ CLK : in std_logic; \r
+ RESET : in std_logic; \r
+ CLKOP : out std_logic; \r
+ LOCK : out std_logic\r
+);\r
+end component sync_pll_40m;\r
+\r
+component raw_buf_stage is\r
+port(\r
+ CLK_IN : in std_logic; -- 100MHz local clock\r
+ CLK_APV_IN : in std_logic; -- 40MHz APV clock\r
+ RESET_IN : in std_logic; -- general reset (100MHz)\r
+ -- trigger related signals\r
+ APV_RESET_IN : in std_logic; -- APV reset signal (100MHz)\r
+ APV_SYNC_IN : in std_logic; -- APV sync trigger has been sent (40MHz)\r
+ APV_FRAME_REQD_IN : in std_logic; -- one APV frame has been requested (100MHz)\r
+ -- ADC0 signals\r
+ ADC0_VALID_IN : in std_logic; -- 40M reconstructed clock is valid\r
+ ADC0_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 0\r
+ ADC0_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 1\r
+ ADC0_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 2\r
+ ADC0_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 3\r
+ ADC0_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 4\r
+ ADC0_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 5\r
+ ADC0_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 6\r
+ ADC0_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 7\r
+ -- ADC1 signals\r
+ ADC1_VALID_IN : in std_logic; -- 40M reconstructed clock is valid\r
+ ADC1_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 0\r
+ ADC1_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 1\r
+ ADC1_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 2\r
+ ADC1_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 3\r
+ ADC1_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 4\r
+ ADC1_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 5\r
+ ADC1_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 6\r
+ ADC1_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 7\r
+ -- Slow control registers\r
+ MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers / event\r
+ BIT_LOW_IN : in std_logic_vector(11 downto 0); -- "bit low" threshold\r
+ BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- "bit high" threshold\r
+ FL_LOW_IN : in std_logic_vector(11 downto 0); -- "flatline low" threshold\r
+ FL_HIGH_IN : in std_logic_vector(11 downto 0); -- "flatline high" threshold\r
+ APV_ON_IN : in std_logic_vector(15 downto 0); -- APV on/off bits from slow control\r
+ -- 100MHZ synchronous interface\r
+ -- APV raw buffers\r
+ BUF_FULL_OUT : out std_logic;\r
+ BUF_ADDR_IN : in std_logic_vector(6 downto 0);\r
+ BUF_DONE_IN : in std_logic;\r
+ BUF_TICK_OUT : out std_logic_vector(15 downto 0);\r
+ BUF_START_OUT : out std_logic_vector(15 downto 0);\r
+ BUF_READY_OUT : out std_logic_vector(15 downto 0);\r
+ BUF_0_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_1_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_2_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_3_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_4_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_5_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_6_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_7_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_8_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_9_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_10_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_11_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_12_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_13_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_14_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_15_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
+end component raw_buf_stage;\r
+\r
+component adc_data_handler is\r
+port(\r
+ RESET_IN : in std_logic;\r
+ ADC_LCLK_IN : in std_logic; -- LCLK from ADC\r
+ ADC_ADCLK_IN : in std_logic; -- ADCLK from ADC\r
+ ADC_CHNL_IN : in std_logic_vector(7 downto 0);\r
+ PLL_CTRL_IN : in std_logic_vector(3 downto 0);\r
+ ADC_DATA7_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA6_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA5_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA4_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA3_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA2_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA1_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA0_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_CE_OUT : out std_logic;\r
+ ADC_VALID_OUT : out std_logic;\r
+ ADC_SWAP_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component adc_data_handler;\r
+\r
+component adc_crossover is\r
+port(\r
+ CLK_APV_IN : in std_logic; -- APV 40MHz local clock\r
+ RESET_IN : in std_logic; -- general reset (100MHz)\r
+ -- ADC clock domain signals\r
+ ADC_CLK_IN : in std_logic;\r
+ ADC_CE_IN : in std_logic; -- in case we use 240MHz + write pulse...\r
+ ADC_DATA_VALID_IN : in std_logic;\r
+ ADC_DATA_7_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_6_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_5_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_4_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_3_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_2_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_1_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_0_IN : in std_logic_vector(11 downto 0);\r
+ LEVEL_WR_OUT : out std_logic_vector(4 downto 0);\r
+ -- APV clock domain signals\r
+ APV_DATA_7_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_6_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_5_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_4_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_3_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_2_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_1_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_0_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_VALID_OUT : out std_logic;\r
+ LEVEL_RD_OUT : out std_logic_vector(4 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+);\r
+end component adc_crossover;\r
+\r
+component crossover is\r
+port(\r
+ DATA : in std_logic_vector(95 downto 0);\r
+ WRCLOCK : in std_logic;\r
+ RDCLOCK : in std_logic;\r
+ WREN : in std_logic;\r
+ RDEN : in std_logic;\r
+ RESET : in std_logic; -- asynchronous reset!\r
+ RPRESET : in std_logic;\r
+ Q : out std_logic_vector(95 downto 0);\r
+ WCNT : out std_logic_vector(4 downto 0);\r
+ RCNT : out std_logic_vector(4 downto 0);\r
+ EMPTY : out std_logic;\r
+ FULL : out std_logic\r
+);\r
+end component crossover;\r
+\r
+component slv_adc_la is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(9 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from\r
+ ADC_CLK_IN : in std_logic; -- ADC reconstructed clock\r
+ ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component slv_adc_la;\r
+\r
+-- NOT USED YET\r
+component logic_analyzer is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- control signals\r
+ ARM_IN : in std_logic; -- arm the machine\r
+ TRG_IN : in std_logic; -- trigger the data acquisition\r
+ MAX_SAMPLE_IN : in std_logic_vector(9 downto 0);\r
+ -- status signals\r
+ SM_ADDR_OUT : out std_logic_vector(9 downto 0); -- sample RAM addresses\r
+ SM_CE_OUT : out std_logic;\r
+ SM_WE_OUT : out std_logic; -- write enable for sample RAM\r
+ CLEAR_OUT : out std_logic; -- sample memory is being cleared\r
+ RUN_OUT : out std_logic; -- ready for trigger\r
+ SAMPLE_OUT : out std_logic; -- data acquisition running\r
+ READY_OUT : out std_logic; -- data acquisition is finished\r
+ LAST_OUT : out std_logic; -- last data word of sampling\r
+ -- Status lines\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component logic_analyzer;\r
+\r
+component onewire_spare_one is\r
+port(\r
+ ADDRESS : in std_logic_vector(2 downto 0);\r
+ Q : out std_logic_vector(3 downto 0)\r
+);\r
+end component onewire_spare_one;\r
+\r
+component adc_onewire_map_mem is\r
+port(\r
+ ADDRESS : in std_logic_vector(6 downto 0);\r
+ Q : out std_logic_vector(3 downto 0)\r
+);\r
+end component adc_onewire_map_mem;\r
+\r
+component adc_channel_select is\r
+port(\r
+ RESET_IN : in std_logic;\r
+ ADC_CLK_IN : in std_logic;\r
+ ADC_SEL_IN : in std_logic_vector(2 downto 0);\r
+ ADC_7_IN : in std_logic_vector(11 downto 0);\r
+ ADC_6_IN : in std_logic_vector(11 downto 0);\r
+ ADC_5_IN : in std_logic_vector(11 downto 0);\r
+ ADC_4_IN : in std_logic_vector(11 downto 0);\r
+ ADC_3_IN : in std_logic_vector(11 downto 0);\r
+ ADC_2_IN : in std_logic_vector(11 downto 0);\r
+ ADC_1_IN : in std_logic_vector(11 downto 0);\r
+ ADC_0_IN : in std_logic_vector(11 downto 0);\r
+ ADC_CH_OUT : out std_logic_vector(11 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component adc_channel_select;\r
+\r
+component slv_adc_snoop is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(9 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from\r
+ ADC_CLK_IN : in std_logic; -- ADC reconstructed clock\r
+ ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component slv_adc_snoop;\r
+\r
+component adc_snoop_mem is\r
+port(\r
+ WRADDRESS : in std_logic_vector(9 downto 0);\r
+ RDADDRESS : in std_logic_vector(9 downto 0);\r
+ DATA : in std_logic_vector(15 downto 0);\r
+ WE : in std_logic;\r
+ RDCLOCK : in std_logic;\r
+ RDCLOCKEN : in std_logic;\r
+ RESET : in std_logic;\r
+ WRCLOCK : in std_logic;\r
+ WRCLOCKEN : in std_logic;\r
+ Q : out std_logic_vector(15 downto 0)\r
+);\r
+end component adc_snoop_mem;\r
+\r
+component max_data is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ TODO_3_IN : in std_logic_vector(3 downto 0);\r
+ TODO_2_IN : in std_logic_vector(3 downto 0);\r
+ TODO_1_IN : in std_logic_vector(3 downto 0);\r
+ TODO_0_IN : in std_logic_vector(3 downto 0);\r
+ TODO_MAX_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component max_data;\r
+\r
+component slv_register_bank is\r
+generic(\r
+ RESET_VALUE : std_logic_vector(15 downto 0) := x"0001"\r
+);\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(3 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ CTRL_0_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_1_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_2_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_3_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_4_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_5_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_6_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_7_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_8_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_9_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_10_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_11_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_12_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_13_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_14_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_15_OUT : out std_logic_vector(15 downto 0);\r
+ STAT_0_IN : in std_logic_vector(15 downto 0);\r
+ STAT_1_IN : in std_logic_vector(15 downto 0);\r
+ STAT_2_IN : in std_logic_vector(15 downto 0);\r
+ STAT_3_IN : in std_logic_vector(15 downto 0);\r
+ STAT_4_IN : in std_logic_vector(15 downto 0);\r
+ STAT_5_IN : in std_logic_vector(15 downto 0);\r
+ STAT_6_IN : in std_logic_vector(15 downto 0);\r
+ STAT_7_IN : in std_logic_vector(15 downto 0);\r
+ STAT_8_IN : in std_logic_vector(15 downto 0);\r
+ STAT_9_IN : in std_logic_vector(15 downto 0);\r
+ STAT_10_IN : in std_logic_vector(15 downto 0);\r
+ STAT_11_IN : in std_logic_vector(15 downto 0);\r
+ STAT_12_IN : in std_logic_vector(15 downto 0);\r
+ STAT_13_IN : in std_logic_vector(15 downto 0);\r
+ STAT_14_IN : in std_logic_vector(15 downto 0);\r
+ STAT_15_IN : in std_logic_vector(15 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component slv_register_bank;\r
+\r
+component slv_status is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ STATUS_IN : in std_logic_vector(31 downto 0)\r
+);\r
+end component slv_status;\r
+\r
+component slv_status_bank is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(3 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ STAT_0_IN : in std_logic_vector(31 downto 0);\r
+ STAT_1_IN : in std_logic_vector(31 downto 0);\r
+ STAT_2_IN : in std_logic_vector(31 downto 0);\r
+ STAT_3_IN : in std_logic_vector(31 downto 0);\r
+ STAT_4_IN : in std_logic_vector(31 downto 0);\r
+ STAT_5_IN : in std_logic_vector(31 downto 0);\r
+ STAT_6_IN : in std_logic_vector(31 downto 0);\r
+ STAT_7_IN : in std_logic_vector(31 downto 0);\r
+ STAT_8_IN : in std_logic_vector(31 downto 0);\r
+ STAT_9_IN : in std_logic_vector(31 downto 0);\r
+ STAT_10_IN : in std_logic_vector(31 downto 0);\r
+ STAT_11_IN : in std_logic_vector(31 downto 0);\r
+ STAT_12_IN : in std_logic_vector(31 downto 0);\r
+ STAT_13_IN : in std_logic_vector(31 downto 0);\r
+ STAT_14_IN : in std_logic_vector(31 downto 0);\r
+ STAT_15_IN : in std_logic_vector(31 downto 0)\r
+);\r
+end component slv_status_bank;\r
+\r
+component pulse_stretch is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ START_IN : in std_logic;\r
+ PULSE_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component pulse_stretch;\r
+\r
+component apv_adc_map_mem is\r
+port(\r
+ ADDRESS : in std_logic_vector(6 downto 0);\r
+ Q : out std_logic_vector(3 downto 0)\r
+);\r
+end component apv_adc_map_mem;\r
+\r
+component adc_apv_map_mem is\r
+port(\r
+ ADDRESS : in std_logic_vector(6 downto 0);\r
+ Q : out std_logic_vector(3 downto 0)\r
+);\r
+end component adc_apv_map_mem;\r
+\r
+component ped_thr_true is\r
+port(\r
+ DATAINA : in std_logic_vector(17 downto 0);\r
+ DATAINB : in std_logic_vector(17 downto 0);\r
+ ADDRESSA : in std_logic_vector(6 downto 0);\r
+ ADDRESSB : in std_logic_vector(6 downto 0);\r
+ CLOCKA : in std_logic;\r
+ CLOCKB : in std_logic;\r
+ CLOCKENA : in std_logic;\r
+ CLOCKENB : in std_logic;\r
+ WRA : in std_logic;\r
+ WRB : in std_logic;\r
+ RESETA : in std_logic;\r
+ RESETB : in std_logic;\r
+ QA : out std_logic_vector(17 downto 0);\r
+ QB : out std_logic_vector(17 downto 0)\r
+);\r
+end component ped_thr_true;\r
+\r
+component slv_ped_thr_mem is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(10 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- backplane identifier\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ -- I/O to the backend\r
+ MEM_CLK_IN : in std_logic;\r
+ MEM_ADDR_IN : in std_logic_vector(6 downto 0);\r
+ MEM_0_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_1_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_2_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_3_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_4_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_5_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_6_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_7_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_8_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_9_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_10_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_11_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_12_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_13_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_14_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_15_D_OUT : out std_logic_vector(17 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component slv_ped_thr_mem;\r
+\r
+component pll_40m is\r
+port( \r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ DPAMODE : in std_logic;\r
+ DPHASE0 : in std_logic;\r
+ DPHASE1 : in std_logic;\r
+ DPHASE2 : in std_logic;\r
+ DPHASE3 : in std_logic;\r
+ CLKOP : out std_logic;\r
+ CLKOS : out std_logic;\r
+ LOCK : out std_logic\r
+);\r
+end component pll_40m;\r
+\r
+component dll_100m is\r
+port( \r
+ CLK : in std_logic;\r
+ RESETN : in std_logic;\r
+ ALUHOLD : in std_logic;\r
+ CLKOP : out std_logic;\r
+ CLKOS : out std_logic;\r
+ LOCK : out std_logic\r
+);\r
+end component dll_100m;\r
+\r
+component state_sync is\r
+port( \r
+ STATE_A_IN : in std_logic;\r
+ CLK_B_IN : in std_logic;\r
+ RESET_B_IN : in std_logic;\r
+ STATE_B_OUT : out std_logic\r
+ );\r
+end component state_sync;\r
+\r
+component pulse_sync is\r
+port( \r
+ CLK_A_IN : in std_logic;\r
+ RESET_A_IN : in std_logic;\r
+ PULSE_A_IN : in std_logic;\r
+ CLK_B_IN : in std_logic;\r
+ RESET_B_IN : in std_logic;\r
+ PULSE_B_OUT : out std_logic\r
+);\r
+end component pulse_sync;\r
+\r
+component rich_trb is\r
+port( \r
+ CLK100M_IN : in std_logic;\r
+ SYSCLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ SD_RXD_P_IN : in std_logic;\r
+ SD_RXD_N_IN : in std_logic;\r
+ SD_TXD_P_OUT : out std_logic;\r
+ SD_TXD_N_OUT : out std_logic;\r
+ SD_PRESENT_IN : in std_logic;\r
+ SD_TXDIS_OUT : out std_logic;\r
+ SD_LOS_IN : in std_logic;\r
+ ONEWIRE_INOUT : inout std_logic;\r
+ -- common regIO status / control registers\r
+-- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI\r
+ COMMON_STAT_REG_IN : in std_logic_vector(2*32-1 downto 0); -- common status register, bit definitions like in WIKI\r
+-- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI\r
+ COMMON_CTRL_REG_OUT : out std_logic_vector(3*32-1 downto 0); -- common control register, bit definitions like in WIKI\r
+ -- status register input to regIO / control register output from regIO\r
+ CONTROL_OUT : out std_logic_vector(63 downto 0);\r
+ STATUS_IN : in std_logic_vector(127 downto 0);\r
+ -- LVL1 signals\r
+ LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);\r
+ LVL1_TRG_RECEIVED_OUT : out std_logic;\r
+ LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);\r
+ LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);\r
+ LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);\r
+ LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);\r
+ LVL1_TRG_RELEASE_IN : in std_logic;\r
+ LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);\r
+ LVL1_INT_TRG_UPDATE_OUT : out std_logic;\r
+ TIMING_TRG_FOUND_IN : in std_logic;\r
+ -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-)\r
+ IPU_NUMBER_OUT : out std_logic_vector(15 downto 0); -- trigger tag\r
+ IPU_INFORMATION_OUT : out std_logic_vector(7 downto 0); -- trigger information\r
+ IPU_START_READOUT_OUT : out std_logic; -- gimme data!\r
+ IPU_DATA_IN : in std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
+ IPU_DATAREADY_IN : in std_logic; -- data is valid\r
+ IPU_READOUT_FINISHED_IN : in std_logic; -- no more data, end transfer, send TRM\r
+ IPU_READ_OUT : out std_logic; -- read strobe, low every second cycle\r
+ IPU_LENGTH_IN : in std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
+ IPU_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern\r
+ -- regIO bus\r
+-- REGIO_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);\r
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
+ REGIO_READ_ENABLE_OUT : out std_logic;\r
+ REGIO_WRITE_ENABLE_OUT : out std_logic;\r
+-- REGIO_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
+-- REGIO_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0);\r
+ REGIO_DATAREADY_IN : in std_logic;\r
+ REGIO_NO_MORE_DATA_IN : in std_logic;\r
+ REGIO_WRITE_ACK_IN : in std_logic;\r
+ REGIO_UNKNOWN_ADDR_IN : in std_logic;\r
+ REGIO_TIMEOUT_OUT : out std_logic;\r
+ -- status LEDs\r
+ LED_LINK_STAT : out std_logic;\r
+ LED_LINK_TXD : out std_logic;\r
+ LED_LINK_RXD : out std_logic;\r
+ LINK_BSM_OUT : out std_logic_vector(3 downto 0);\r
+ RESET_OUT : out std_logic;\r
+ TICK_10S_OUT : out std_logic;\r
+ -- Debug\r
+ DEBUG : out std_logic_vector(63 downto 0)\r
+);\r
+end component rich_trb;\r
+\r
+component slave_bus is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- RegIO signals\r
+ REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus\r
+ REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint\r
+ REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint\r
+ REGIO_READ_ENABLE_IN : in std_logic; -- read pulse\r
+ REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse\r
+ REGIO_TIMEOUT_IN : in std_logic; -- access timed out\r
+ REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested\r
+ REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted\r
+ REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now\r
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+ -- 1Wire connections\r
+ ONEWIRE_START_IN : in std_logic; -- start 1Wire scan (pulse)\r
+ ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); -- 1Wire ID on APV FEs\r
+ BP_ONEWIRE_INOUT : inout std_logic; -- 1Wire ID on backplane\r
+ -- SPI connections\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SCK_OUT : out std_logic;\r
+ SPI_SDI_IN : in std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ -- ADC 0 SPI connections\r
+ SPI_ADC0_CS_OUT : out std_logic;\r
+ SPI_ADC0_SCK_OUT : out std_logic;\r
+ SPI_ADC0_SDO_OUT : out std_logic;\r
+ ADC0_PLL_LOCKED_IN : in std_logic;\r
+ ADC0_PD_OUT : out std_logic;\r
+ ADC0_RST_OUT : out std_logic;\r
+ ADC0_DEL_OUT : out std_logic_vector(3 downto 0);\r
+ ADC0_CLK_IN : in std_logic;\r
+ ADC0_DATA_IN : in std_logic_vector(11 downto 0);\r
+ ADC0_SEL_OUT : out std_logic_vector(2 downto 0);\r
+ APV0_RST_OUT : out std_logic;\r
+ -- ADC 0 SPI connections\r
+ SPI_ADC1_CS_OUT : out std_logic;\r
+ SPI_ADC1_SCK_OUT : out std_logic;\r
+ SPI_ADC1_SDO_OUT : out std_logic;\r
+ ADC1_PLL_LOCKED_IN : in std_logic;\r
+ ADC1_PD_OUT : out std_logic;\r
+ ADC1_RST_OUT : out std_logic;\r
+ ADC1_DEL_OUT : out std_logic_vector(3 downto 0);\r
+ ADC1_CLK_IN : in std_logic;\r
+ ADC1_DATA_IN : in std_logic_vector(11 downto 0);\r
+ ADC1_SEL_OUT : out std_logic_vector(2 downto 0);\r
+ APV1_RST_OUT : out std_logic;\r
+ -- User specific inputs / outputs\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ -- pedestal interface\r
+ PED_ADDR_IN : in std_logic_vector(6 downto 0); -- pedestal addressing from data handlers\r
+ PED_DATA_0_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_1_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_2_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_3_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_4_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_5_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_6_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_7_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_8_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_9_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_10_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_11_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_12_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_13_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_14_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_15_OUT : out std_logic_vector(17 downto 0);\r
+ -- threshold interface\r
+ THR_ADDR_IN : in std_logic_vector(6 downto 0); -- threshold addressing from data handlers\r
+ THR_DATA_0_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_1_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_2_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_3_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_4_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_5_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_6_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_7_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_8_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_9_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_10_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_11_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_12_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_13_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_14_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_15_OUT : out std_logic_vector(17 downto 0);\r
+ -- APV control / status\r
+ CTRL_0_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_1_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_2_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_3_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_4_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_5_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_6_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_7_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_8_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_9_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_10_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_11_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_12_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_13_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_14_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_15_OUT : out std_logic_vector(15 downto 0);\r
+ STAT_0_IN : in std_logic_vector(15 downto 0);\r
+ STAT_1_IN : in std_logic_vector(15 downto 0);\r
+ STAT_2_IN : in std_logic_vector(15 downto 0);\r
+ STAT_3_IN : in std_logic_vector(15 downto 0);\r
+ STAT_4_IN : in std_logic_vector(15 downto 0);\r
+ STAT_5_IN : in std_logic_vector(15 downto 0);\r
+ STAT_6_IN : in std_logic_vector(15 downto 0);\r
+ STAT_7_IN : in std_logic_vector(15 downto 0);\r
+ STAT_8_IN : in std_logic_vector(15 downto 0);\r
+ STAT_9_IN : in std_logic_vector(15 downto 0);\r
+ STAT_10_IN : in std_logic_vector(15 downto 0);\r
+ STAT_11_IN : in std_logic_vector(15 downto 0);\r
+ STAT_12_IN : in std_logic_vector(15 downto 0);\r
+ STAT_13_IN : in std_logic_vector(15 downto 0);\r
+ STAT_14_IN : in std_logic_vector(15 downto 0);\r
+ STAT_15_IN : in std_logic_vector(15 downto 0);\r
+ -- FIFO status\r
+ FIFO_STATUS_0_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_1_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_2_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_3_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_4_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_5_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_6_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_7_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_8_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_9_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_10_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_11_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_12_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_13_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_14_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_15_IN : in std_logic_vector(31 downto 0);\r
+ IPU_STATUS_IN : in std_logic_vector(31 downto 0);\r
+ RELEASE_STATUS_IN : in std_logic_vector(31 downto 0);\r
+ -- some control signals\r
+ CTRL_LVL_OUT : out std_logic_vector(31 downto 0);\r
+ CTRL_TRG_OUT : out std_logic_vector(31 downto 0);\r
+ CTRL_PLL_OUT : out std_logic_vector(15 downto 0);\r
+ STATUS_PLL_IN : in std_logic_vector(15 downto 0);\r
+ -- temporary stuff\r
+ TEST_REG_IN : in std_logic_vector(31 downto 0); -- just for testing!\r
+ TEST_REG_OUT : out std_logic_vector(31 downto 0); -- just for testing!\r
+ -- Debug\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0);\r
+ STAT : out std_logic_vector(31 downto 0)\r
+);\r
+end component slave_bus;\r
+\r
+\r
+component apv_trgctrl is\r
+port( \r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic;\r
+ CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
+ -- Triggers\r
+ SYNC_TRG_IN : in std_logic; -- 100MHz signal to SYNC APVs\r
+ TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs\r
+ TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
+ STILL_BUSY_IN : in std_logic; -- set to '1' if any buffer is in danger of overflow\r
+ TRG_FOUND_OUT : out std_logic; -- trigger found\r
+ TRG_TOO_LONG_OUT : out std_logic; -- only for TRG0 channel\r
+ SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number\r
+ -- slow control settings\r
+ TRG_MAX_OUT : out std_logic_vector(3 downto 0); -- maximum number of triggers/event\r
+ TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3\r
+ TRG_3_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2\r
+ TRG_2_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1\r
+ TRG_1_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0\r
+ TRG_0_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers\r
+ -- TRB LVL1 signals\r
+ TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag\r
+ TRB_TRND_IN : in std_logic_vector(7 downto 0); -- TRB LVL1 random tag\r
+ TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- TRB LVL1 trigger type\r
+ TRB_TINFO_IN : in std_logic_vector(23 downto 0); -- TRB LVL1 trigger information\r
+ TRB_TRGRCVD_IN : in std_logic; -- TRB LVL1 trigger received\r
+ TRB_MISSING_OUT : out std_logic; -- TRB LVL1 trigger arrived, but has no corresponding timing trigger\r
+ TRB_RELEASE_OUT : out std_logic; -- release TRB LVL1 channel\r
+ TRB_COUNTER_OUT : out std_logic_vector(15 downto 0);\r
+ TRB_COUNTER_IN : in std_logic_vector(15 downto 0);\r
+ TRB_LD_COUNTER_IN : in std_logic;\r
+ -- EDS signals\r
+ EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EventDataSheet (tm) data word\r
+ EDS_AVAIL_OUT : out std_logic; -- EDS valid, APV trigger done\r
+ EDS_DONE_IN : in std_logic; -- release current EDS buffer\r
+ EDS_FULL_OUT : out std_logic; -- EDS buffer is full\r
+ EDS_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
+ FRM_REQD_OUT : out std_logic; -- frame requested, (level counter decrement)\r
+ -- APV signals\r
+ APV_TRG_OUT : out std_logic;\r
+ APV_SYNC_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
+end component apv_trgctrl;\r
+\r
+component ped_corr_ctrl is\r
+port( \r
+ CLK_IN : in std_logic; -- 100MHz local clock\r
+ RESET_IN : in std_logic; -- synchronous reset\r
+ -- Slow control registers\r
+ VERBOSE_IN : in std_logic; -- add debug words for each APV\r
+ -- EDS buffer -- back to previous source stage\r
+ EDS_DATA_IN : in std_logic_vector(39 downto 0);\r
+ EDS_AVAIL_IN : in std_logic;\r
+ EDS_DONE_OUT : out std_logic;\r
+ -- DHDR information -- to next stage\r
+ DHDR_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_OUT : out std_logic_vector(15 downto 0);\r
+ DHDR_STORE_OUT : out std_logic;\r
+ DHDR_BUF_FULL_IN : in std_logic;\r
+ FIFO_SPACE_REQ_OUT : out std_logic_vector(11 downto 0);\r
+ -- data buffers -- from raw_buf_stage\r
+ BUF_ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ BUF_DONE_OUT : out std_logic;\r
+ BUF_TICK_IN : in std_logic_vector(15 downto 0);\r
+ BUF_START_IN : in std_logic_vector(15 downto 0);\r
+ -- raw data\r
+ BUF_0_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_1_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_2_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_3_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_4_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_5_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_6_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_7_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_8_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_9_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_10_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_11_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_12_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_13_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_14_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_15_DATA_IN : in std_logic_vector(37 downto 0);\r
+ -- Pedestal data\r
+ PED_ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ PED_0_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_1_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_2_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_3_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_4_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_5_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_6_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_7_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_8_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_9_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_10_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_11_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_12_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_13_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_14_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_15_DATA_IN : in std_logic_vector(17 downto 0);\r
+ -- Threshold data\r
+ THR_ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ THR_0_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_1_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_2_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_3_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_4_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_5_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_6_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_7_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_8_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_9_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_10_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_11_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_12_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_13_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_14_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_15_DATA_IN : in std_logic_vector(17 downto 0);\r
+ -- processed data\r
+ FIFO_START_OUT : out std_logic;\r
+ FIFO_0_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_WE_OUT : out std_logic_vector(15 downto 0);\r
+ FIFO_DONE_OUT : out std_logic; -- write level information into small FIFOs\r
+ -- Debug signals\r
+ DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component ped_corr_ctrl;\r
+\r
+component ipu_fifo_stage is\r
+port( \r
+ CLK_IN : in std_logic; -- 100MHz local clock\r
+ RESET_IN : in std_logic; -- synchronous reset\r
+ IPU_RESET_IN : in std_logic; -- requested by TRBnet standard\r
+ -- Slow control signals\r
+ SECTOR_IN : in std_logic_vector(2 downto 0);\r
+ MODULE_IN : in std_logic_vector(2 downto 0);\r
+ -- IPU channel connections\r
+ IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag\r
+ IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information\r
+ IPU_START_READOUT_IN : in std_logic; -- gimme data!\r
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
+ IPU_DATAREADY_OUT : out std_logic; -- data is valid\r
+ IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM\r
+ IPU_READ_IN : in std_logic; -- read strobe, low every second cycle\r
+ IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
+ IPU_LAST_NUM_OUT : out std_logic_vector(31 downto 0); -- last number received / readout\r
+ LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter\r
+ -- DHDR buffer input\r
+ DHDR_DATA_IN : in std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_IN : in std_logic_vector(15 downto 0);\r
+ DHDR_STORE_IN : in std_logic;\r
+ DHDR_BUF_FULL_OUT : out std_logic;\r
+ -- processed data input\r
+ FIFO_SPACE_REQ_IN : in std_logic_vector(11 downto 0);\r
+ FIFO_START_IN : in std_logic;\r
+ FIFO_0_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_WE_IN : in std_logic_vector(15 downto 0);\r
+ FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs\r
+ -- data buffer status\r
+ FIFO_0_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_1_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_2_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_3_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_4_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_5_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_6_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_7_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_8_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_9_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_10_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_11_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_12_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_13_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_14_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_15_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ IPU_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ RELEASE_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ -- Debug signals\r
+ DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
+end component ipu_fifo_stage;\r
+\r
+component ipu_dummy is\r
+port( \r
+ CLK_IN : in std_logic; -- 100MHz local clock\r
+ RESET_IN : in std_logic; -- synchronous reset\r
+ -- Slow control signals\r
+ MIN_COUNT_IN : in std_logic_vector(15 downto 0); -- minimum counter value\r
+ MAX_COUNT_IN : in std_logic_vector(15 downto 0); -- maximum counter value\r
+ CTRL_IN : in std_logic_vector(7 downto 0); -- control bits from slow control\r
+ -- IPU channel connections\r
+ IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag\r
+ IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information\r
+ IPU_START_READOUT_IN : in std_logic; -- gimme data!\r
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
+ IPU_DATAREADY_OUT : out std_logic; -- data is valid\r
+ IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM\r
+ IPU_READ_IN : in std_logic; -- read strobe, low every second cycle\r
+ IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
+ -- DHDR buffer\r
+ LVL1_FIFO_RD_OUT : out std_logic;\r
+ LVL1_FIFO_EMPTY_IN : in std_logic;\r
+ LVL1_FIFO_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ LVL1_FIFO_CODE_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_FIFO_INFORMATION_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_FIFO_TYPE_IN : in std_logic_vector(3 downto 0);\r
+ -- Debug signals\r
+ DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
+end component ipu_dummy;\r
+\r
+component reboot_handler is\r
+port( \r
+ RESET_IN : in std_logic;\r
+ CLK_IN : in std_logic;\r
+ START_IN : in std_logic;\r
+ REBOOT_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component reboot_handler;\r
+\r
+component real_trg_handler is\r
+port( \r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic;\r
+ TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs\r
+ TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
+ APV_TRGDONE_IN : in std_logic; -- APV trigger statemachine finished (one pulse)\r
+ TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3\r
+ TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2\r
+ TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1\r
+ TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0\r
+ TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers\r
+ TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint\r
+ TRG_TOO_LONG_OUT : out std_logic; -- only for TRG0 channel\r
+ SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number\r
+ TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag\r
+ TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number\r
+ TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- LVL1 trigger type\r
+ TRB_TINFO_IN : in std_logic_vector(23 downto 0); -- LVL1 24bit trigger information\r
+ TRB_TRGRCVD_IN : in std_logic; -- LVL1 trigger has been received on TRB\r
+ TRB_MISSING_OUT : out std_logic; -- LVL1 trigger without timing trigger\r
+ LVL1_COUNTER_OUT : out std_logic_vector(15 downto 0); -- LVL1 counter\r
+ LVL1_COUNTER_IN : in std_logic_vector(15 downto 0);\r
+ LVL1_LD_COUNTER_IN : in std_logic;\r
+ BUSY_RELEASE_IN : in std_logic; -- common signal from busy calculator\r
+ APV_TRGSEL_OUT : out std_logic_vector(3 downto 0); -- select one APV trigger state machine\r
+ APV_TRGSTART_OUT : out std_logic; -- start one APV trigger state machine\r
+ EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EDS data\r
+ EDS_WE_OUT : out std_logic; -- EDS write enable (general interface)\r
+ EDS_START_OUT : out std_logic; -- separate increment signal for EDS buffer level\r
+ EDS_READY_OUT : out std_logic; -- APV trigger sequence done, TERMinate the TRB LVL1 trigger\r
+ DBG_FRMCTR_OUT : out std_logic_vector(3 downto 0); -- framecounter itself\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
+end component real_trg_handler;\r
+\r
+component apv_trg_handler is\r
+port( \r
+ CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
+ RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV)\r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; -- synced reset signal (100MHz)\r
+ APV_TRGSTART_IN : in std_logic; -- start signal for one sequence\r
+ APV_TRGSEL_IN : in std_logic; -- select signal for one sequence\r
+ APV_TRG_TODO_IN : in std_logic_vector(3 downto 0); -- number of APV triggers\r
+ APV_TRG_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between APV triggers\r
+ APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished\r
+ APV_TRG_OUT : out std_logic;\r
+ APV_TRGSENT_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component apv_trg_handler;\r
+\r
+component apv_sync_handler is\r
+port( \r
+ CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
+ RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV)\r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; -- synced reset signal (100MHz)\r
+ APV_TRGSTART_IN : in std_logic; -- start signal for one sequence\r
+ APV_TRGSEL_IN : in std_logic; -- select signal for one sequence\r
+ APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished\r
+ APV_TRG_OUT : out std_logic;\r
+ APV_SYNC_OUT : out std_logic; -- signal for statemachines\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component apv_sync_handler;\r
+\r
+component eds_buf is\r
+port( \r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic;\r
+ -- EDS input, all synced to CLK_IN\r
+ EDS_DATA_IN : in std_logic_vector(39 downto 0); -- EDS data input\r
+ EDS_WE_IN : in std_logic; -- EDS write enable\r
+ EDS_DONE_IN : in std_logic; -- release EDS\r
+ EDS_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ EDS_AVAILABLE_OUT : out std_logic;\r
+ -- trigger busy information\r
+ BUF_FULL_OUT : out std_logic;\r
+ BUF_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component eds_buf;\r
+\r
+component adc_pll is\r
+port( \r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLKOP : out std_logic;\r
+ LOCK : out std_logic\r
+);\r
+end component adc_pll;\r
+\r
+component adc_ch_in is\r
+port( \r
+ DEL : in std_logic_vector(3 downto 0);\r
+ ECLK : in std_logic;\r
+ SCLK : in std_logic;\r
+ RST : in std_logic;\r
+ DATA : in std_logic_vector(0 downto 0);\r
+ Q : out std_logic_vector(1 downto 0)\r
+);\r
+End component adc_ch_in;\r
+\r
+component adc_twochannels is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ CLOCK_IN : in std_logic_vector(1 downto 0); -- DDR bit clock\r
+ DATA_0_IN : in std_logic_vector(1 downto 0); -- ADC channel one\r
+ DATA_1_IN : in std_logic_vector(1 downto 0); -- ADC channel two\r
+ DATA_0_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel one\r
+ DATA_1_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel two\r
+ STORE_OUT : out std_logic;\r
+ SWAP_OUT : out std_logic;\r
+ CLOCK_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component adc_twochannels;\r
+\r
+component apv_locker is\r
+port( \r
+ CLK_APV_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ ADC_RAW_IN : in std_logic_vector(11 downto 0); -- ADC: raw data, synchronous to ADC_CLK_IN\r
+ ADC_VALID_IN : in std_logic; -- ADC: ser2par data is valid\r
+ SYNC_IN : in std_logic; -- sync trigger input\r
+ APV_ON_IN : in std_logic; -- this APV channel is switched on\r
+ BIT_LOW_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '0'\r
+ BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '1'\r
+ FL_LOW_IN : in std_logic_vector(11 downto 0); -- lower threshold for ADC flatline\r
+ FL_HIGH_IN : in std_logic_vector(11 downto 0); -- upper threshold for ADC flatline\r
+ STATUS_IGNORE_OUT : out std_logic; -- APV is to be ignored (effectively => switched off)\r
+ STATUS_UNKNOWN_OUT : out std_logic; -- APV is not initialized yet\r
+ STATUS_BADADC_OUT : out std_logic; -- ADC ser2par data is invalid\r
+ STATUS_LOCKED_OUT : out std_logic; -- APV locked successfully\r
+ STATUS_LOST_OUT : out std_logic; -- APV tickmark missing or wrong\r
+ STATUS_NOSYNC_OUT : out std_logic; -- APV did not lock successfully\r
+ STATUS_MISSING_OUT : out std_logic; -- APV is missing, ADC flatline detected\r
+ STATUS_TICKMARK_OUT : out std_logic;\r
+ FRAME_ROW_OUT : out std_logic_vector(7 downto 0); -- decoded row from APV header\r
+ FRAME_ERROR_OUT : out std_logic; -- decoded error bit from APV header\r
+ FRAME_FLAT_OUT : out std_logic; -- APV sends a flat line (analog dead?)\r
+ FRAME_OVF_OUT : out std_logic; -- at least one channel in frame was overflow\r
+ FRAME_UDF_OUT : out std_logic; -- at least one channel in frame was underflow\r
+ FRAME_CTR_OUT : out std_logic_vector(3 downto 0); -- frame counter for incoming data frames\r
+ APV_CHANNEL_OUT : out std_logic_vector(6 downto 0); -- physical channel ID\r
+ APV_OVERFLOW_OUT : out std_logic; -- channel is truncated high\r
+ APV_UNDERFLOW_OUT : out std_logic; -- channel is truncated low\r
+ APV_RAW_OUT : out std_logic_vector(11 downto 0); -- APV raw data\r
+ APV_ANALOG_OUT : out std_logic; -- APV analog data is valid\r
+ APV_START_OUT : out std_logic; -- valid data frame found, reserve one buffer\r
+ APV_LAST_OUT : out std_logic; -- last APV channel of dataframe\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component apv_locker;\r
+\r
+component apv_raw_buffer is\r
+port( \r
+ CLK_APV_IN : in std_logic; -- write clock from APV handling stage\r
+ RESET_IN : in std_logic;\r
+ FRM_REQD_IN : in std_logic; -- one data frame has been requested from APV\r
+ MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers per event\r
+ ADC_ANALOG_IN : in std_logic; -- write enable for ADC data\r
+ ADC_START_IN : in std_logic; -- data frame detected, block the buffer page\r
+ ADC_LAST_IN : in std_logic; -- last channel signal\r
+ ADC_CHANNEL_IN : in std_logic_vector(6 downto 0); -- physical channel ID\r
+ ADC_RAW_IN : in std_logic_vector(17 downto 0); -- raw ADC data, UDF, OVF, ERROR\r
+ ADC_STATUS_IN : in std_logic_vector(7 downto 0); -- status information for APV\r
+ ADC_FRAME_IN : in std_logic_vector(11 downto 0); -- status information for frame\r
+ BUF_CLK_IN : in std_logic; -- read clock\r
+ BUF_RESET_IN : in std_logic; -- 100MHz reset\r
+ BUF_START_OUT : out std_logic; -- one block starts writing\r
+ BUF_READY_OUT : out std_logic; -- one block has been written\r
+ BUF_ADDR_IN : in std_logic_vector(6 downto 0); -- address inside current buffer\r
+ BUF_DONE_IN : in std_logic; -- buffer has been read (discard buffer)\r
+ BUF_DATA_OUT : out std_logic_vector(17 downto 0); -- data from buffer\r
+ BUF_STATUS_OUT : out std_logic_vector(7 downto 0); -- generic APV status output\r
+ BUF_FRAME_OUT : out std_logic_vector(11 downto 0); -- current frame status output\r
+ BUF_GOOD_OUT : out std_logic; -- APV is active and synced -> GOOD situation\r
+ BUF_BROKEN_OUT : out std_logic; -- APV is active, but not synced -> BAD situation\r
+ BUF_IGNORE_OUT : out std_logic; -- APV is switched off -> switched off\r
+ BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); -- number of stored frames inside buffer\r
+ BUF_TICKMARK_OUT : out std_logic; -- tickmark signal for timeouts in the EDS handler\r
+ BUF_FULL_OUT : out std_logic; -- inhibit any next trigger if set!\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component apv_raw_buffer;\r
+\r
+-- moved to trb_net_components.vhd\r
+--\r
+--component slv_register is\r
+--generic(\r
+-- RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" \r
+--);\r
+--port( \r
+-- CLK_IN : in std_logic;\r
+-- RESET_IN : in std_logic;\r
+-- BUSY_IN : in std_logic;\r
+-- -- Slave bus\r
+-- SLV_READ_IN : in std_logic;\r
+-- SLV_WRITE_IN : in std_logic;\r
+-- SLV_BUSY_OUT : out std_logic;\r
+-- SLV_ACK_OUT : out std_logic;\r
+-- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+-- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+-- -- I/O to the backend\r
+-- REG_DATA_IN : in std_logic_vector(31 downto 0);\r
+-- REG_DATA_OUT : out std_logic_vector(31 downto 0);\r
+-- -- Status lines\r
+-- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+--);\r
+--end component slv_register;\r
+\r
+component slv_half_register is\r
+generic( \r
+ RESET_VALUE : std_logic_vector(15 downto 0) := x"0000" \r
+);\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ STATUS_REG_IN : in std_logic_vector(15 downto 0);\r
+ CTRL_REG_OUT : out std_logic_vector(15 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component slv_half_register;\r
+\r
+component i2c_master is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component i2c_master;\r
+\r
+component slv_onewire_memory is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(5 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- backplane identifier\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ -- 1Wire lines\r
+ ONEWIRE_START_IN : in std_logic;\r
+ ONEWIRE_INOUT : inout std_logic_vector(15 downto 0);\r
+ BP_ONEWIRE_INOUT : inout std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(63 downto 0) -- DEBUG\r
+);\r
+end component slv_onewire_memory;\r
+\r
+component spi_real_slim is\r
+port( \r
+ SYSCLK : in std_logic; -- 100MHz sysclock\r
+ RESET : in std_logic; -- synchronous reset\r
+ -- Command interface\r
+ START_IN : in std_logic; -- one start pulse\r
+ BUSY_OUT : out std_logic; -- SPI transactions are ongoing\r
+ CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte\r
+ -- SPI interface\r
+ SPI_SCK_OUT : out std_logic;\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ -- DEBUG\r
+ CLK_EN_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+);\r
+end component spi_real_slim;\r
+\r
+component spi_adc_master is\r
+generic( \r
+ RESET_VALUE_CTRL : std_logic_vector(7 downto 0) := x"60" \r
+);\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- SPI connections\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ SPI_SCK_OUT : out std_logic;\r
+ -- ADC connections\r
+ ADC_LOCKED_IN : in std_logic;\r
+ ADC_PD_OUT : out std_logic;\r
+ ADC_RST_OUT : out std_logic;\r
+ ADC_DEL_OUT : out std_logic_vector(3 downto 0);\r
+ -- APV connections\r
+ APV_RST_OUT : out std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component spi_adc_master;\r
+\r
+component i2c_slim is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- I2C command / setup\r
+ I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions\r
+ ACTION_IN : in std_logic; -- '0' -> write, '1' -> read\r
+ I2C_SPEED_IN : in std_logic_vector( 5 downto 0 ); -- speed adjustment (to be defined)\r
+ I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored)\r
+ I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte)\r
+ I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command\r
+ I2C_DR_OUT : out std_logic_vector( 7 downto 0 ); -- data word from read command\r
+ STATUS_OUT : out std_logic_vector( 7 downto 0 ); -- status and error bits\r
+ I2C_BUSY_OUT : out std_logic;\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+ -- Debug\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component i2c_slim;\r
+\r
+component i2c_gstart is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ START_IN : in std_logic;\r
+ DOSTART_IN : in std_logic;\r
+ I2C_SPEED_IN : in std_logic_vector(7 downto 0);\r
+ SDONE_OUT : out std_logic;\r
+ SOK_OUT : out std_logic;\r
+ SDA_IN : in std_logic;\r
+ SCL_IN : in std_logic;\r
+ R_SCL_OUT : out std_logic;\r
+ S_SCL_OUT : out std_logic;\r
+ R_SDA_OUT : out std_logic;\r
+ S_SDA_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(3 downto 0)\r
+);\r
+end component i2c_gstart;\r
+\r
+component i2c_sendb is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ DOBYTE_IN : in std_logic;\r
+ I2C_SPEED_IN : in std_logic_vector(7 downto 0);\r
+ I2C_BYTE_IN : in std_logic_vector(8 downto 0);\r
+ I2C_BACK_OUT : out std_logic_vector(8 downto 0);\r
+ SDA_IN : in std_logic;\r
+ R_SDA_OUT : out std_logic;\r
+ S_SDA_OUT : out std_logic;\r
+-- SCL_IN : in std_logic;\r
+ R_SCL_OUT : out std_logic;\r
+ S_SCL_OUT : out std_logic;\r
+ BDONE_OUT : out std_logic;\r
+ BOK_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(3 downto 0)\r
+);\r
+end component i2c_sendb;\r
+\r
+component onewire_master is\r
+generic( \r
+ CLK_PERIOD : integer := 10 -- clock perion in nanoseconds\r
+);\r
+port( \r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ READOUT_ENABLE_IN : in std_logic;\r
+ -- connection to 1-wire interface (16 APV FEs)\r
+ ONEWIRE : inout std_logic_vector(15 downto 0);\r
+ BP_ONEWIRE : inout std_logic;\r
+ -- connection to external DPRAM for slow control readout\r
+ BP_DATA_OUT : out std_logic_vector(15 downto 0);\r
+ DATA_OUT : out std_logic_vector(15 downto 0);\r
+ ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ WRITE_OUT : out std_logic;\r
+ BUSY_OUT : out std_logic;\r
+ -- debug\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ STAT : out std_logic_vector(15 downto 0)\r
+);\r
+end component onewire_master;\r
+\r
+component slv_onewire_dpram\r
+port( \r
+ WRADDRESS : in std_logic_vector(6 downto 0);\r
+ RDADDRESS : in std_logic_vector(5 downto 0);\r
+ DATA : in std_logic_vector(15 downto 0);\r
+ WE : in std_logic;\r
+ RDCLOCK : in std_logic;\r
+ RDCLOCKEN : in std_logic;\r
+ RESET : in std_logic;\r
+ WRCLOCK : in std_logic;\r
+ WRCLOCKEN : in std_logic;\r
+ Q : out std_logic_vector(31 downto 0)\r
+);\r
+end component slv_onewire_dpram;\r
+\r
+component fifo_2kx27 is\r
+port( \r
+ DATA : in std_logic_vector(26 downto 0);\r
+ CLOCK : in std_logic;\r
+ WREN : in std_logic;\r
+ RDEN : in std_logic;\r
+ RESET : in std_logic;\r
+ Q : out std_logic_vector(26 downto 0);\r
+ WCNT : out std_logic_vector(11 downto 0);\r
+ EMPTY : out std_logic;\r
+ FULL : out std_logic\r
+);\r
+end component fifo_2kx27;\r
+\r
+component fifo_1kx18 is\r
+port(\r
+ DATA : in std_logic_vector(17 downto 0); \r
+ CLOCK : in std_logic; \r
+ WREN : in std_logic; \r
+ RDEN : in std_logic; \r
+ RESET : in std_logic; \r
+ Q : out std_logic_vector(17 downto 0); \r
+ WCNT : out std_logic_vector(10 downto 0); \r
+ EMPTY : out std_logic; \r
+ ALMOSTFULL : out std_logic;\r
+ FULL : out std_logic\r
+);\r
+end component fifo_1kx18;\r
+\r
+component decoder_8bit is\r
+port( \r
+ ADDRESS : in std_logic_vector(7 downto 0);\r
+ Q : out std_logic_vector(3 downto 0)\r
+);\r
+end component decoder_8bit;\r
+\r
+component buf_toc is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ BUF_TICK_IN : in std_logic; -- tickmark from raw buffer\r
+ BUF_START_IN : in std_logic; -- start of frame from raw buffer\r
+ WAITFRAME_IN : in std_logic; -- statemachine is in "wait for frame" mode\r
+ FRAMES_REQD_IN : in std_logic_vector(3 downto 0); -- number of frames requested from EDS\r
+ BUF_LVL_IN : in std_logic_vector(7 downto 0);\r
+ GOODDATA_OUT : out std_logic;\r
+ BADDATA_OUT : out std_logic;\r
+ NODATA_OUT : out std_logic;\r
+ READY_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component buf_toc;\r
+\r
+component ref_row_sel is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ READY_IN : in std_logic_vector(15 downto 0);\r
+ GOODDATA_IN : in std_logic_vector(15 downto 0);\r
+ FRAME_0_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_1_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_2_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_3_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_4_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_5_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_6_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_7_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_8_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_9_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_10_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_11_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_12_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_13_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_14_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_15_IN : in std_logic_vector(11 downto 0);\r
+ VALID_BUFS_OUT : out std_logic;\r
+ READY_OUT : out std_logic;\r
+ ROW_ERROR_OUT : out std_logic; -- at least one row number is wrong\r
+ APV_ERROR_OUT : out std_logic; -- at least one APV sent ERROR bit\r
+ APV_ERROR_BITS_OUT : out std_logic_vector(15 downto 0);\r
+ REF_ROW_OUT : out std_logic_vector(7 downto 0); -- selected reference row\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component ref_row_sel;\r
+\r
+component frmctr_check is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ GOODDATA_IN : in std_logic_vector(15 downto 0);\r
+ FRAMECOUNTER_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_0_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_1_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_2_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_3_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_4_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_5_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_6_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_7_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_8_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_9_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_10_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_11_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_12_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_13_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_14_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_15_IN : in std_logic_vector(3 downto 0);\r
+ FRC_ERROR_OUT : out std_logic; -- at least one framecounter is wrong\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component frmctr_check;\r
+\r
+component apv_pc_nc_alu is\r
+port( \r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic;\r
+ START_IN : in std_logic;\r
+ MAX_FRAMES_IN : in std_logic_vector(3 downto 0); -- number of frames requested\r
+ CURR_FRAME_IN : in std_logic_vector(3 downto 0); -- current frame number\r
+ LOC_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
+ EDS_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
+ EDS_DATA_IN : in std_logic_vector(39 downto 0); -- DEBUG !!!\r
+ BUF_GOOD_IN : in std_logic;\r
+ BUF_BAD_IN : in std_logic;\r
+ BUF_IGNORE_IN : in std_logic;\r
+ ERROR_IN : in std_logic_vector(3 downto 0); -- buffer status, errors from checkers\r
+ DO_HEADER_IN : in std_logic;\r
+ DO_ERROR_IN : in std_logic;\r
+ SUPPRESS_IN : in std_logic;\r
+ VERBOSE_IN : in std_logic;\r
+ EVT_TYPE_IN : in std_logic_vector(2 downto 0);\r
+ RAW_ADDR_IN : in std_logic_vector(6 downto 0);\r
+ RAW_DATA_IN : in std_logic_vector(37 downto 0);\r
+ PED_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_DATA_IN : in std_logic_vector(17 downto 0);\r
+ FRAME_IN : in std_logic;\r
+ FIFO_DATA_OUT : out std_logic_vector(26 downto 0); -- [21] -> [31], [20:0] -> [20:0]\r
+ WE_OUT : out std_logic;\r
+ COUNT_OUT : out std_logic_vector(9 downto 0);\r
+ ANYDATA_OUT : out std_logic; -- this FIFO needs attention during readout\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component apv_pc_nc_alu;\r
+\r
+component input_bram is\r
+port( \r
+ WRADDRESS : in std_logic_vector(10 downto 0);\r
+ RDADDRESS : in std_logic_vector(10 downto 0);\r
+ DATA : in std_logic_vector(17 downto 0);\r
+ WE : in std_logic;\r
+ RDCLOCK : in std_logic;\r
+ RDCLOCKEN : in std_logic;\r
+ RESET : in std_logic;\r
+ WRCLOCK : in std_logic;\r
+ WRCLOCKEN : in std_logic;\r
+ Q : out std_logic_vector(17 downto 0)\r
+);\r
+end component input_bram;\r
+\r
+component frame_status_mem is\r
+port( \r
+ WRADDRESS : in std_logic_vector(3 downto 0);\r
+ DATA : in std_logic_vector(11 downto 0);\r
+ WRCLOCK : in std_logic;\r
+ WE : in std_logic;\r
+ WRCLOCKEN : in std_logic;\r
+ RDADDRESS : in std_logic_vector(3 downto 0);\r
+ RDCLOCK : in std_logic;\r
+ RDCLOCKEN : in std_logic;\r
+ RESET : in std_logic;\r
+ Q : out std_logic_vector(11 downto 0)\r
+);\r
+end component frame_status_mem;\r
+\r
+component apv_lock_sm is\r
+port( \r
+ CLK_APV_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ SYNC_IN : in std_logic; -- start APV synchronisation\r
+ ADC_VALID_IN : in std_logic; -- ADC delivers valid data\r
+ TIMED_IN : in std_logic; -- synchronisation timeout\r
+ MATCH_IN : in std_logic; -- artifical tickmark from synchronized counter\r
+ LOCKED_IN : in std_logic; -- enough good tickmarks\r
+ TICK_IN : in std_logic; -- tickmark from digital parser\r
+ HEADER_IN : in std_logic; -- header from digital parser\r
+ FLATLINE_IN : in std_logic; -- flatline from digital parser\r
+ RST_PC_OUT : out std_logic; -- reset period counter\r
+ RST_TC_OUT : out std_logic; -- reset timeout counter\r
+ INC_TC_OUT : out std_logic;\r
+ RST_LC_OUT : out std_logic; -- reset lock counter\r
+ INC_LC_OUT : out std_logic;\r
+ UNKNOWN_OUT : out std_logic;\r
+ BADADC_OUT : out std_logic; -- ADC data invalid\r
+ LOCKED_OUT : out std_logic;\r
+ LOST_OUT : out std_logic;\r
+ NOSYNC_OUT : out std_logic;\r
+ NOAPV_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component apv_lock_sm;\r
+\r
+component apv_digital is\r
+port( \r
+ CLK_APV_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ ADC_RAW_IN : in std_logic_vector(11 downto 0);\r
+ BIT_LOW_IN : in std_logic_vector(11 downto 0);\r
+ BIT_HIGH_IN : in std_logic_vector(11 downto 0);\r
+ FL_LOW_IN : in std_logic_vector(11 downto 0);\r
+ FL_HIGH_IN : in std_logic_vector(11 downto 0);\r
+ BIT_DATA_OUT : out std_logic_vector(11 downto 0);\r
+ BIT_VALID_OUT : out std_logic_vector(11 downto 0);\r
+ BIT_HIGH_OUT : out std_logic;\r
+ BIT_LOW_OUT : out std_logic;\r
+ TICKMARK_OUT : out std_logic;\r
+ HEADER_OUT : out std_logic;\r
+ FLAT_LINE_OUT : out std_logic\r
+);\r
+end component apv_digital;\r
+\r
+component eds_buffer_dpram is\r
+port( \r
+ WRADDRESS : in std_logic_vector(3 downto 0);\r
+ DATA : in std_logic_vector(39 downto 0);\r
+ WRCLOCK : in std_logic;\r
+ WE : in std_logic;\r
+ WRCLOCKEN : in std_logic;\r
+ RDADDRESS : in std_logic_vector(3 downto 0);\r
+ RDCLOCK : in std_logic;\r
+ RDCLOCKEN : in std_logic;\r
+ RESET : in std_logic;\r
+ Q : out std_logic_vector(39 downto 0)\r
+);\r
+end component eds_buffer_dpram;\r
+\r
+end package;\r
+\r
+-- Down in the Dumps...\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+-- Missing: FIFO buffer handling, full / empty checks\r
+\r
+entity ipu_fifo_stage is\r
+port(\r
+ CLK_IN : in std_logic; -- 100MHz local clock\r
+ RESET_IN : in std_logic; -- synchronous reset\r
+ IPU_RESET_IN : in std_logic; -- requested by TRBnet standard\r
+ -- Slow control signals\r
+ SECTOR_IN : in std_logic_vector(2 downto 0);\r
+ MODULE_IN : in std_logic_vector(2 downto 0);\r
+ -- IPU channel connections\r
+ IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag\r
+ IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information\r
+ IPU_START_READOUT_IN : in std_logic; -- gimme data!\r
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
+ IPU_DATAREADY_OUT : out std_logic; -- data is valid\r
+ IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM\r
+ IPU_READ_IN : in std_logic; -- read strobe, low every second cycle\r
+ IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
+ IPU_LAST_NUM_OUT : out std_logic_vector(31 downto 0); -- last number received / readout\r
+ LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter\r
+ -- DHDR buffer input\r
+ DHDR_DATA_IN : in std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_IN : in std_logic_vector(15 downto 0);\r
+ DHDR_STORE_IN : in std_logic;\r
+ DHDR_BUF_FULL_OUT : out std_logic;\r
+ -- processed data input\r
+ FIFO_START_IN : in std_logic;\r
+ FIFO_SPACE_REQ_IN : in std_logic_vector(11 downto 0);\r
+ FIFO_0_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_WE_IN : in std_logic_vector(15 downto 0);\r
+ FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs\r
+ -- data buffer status\r
+ FIFO_0_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_1_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_2_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_3_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_4_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_5_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_6_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_7_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_8_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_9_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_10_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_11_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_12_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_13_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_14_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_15_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ IPU_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ RELEASE_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ -- Debug signals\r
+ DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
+end;\r
+\r
+architecture behavioral of ipu_fifo_stage is\r
+\r
+-- Placer Directives\r
+attribute HGROUP : string;\r
+-- for whole architecture\r
+attribute HGROUP of behavioral : architecture is "IPU_FIFO_STAGE_group";\r
+\r
+-- state machine definitions\r
+type STATES is (SLEEP,RDLF,GETFD,DELH,WHDR,GETD,WAITD,WAITDL,DEL0,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+-- signals\r
+signal debug : std_logic_vector(63 downto 0);\r
+signal bsm_x : std_logic_vector(7 downto 0);\r
+signal next_trgnum_match : std_logic;\r
+signal trgnum_match : std_logic;\r
+\r
+signal dhdr_fifo_in_int : std_logic_vector(47 downto 0);\r
+signal dhdr_fifo_out_int : std_logic_vector(47 downto 0);\r
+signal dhdr_avail : std_logic;\r
+signal next_todo_list : std_logic_vector(15 downto 0);\r
+signal todo_list : std_logic_vector(15 downto 0);\r
+signal next_fifo_sel : std_logic_vector(4 downto 0);\r
+signal fifo_sel : std_logic_vector(4 downto 0);\r
+signal next_sel_fifo : std_logic_vector(15 downto 0);\r
+signal sel_fifo : std_logic_vector(15 downto 0);\r
+\r
+signal comb_rd_dfifo : std_logic_vector(15 downto 0);\r
+signal comb_st_data : std_logic_vector(15 downto 0);\r
+signal comb_ack_todo : std_logic;\r
+\r
+signal ipu_out_data : std_logic_vector(31 downto 0);\r
+\r
+-- state machine signals\r
+signal next_rd_lfifo : std_logic;\r
+signal rd_lfifo : std_logic; -- read current LENGTH_FIFO information (as well as LockAtMe bit)\r
+signal next_dataready : std_logic;\r
+signal dataready : std_logic; -- data word is available\r
+signal next_set_hdr : std_logic;\r
+signal set_hdr : std_logic; -- store DHDR in output register\r
+signal next_set_data : std_logic;\r
+signal set_data : std_logic; -- store DATA from current DATA FIFO in output register\r
+signal next_ld_todo : std_logic;\r
+signal ld_todo : std_logic; -- load initial TODO list\r
+signal next_ack_todo : std_logic;\r
+signal ack_todo : std_logic; -- remove current entry from TODO list\r
+signal next_finished : std_logic;\r
+signal finished : std_logic; -- readout is finished\r
+signal next_preload : std_logic;\r
+signal preload : std_logic; -- read first data word from DATA FIFOs\r
+\r
+-- generate needs arrays...\r
+type fifo_data_t is array (0 to 15) of std_logic_vector(26 downto 0);\r
+signal fifo_in_data : fifo_data_t;\r
+signal fifo_out_data : fifo_data_t;\r
+type fifo_count_t is array (0 to 15) of std_logic_vector(10 downto 0);\r
+signal fifo_in_count : fifo_count_t;\r
+type fifo_todo_t is array (0 to 15) of unsigned(9 downto 0);\r
+signal fifo_todo : fifo_todo_t;\r
+type fifo_ldata_t is array (0 to 15) of std_logic_vector(10 downto 0);\r
+signal fifo_ldata : fifo_ldata_t;\r
+type fifo_cnt_t is array (0 to 15) of unsigned(11 downto 0);\r
+signal fifo_data_free_x : fifo_cnt_t;\r
+signal fifo_data_free : fifo_cnt_t;\r
+type fifo_wcnt_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
+signal fifo_wcnt : fifo_wcnt_t;\r
+type fifo_lunused_t is array (0 to 15) of std_logic_vector(6 downto 0);\r
+signal fifo_lunused : fifo_lunused_t;\r
+type fifo_status_t is array (0 to 15) of std_logic_vector(31 downto 0);\r
+signal fifo_status : fifo_status_t;\r
+\r
+signal ipu_status : std_logic_vector(31 downto 0);\r
+signal release_status : std_logic_vector(31 downto 0);\r
+\r
+signal dfifo_available_x : std_logic_vector(15 downto 0);\r
+signal dfifo_available : std_logic_vector(15 downto 0);\r
+signal dfifo_empty : std_logic_vector(15 downto 0);\r
+signal dfifo_full : std_logic_vector(15 downto 0);\r
+\r
+signal lfifo_empty : std_logic_vector(15 downto 0);\r
+signal lfifo_almostfull : std_logic_vector(15 downto 0);\r
+signal lfifo_full : std_logic_vector(15 downto 0);\r
+\r
+signal next_fifo_done : std_logic_vector(15 downto 0);\r
+signal fifo_done : std_logic_vector(15 downto 0);\r
+signal next_fifo_last : std_logic;\r
+signal fifo_last : std_logic;\r
+\r
+signal my_trg_number : std_logic_vector(31 downto 0); -- just for checking!\r
+\r
+signal old_apv_num : std_logic_vector(3 downto 0);\r
+signal new_apv_num : std_logic_vector(3 downto 0);\r
+\r
+signal cyclectr : unsigned(15 downto 0); -- cycle counter\r
+\r
+signal next_dhdr_buf_full : std_logic;\r
+signal dhdr_buf_full : std_logic;\r
+\r
+signal reset_all : std_logic;\r
+\r
+-- Jan Michel's status bits (faked)\r
+signal status_bits : std_logic_vector(3 downto 0);\r
+\r
+attribute syn_noprune : boolean;\r
+attribute syn_noprune of THE_DBG_REG : label is true;\r
+signal my_debug : std_logic_vector(15 downto 0);\r
+\r
+begin\r
+\r
+--------------------------------------------------------------------\r
+-- Test the NOPRUNE + EPIC feature\r
+--------------------------------------------------------------------\r
+THE_DBG_REG: dbg_reg\r
+generic map(\r
+ WIDTH => 16\r
+)\r
+port map(\r
+ DEBUG_IN => my_debug,\r
+ DEBUG_OUT => open\r
+);\r
+\r
+my_debug(15) <= next_dataready; \r
+my_debug(14 downto 8) <= fifo_wcnt(0)(6 downto 0);\r
+my_debug(7 downto 0) <= bsm_x;\r
+--------------------------------------------------------------------\r
+--------------------------------------------------------------------\r
+\r
+---------------------------------------------------------------------------\r
+-- Combine syncronous resets\r
+---------------------------------------------------------------------------\r
+reset_all <= RESET_IN or IPU_RESET_IN;\r
+\r
+---------------------------------------------------------------------------\r
+-- Statemachine\r
+---------------------------------------------------------------------------\r
+\r
+-- state registers\r
+STATE_MEM: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( reset_all = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ rd_lfifo <= '0';\r
+ dataready <= '0';\r
+ set_hdr <= '0';\r
+ set_data <= '0';\r
+ ld_todo <= '0';\r
+ ack_todo <= '0';\r
+ preload <= '0';\r
+ finished <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ rd_lfifo <= next_rd_lfifo;\r
+ dataready <= next_dataready;\r
+ set_hdr <= next_set_hdr;\r
+ set_data <= next_set_data;\r
+ ld_todo <= next_ld_todo;\r
+ ack_todo <= next_ack_todo;\r
+ preload <= next_preload;\r
+ finished <= next_finished;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- state transitions\r
+STATE_TRANSFORM: process( CURRENT_STATE, dhdr_avail, IPU_START_READOUT_IN, IPU_READ_IN, fifo_last, fifo_sel(4) )\r
+begin\r
+ NEXT_STATE <= SLEEP; -- avoid latches\r
+ next_rd_lfifo <= '0';\r
+ next_dataready <= '0';\r
+ next_set_hdr <= '0';\r
+ next_set_data <= '0';\r
+ next_ld_todo <= '0';\r
+ next_ack_todo <= '0';\r
+ next_preload <= '0';\r
+ next_finished <= '0';\r
+ \r
+ case CURRENT_STATE is\r
+ when SLEEP => if( (dhdr_avail = '1') and (IPU_START_READOUT_IN = '1') ) then\r
+ NEXT_STATE <= RDLF;\r
+ next_rd_lfifo <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RDLF => NEXT_STATE <= GETFD;\r
+ next_set_hdr <= '1';\r
+ next_ld_todo <= '1';\r
+ when GETFD => NEXT_STATE <= DELH;\r
+ next_preload <= '1';\r
+ when DELH => NEXT_STATE <= WHDR;\r
+ next_dataready <= '1';\r
+ when WHDR => if ( (IPU_READ_IN = '1') and (fifo_sel(4) = '0') ) then\r
+ NEXT_STATE <= GETD; -- there are datawords to send\r
+ next_set_data <= '1';\r
+ next_ack_todo <= '1';\r
+ elsif( (IPU_READ_IN = '1') and (fifo_sel(4) = '1') ) then\r
+ NEXT_STATE <= DONE; -- only DHDR, no data words\r
+ next_finished <= '1';\r
+ else\r
+ NEXT_STATE <= WHDR;\r
+ next_dataready <= '1';\r
+ end if;\r
+ when GETD => if( fifo_last = '1' ) then\r
+ NEXT_STATE <= DEL0;\r
+ else\r
+ NEXT_STATE <= WAITD;\r
+ next_dataready <= '1';\r
+ end if;\r
+ when WAITD => if( ipu_read_in = '1' ) then\r
+ NEXT_STATE <= GETD;\r
+ next_set_data <= '1';\r
+ else\r
+ NEXT_STATE <= WAITD;\r
+ next_dataready <= '1';\r
+ end if;\r
+ when DEL0 => NEXT_STATE <= WAITDL;\r
+ next_dataready <= '1';\r
+ when WAITDL => if ( (IPU_READ_IN = '1') and (fifo_sel(4) = '0') ) then\r
+ NEXT_STATE <= GETD;\r
+ next_set_data <= '1';\r
+ next_ack_todo <= '1';\r
+ elsif( (IPU_READ_IN = '1') and (fifo_sel(4) = '1') ) then\r
+ NEXT_STATE <= DONE;\r
+ next_finished <= '1';\r
+ else\r
+ NEXT_STATE <= WAITDL;\r
+ next_dataready <= '1';\r
+ end if;\r
+ when DONE => if( IPU_START_READOUT_IN = '0' ) then\r
+ NEXT_STATE <= SLEEP;\r
+ else\r
+ NEXT_STATE <= DONE;\r
+ end if;\r
+\r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process STATE_TRANSFORM;\r
+\r
+-- Handshaking to IPU data channel\r
+IPU_DATAREADY_OUT <= dataready;\r
+IPU_READOUT_FINISHED_OUT <= finished;\r
+\r
+-- length information can be simply copied\r
+IPU_LENGTH_OUT <= dhdr_fifo_out_int(47 downto 32);\r
+\r
+-- IPU error pattern\r
+IPU_ERROR_PATTERN_OUT(31 downto 24) <= (others => '0');\r
+IPU_ERROR_PATTERN_OUT(23) <= '0'; -- "single broken event"\r
+IPU_ERROR_PATTERN_OUT(23) <= '0'; -- "severe problem"\r
+IPU_ERROR_PATTERN_OUT(21) <= '0'; -- "partially not found"\r
+IPU_ERROR_PATTERN_OUT(20) <= not trgnum_match; -- "not found"\r
+IPU_ERROR_PATTERN_OUT(19 downto 0) <= (others => '0');\r
+\r
+-- state decoding (ONLY FOR DEBUGGING!)\r
+STATE_DECODE: process( CURRENT_STATE )\r
+begin\r
+ case CURRENT_STATE is\r
+ when SLEEP => bsm_x <= x"00";\r
+ status_bits <= x"0";\r
+ when RDLF => bsm_x <= x"11"; --x"01";\r
+ status_bits <= x"1";\r
+ when GETFD => bsm_x <= x"22"; --x"02";\r
+ status_bits <= x"2";\r
+ when DELH => bsm_x <= x"33"; --x"03";\r
+ status_bits <= x"3";\r
+ when WHDR => bsm_x <= x"f4"; --x"04";\r
+ status_bits <= x"3";\r
+ when GETD => bsm_x <= x"e5"; --x"05";\r
+ status_bits <= x"4";\r
+ when WAITD => bsm_x <= x"d6"; --x"06";\r
+ status_bits <= x"4";\r
+ when WAITDL => bsm_x <= x"c7"; --x"07";\r
+ status_bits <= x"4";\r
+ when DEL0 => bsm_x <= x"b8"; --x"08";\r
+ status_bits <= x"4";\r
+ when DONE => bsm_x <= x"a9"; --x"09";\r
+ status_bits <= x"5";\r
+ when others => bsm_x <= x"ff";\r
+ status_bits <= x"f";\r
+ end case;\r
+end process STATE_DECODE;\r
+\r
+---------------------------------------------------------------------------\r
+-- Aliasing the data streams\r
+---------------------------------------------------------------------------\r
+fifo_in_data(0) <= FIFO_0_DATA_IN(26 downto 0); fifo_in_count(0) <= FIFO_0_DATA_IN(37 downto 27);\r
+fifo_in_data(1) <= FIFO_1_DATA_IN(26 downto 0); fifo_in_count(1) <= FIFO_1_DATA_IN(37 downto 27);\r
+fifo_in_data(2) <= FIFO_2_DATA_IN(26 downto 0); fifo_in_count(2) <= FIFO_2_DATA_IN(37 downto 27);\r
+fifo_in_data(3) <= FIFO_3_DATA_IN(26 downto 0); fifo_in_count(3) <= FIFO_3_DATA_IN(37 downto 27);\r
+fifo_in_data(4) <= FIFO_4_DATA_IN(26 downto 0); fifo_in_count(4) <= FIFO_4_DATA_IN(37 downto 27);\r
+fifo_in_data(5) <= FIFO_5_DATA_IN(26 downto 0); fifo_in_count(5) <= FIFO_5_DATA_IN(37 downto 27);\r
+fifo_in_data(6) <= FIFO_6_DATA_IN(26 downto 0); fifo_in_count(6) <= FIFO_6_DATA_IN(37 downto 27);\r
+fifo_in_data(7) <= FIFO_7_DATA_IN(26 downto 0); fifo_in_count(7) <= FIFO_7_DATA_IN(37 downto 27);\r
+fifo_in_data(8) <= FIFO_8_DATA_IN(26 downto 0); fifo_in_count(8) <= FIFO_8_DATA_IN(37 downto 27);\r
+fifo_in_data(9) <= FIFO_9_DATA_IN(26 downto 0); fifo_in_count(9) <= FIFO_9_DATA_IN(37 downto 27);\r
+fifo_in_data(10) <= FIFO_10_DATA_IN(26 downto 0); fifo_in_count(10) <= FIFO_10_DATA_IN(37 downto 27);\r
+fifo_in_data(11) <= FIFO_11_DATA_IN(26 downto 0); fifo_in_count(11) <= FIFO_11_DATA_IN(37 downto 27);\r
+fifo_in_data(12) <= FIFO_12_DATA_IN(26 downto 0); fifo_in_count(12) <= FIFO_12_DATA_IN(37 downto 27);\r
+fifo_in_data(13) <= FIFO_13_DATA_IN(26 downto 0); fifo_in_count(13) <= FIFO_13_DATA_IN(37 downto 27);\r
+fifo_in_data(14) <= FIFO_14_DATA_IN(26 downto 0); fifo_in_count(14) <= FIFO_14_DATA_IN(37 downto 27);\r
+fifo_in_data(15) <= FIFO_15_DATA_IN(26 downto 0); fifo_in_count(15) <= FIFO_15_DATA_IN(37 downto 27);\r
+\r
+---------------------------------------------------------------------------\r
+-- DATA and LENGTH FIFO for the APV data streams\r
+---------------------------------------------------------------------------\r
+\r
+-- We also store the DHDR inside the LFIFOs. They are big enough and have unused bits like hell.\r
+dhdr_fifo_in_int <= DHDR_LENGTH_IN & DHDR_DATA_IN;\r
+\r
+GEN_FIFO: for i in 0 to 15 generate\r
+ THE_DFIFO: fifo_2kx27\r
+ port map(\r
+ DATA => fifo_in_data(i),\r
+ CLOCK => CLK_IN,\r
+ WREN => FIFO_WE_IN(i),\r
+ RDEN => comb_rd_dfifo(i),\r
+ RESET => reset_all,\r
+ Q => fifo_out_data(i),\r
+ WCNT => fifo_wcnt(i),\r
+ EMPTY => dfifo_empty(i),\r
+ FULL => dfifo_full(i)\r
+ );\r
+\r
+ -- Combinatorial read pulse for FIFOs\r
+ comb_rd_dfifo(i) <= (not fifo_done(i) and sel_fifo(i) and IPU_READ_IN and dataready) or (preload and fifo_ldata(i)(10));\r
+\r
+ -- Combinatorial store pulse for data (last data word need to be transfered also!)\r
+ comb_st_data(i) <= (sel_fifo(i) and IPU_READ_IN and dataready);\r
+\r
+ -- getting the number of free entries in the data fifo by subtracting [size] - [used entries]\r
+ fifo_data_free_x(i) <= x"800" - unsigned(fifo_wcnt(i));\r
+\r
+ -- check if next event will still fit into data FIFO\r
+ dfifo_available_x(i) <= '1' when (fifo_data_free(i) > unsigned(FIFO_SPACE_REQ_IN)) else '0';\r
+\r
+ THE_SMALL_SYNCER: process( clk_in)\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ fifo_data_free(i) <= fifo_data_free_x(i);\r
+ dfifo_available(i) <= dfifo_available_x(i);\r
+ end if;\r
+ end process THE_SMALL_SYNCER; \r
+\r
+ -- length fifo - stores the number of words to fetch from dfifo\r
+ THE_LFIFO: fifo_1kx18\r
+ port map(\r
+ DATA(17 downto 15) => dhdr_fifo_in_int(i*3 + 2 downto i*3),\r
+ DATA(14 downto 11) => b"0000", -- free for other stuff!\r
+ DATA(10 downto 0) => fifo_in_count(i),\r
+ CLOCK => CLK_IN,\r
+ WREN => FIFO_DONE_IN,\r
+ RDEN => rd_lfifo,\r
+ RESET => reset_all,\r
+ Q(17 downto 11) => fifo_lunused(i), -- will be portions of DHDR\r
+ Q(10 downto 0) => fifo_ldata(i),\r
+ WCNT => open, -- BUG\r
+ EMPTY => lfifo_empty(i), -- BUG\r
+ ALMOSTFULL => lfifo_almostfull(i), -- BUG\r
+ FULL => lfifo_full(i) -- BUG\r
+ );\r
+ next_todo_list(i) <= fifo_ldata(i)(10);\r
+\r
+ -- reassamble the DHDR information \r
+ dhdr_fifo_out_int(i*3 + 2 downto i*3) <= fifo_lunused(i)(6 downto 4);\r
+ \r
+ -- TODO counter for all FIFOs\r
+ THE_TODO_CTR_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( (reset_all = '1') or (rd_lfifo = '1') ) then\r
+ fifo_todo(i) <= (others => '0');\r
+ elsif( ld_todo = '1' ) then\r
+ fifo_todo(i) <= unsigned(fifo_ldata(i)(9 downto 0));\r
+ elsif( comb_rd_dfifo(i) = '1' ) then\r
+ fifo_todo(i) <= fifo_todo(i) - 1;\r
+ end if;\r
+ end if;\r
+ end process THE_TODO_CTR_PROC;\r
+\r
+ next_fifo_done(i) <= '1' when ( fifo_todo(i) = b"00_0000_0000" ) else '0';\r
+\r
+ -- FIFO status bits, compatible with Jans data handler\r
+ fifo_status(i)(31 downto 28) <= (others => '0'); -- reserved\r
+ fifo_status(i)(27) <= '0'; --fifo_done_in; -- length FIFO write strobe (not implemented)\r
+ fifo_status(i)(26) <= lfifo_full(i); -- length FIFO full. This is an error flag.\r
+ fifo_status(i)(25) <= lfifo_almostfull(i); -- length FIFO almost full\r
+ fifo_status(i)(24) <= lfifo_empty(i); -- length FIFO empty\r
+ fifo_status(i)(23) <= '0'; -- reserved\r
+ fifo_status(i)(22) <= '0'; -- buffer state machine waiting for busy release\r
+ fifo_status(i)(21) <= '0'; -- buffer state machine busy waiting for data\r
+ fifo_status(i)(20) <= '0'; -- buffer state machine idle\r
+ fifo_status(i)(19) <= '0'; --FIFO_WE_IN(i); -- FIFO write strobe (not implemented)\r
+ fifo_status(i)(18) <= dfifo_full(i); -- FIFO full. This is an error flag.\r
+ fifo_status(i)(17) <= not dfifo_available(i); -- FIFO almost full\r
+ fifo_status(i)(16) <= dfifo_empty(i); -- FIFO empty\r
+ fifo_status(i)(15 downto 0) <= b"0000" & fifo_wcnt(i); -- current fill level of FIFO\r
+\r
+end generate GEN_FIFO;\r
+\r
+comb_ack_todo <= fifo_last and set_data;\r
+\r
+next_dhdr_buf_full <= '1' when (lfifo_almostfull(0) = '1') or\r
+ (dfifo_available /= b"1111_1111_1111_1111")\r
+ else '0';\r
+dhdr_avail <= not lfifo_empty(0); -- FAKE\r
+\r
+-- compare incoming trigger number with stored DHDR information\r
+next_trgnum_match <= '1' when ( IPU_NUMBER_IN = dhdr_fifo_out_int(15 downto 0) ) else '0';\r
+\r
+THE_TRGNUM_MATCH_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( reset_all = '1' ) then\r
+ trgnum_match <= '0';\r
+ my_trg_number <= (others => '0');\r
+ elsif( set_hdr = '1' ) then\r
+ trgnum_match <= next_trgnum_match;\r
+ my_trg_number <= IPU_NUMBER_IN & dhdr_fifo_out_int(15 downto 0);\r
+ end if;\r
+ end if;\r
+end process THE_TRGNUM_MATCH_PROC;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- priority encoding is used to select the next buffer for readout\r
+---------------------------------------------------------------------------\r
+THE_PRI_ENCODER_PROC: process( todo_list, fifo_done )\r
+begin\r
+ if ( todo_list(15 downto 15) = "1" ) then\r
+ next_fifo_sel <= "01111"; next_sel_fifo <= b"1000_0000_0000_0000"; next_fifo_last <= fifo_done(15);\r
+ elsif( todo_list(15 downto 14) = "01" ) then\r
+ next_fifo_sel <= "01110"; next_sel_fifo <= b"0100_0000_0000_0000"; next_fifo_last <= fifo_done(14);\r
+ elsif( todo_list(15 downto 13) = "001" ) then\r
+ next_fifo_sel <= "01101"; next_sel_fifo <= b"0010_0000_0000_0000"; next_fifo_last <= fifo_done(13);\r
+ elsif( todo_list(15 downto 12) = "0001" ) then\r
+ next_fifo_sel <= "01100"; next_sel_fifo <= b"0001_0000_0000_0000"; next_fifo_last <= fifo_done(12);\r
+ elsif( todo_list(15 downto 11) = "00001" ) then\r
+ next_fifo_sel <= "01011"; next_sel_fifo <= b"0000_1000_0000_0000"; next_fifo_last <= fifo_done(11);\r
+ elsif( todo_list(15 downto 10) = "000001" ) then\r
+ next_fifo_sel <= "01010"; next_sel_fifo <= b"0000_0100_0000_0000"; next_fifo_last <= fifo_done(10);\r
+ elsif( todo_list(15 downto 9) = "0000001" ) then\r
+ next_fifo_sel <= "01001"; next_sel_fifo <= b"0000_0010_0000_0000"; next_fifo_last <= fifo_done(9);\r
+ elsif( todo_list(15 downto 8) = "00000001" ) then\r
+ next_fifo_sel <= "01000"; next_sel_fifo <= b"0000_0001_0000_0000"; next_fifo_last <= fifo_done(8);\r
+ elsif( todo_list(15 downto 7) = "000000001" ) then\r
+ next_fifo_sel <= "00111"; next_sel_fifo <= b"0000_0000_1000_0000"; next_fifo_last <= fifo_done(7);\r
+ elsif( todo_list(15 downto 6) = "0000000001" ) then\r
+ next_fifo_sel <= "00110"; next_sel_fifo <= b"0000_0000_0100_0000"; next_fifo_last <= fifo_done(6);\r
+ elsif( todo_list(15 downto 5) = "00000000001" ) then\r
+ next_fifo_sel <= "00101"; next_sel_fifo <= b"0000_0000_0010_0000"; next_fifo_last <= fifo_done(5);\r
+ elsif( todo_list(15 downto 4) = "000000000001" ) then\r
+ next_fifo_sel <= "00100"; next_sel_fifo <= b"0000_0000_0001_0000"; next_fifo_last <= fifo_done(4);\r
+ elsif( todo_list(15 downto 3) = "0000000000001" ) then\r
+ next_fifo_sel <= "00011"; next_sel_fifo <= b"0000_0000_0000_1000"; next_fifo_last <= fifo_done(3);\r
+ elsif( todo_list(15 downto 2) = "00000000000001" ) then\r
+ next_fifo_sel <= "00010"; next_sel_fifo <= b"0000_0000_0000_0100"; next_fifo_last <= fifo_done(2);\r
+ elsif( todo_list(15 downto 1) = "000000000000001" ) then\r
+ next_fifo_sel <= "00001"; next_sel_fifo <= b"0000_0000_0000_0010"; next_fifo_last <= fifo_done(1);\r
+ elsif( todo_list(15 downto 0) = "0000000000000001" ) then\r
+ next_fifo_sel <= "00000"; next_sel_fifo <= b"0000_0000_0000_0001"; next_fifo_last <= fifo_done(0);\r
+ else\r
+ next_fifo_sel <= "10000"; next_sel_fifo <= b"0000_0000_0000_0000"; next_fifo_last <= '0';\r
+ end if;\r
+end process THE_PRI_ENCODER_PROC;\r
+\r
+-- We need to clear single bits during readout here!!!\r
+THE_TODO_LIST_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( reset_all = '1' ) then\r
+ todo_list <= (others => '0');\r
+ elsif( ld_todo = '1' ) then\r
+ todo_list <= next_todo_list; -- store initial todo list\r
+ elsif( comb_ack_todo = '1' ) then\r
+ todo_list <= todo_list and not sel_fifo; -- does this work?!?\r
+ end if;\r
+ end if;\r
+end process THE_TODO_LIST_PROC;\r
+\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- synchronizing process\r
+---------------------------------------------------------------------------\r
+THE_SYNC_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ fifo_sel <= next_fifo_sel;\r
+ sel_fifo <= next_sel_fifo;\r
+ fifo_done <= next_fifo_done;\r
+ fifo_last <= next_fifo_last;\r
+ dhdr_buf_full <= next_dhdr_buf_full;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- backplane wise APV mapping\r
+---------------------------------------------------------------------------\r
+old_apv_num <= fifo_sel(3 downto 0);\r
+\r
+THE_ADC_APV_MAP_MEM: adc_apv_map_mem\r
+port map( ADDRESS(6 downto 4) => MODULE_IN(2 downto 0),\r
+ ADDRESS(3 downto 0) => old_apv_num,\r
+ Q => new_apv_num\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Data multiplexer\r
+---------------------------------------------------------------------------\r
+THE_DATA_MUX_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if ( set_hdr = '1' ) then\r
+ ipu_out_data <= dhdr_fifo_out_int(31 downto 0);\r
+ elsif( comb_st_data(0) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(0)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(0)(20 downto 0);\r
+ elsif( comb_st_data(1) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(1)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(1)(20 downto 0);\r
+ elsif( comb_st_data(2) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(2)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(2)(20 downto 0);\r
+ elsif( comb_st_data(3) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(3)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(3)(20 downto 0);\r
+ elsif( comb_st_data(4) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(4)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(4)(20 downto 0);\r
+ elsif( comb_st_data(5) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(5)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(5)(20 downto 0);\r
+ elsif( comb_st_data(6) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(6)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(6)(20 downto 0);\r
+ elsif( comb_st_data(7) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(7)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(7)(20 downto 0);\r
+ elsif( comb_st_data(8) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(8)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(8)(20 downto 0);\r
+ elsif( comb_st_data(9) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(9)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(9)(20 downto 0);\r
+ elsif( comb_st_data(10) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(10)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(10)(20 downto 0);\r
+ elsif( comb_st_data(11) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(11)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(11)(20 downto 0);\r
+ elsif( comb_st_data(12) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(12)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(12)(20 downto 0);\r
+ elsif( comb_st_data(13) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(13)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(13)(20 downto 0);\r
+ elsif( comb_st_data(14) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(14)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(14)(20 downto 0);\r
+ elsif( comb_st_data(15) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(15)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(15)(20 downto 0);\r
+ end if;\r
+ end if;\r
+end process THE_DATA_MUX_PROC;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- IPU cycle counter... just to be sure\r
+---------------------------------------------------------------------------\r
+THE_CYCLE_COUNTER_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( reset_all = '1' ) then\r
+ cyclectr <= (others => '0');\r
+ elsif( finished = '1' ) then\r
+ cyclectr <= cyclectr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_CYCLE_COUNTER_PROC;\r
+\r
+-- IPU handler status\r
+ipu_status(31 downto 16) <= (others => '0'); -- reserved\r
+ipu_status(15) <= '0'; -- error flag: endpoint not configured\r
+ipu_status(14) <= '0'; -- error flag: synchronisation\r
+ipu_status(13) <= '0'; -- error flag: event has missing data\r
+ipu_status(12) <= not trgnum_match; -- error flag: event not found\r
+ipu_status(11 downto 4) <= (others => '0'); -- reserved\r
+ipu_status(3 downto 0) <= status_bits; -- IPU transfer status \r
+\r
+-- LVL1 and IPU channel release status\r
+release_status(31 downto 16) <= fifo_done;\r
+release_status(15 downto 0) <= (others => '0'); -- BUG\r
+\r
+---------------------------------------------------------------------------\r
+-- Output signals\r
+---------------------------------------------------------------------------\r
+IPU_DATA_OUT <= ipu_out_data;\r
+LVL2_COUNTER_OUT <= std_logic_vector(cyclectr);\r
+IPU_LAST_NUM_OUT <= my_trg_number;\r
+DHDR_BUF_FULL_OUT <= dhdr_buf_full;\r
+\r
+FIFO_0_STATUS_OUT <= fifo_status(0);\r
+FIFO_1_STATUS_OUT <= fifo_status(1);\r
+FIFO_2_STATUS_OUT <= fifo_status(2);\r
+FIFO_3_STATUS_OUT <= fifo_status(3);\r
+FIFO_4_STATUS_OUT <= fifo_status(4);\r
+FIFO_5_STATUS_OUT <= fifo_status(5);\r
+FIFO_6_STATUS_OUT <= fifo_status(6);\r
+FIFO_7_STATUS_OUT <= fifo_status(7);\r
+FIFO_8_STATUS_OUT <= fifo_status(8);\r
+FIFO_9_STATUS_OUT <= fifo_status(9);\r
+FIFO_10_STATUS_OUT <= fifo_status(10);\r
+FIFO_11_STATUS_OUT <= fifo_status(11);\r
+FIFO_12_STATUS_OUT <= fifo_status(12);\r
+FIFO_13_STATUS_OUT <= fifo_status(13);\r
+FIFO_14_STATUS_OUT <= fifo_status(14);\r
+FIFO_15_STATUS_OUT <= fifo_status(15);\r
+IPU_STATUS_OUT <= ipu_status;\r
+RELEASE_STATUS_OUT <= release_status;\r
+\r
+---------------------------------------------------------------------------\r
+-- debug information\r
+---------------------------------------------------------------------------\r
+debug(63 downto 48) <= todo_list;\r
+debug(47 downto 25) <= (others => '0');\r
+debug(24 downto 20) <= fifo_sel;\r
+debug(19 downto 17) <= (others => '0');\r
+debug(16) <= fifo_last;\r
+debug(15 downto 0) <= fifo_done;\r
+\r
+---------------------------------------------------------------------------\r
+-- DEBUG signals\r
+---------------------------------------------------------------------------\r
+DBG_BSM_OUT <= bsm_x;\r
+DBG_OUT <= debug;\r
+\r
+end behavioral;\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+-- Comment: better than the first version, but still a lot of optimization possible.\r
+\r
+-- (1) no more compare tags here. some steps in the FSM can be taken out.\r
+-- (2) no more rst_lvl1_counter signal anymore in the CCR. to be replaced!\r
+\r
+entity real_trg_handler is\r
+port(\r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic;\r
+ TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs\r
+ TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
+ APV_TRGDONE_IN : in std_logic; -- APV trigger statemachine finished (one pulse)\r
+ TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3\r
+ TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2\r
+ TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1\r
+ TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0\r
+ TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers\r
+ TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint\r
+ TRG_TOO_LONG_OUT : out std_logic; -- only for TRG0 channel\r
+ SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number\r
+ -- TRB LVL1 channel signals\r
+ TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag\r
+ TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number\r
+ TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- LVL1 4bit trigger type\r
+ TRB_TINFO_IN : in std_logic_vector(23 downto 0); -- LVL1 24bit trigger information\r
+ TRB_TRGRCVD_IN : in std_logic; -- LVL1 trigger has been received on TRB\r
+ TRB_MISSING_OUT : out std_logic; -- LVL1 trigger without timing trigger\r
+ LVL1_COUNTER_OUT : out std_logic_vector(15 downto 0);\r
+ LVL1_COUNTER_IN : in std_logic_vector(15 downto 0);\r
+ LVL1_LD_COUNTER_IN : in std_logic;\r
+ BUSY_RELEASE_IN : in std_logic; -- common signal from busy calculator\r
+ --\r
+ APV_TRGSEL_OUT : out std_logic_vector(3 downto 0); -- select one APV trigger state machine\r
+ APV_TRGSTART_OUT : out std_logic; -- start an APV trigger state machine\r
+ EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EDS data\r
+ EDS_WE_OUT : out std_logic; -- EDS write enable (general interface)\r
+ EDS_START_OUT : out std_logic; -- separate increment signal for EDS buffer level\r
+ EDS_READY_OUT : out std_logic; -- APV trigger sequence done\r
+ DBG_FRMCTR_OUT : out std_logic_vector(3 downto 0); -- framecounter itself\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
+end;\r
+\r
+architecture behavioral of real_trg_handler is\r
+\r
+-- state machine signals\r
+type STATES is (SLEEP, STORE, START, COUNT, RELAX, CHECK, WAPV, WLVL1, TRBS,\r
+ WEDS, WDEL0, WDEL1, WBUSY, DONE, CNTEVT, BADTRG, TTLTRG);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+-- normal signals\r
+signal trg_comb : std_logic_vector(3 downto 0); -- TRB or hardware inputs\r
+signal trg_q : std_logic_vector(3 downto 0);\r
+signal trg_qq : std_logic_vector(3 downto 0);\r
+signal trg_qqq : std_logic_vector(3 downto 0);\r
+signal trg_qqqq : std_logic_vector(3 downto 0);\r
+signal trg_edge : std_logic_vector(3 downto 0);\r
+signal decoded_trg : std_logic_vector(3 downto 0);\r
+signal todo_start : std_logic_vector(3 downto 0);\r
+signal trg_found : std_logic;\r
+\r
+signal evtctr : unsigned(15 downto 0); -- event counter\r
+signal ce_evtctr : std_logic;\r
+signal next_ce_evtctr : std_logic;\r
+signal frmctr : unsigned(3 downto 0); -- frame counter\r
+signal ce_frmctr : std_logic;\r
+signal next_ce_frmctr : std_logic;\r
+signal todo_ctr : unsigned(3 downto 0);\r
+signal next_todo_done : std_logic;\r
+signal todo_done : std_logic;\r
+signal next_apv_trgstart : std_logic;\r
+signal apv_trgstart : std_logic;\r
+signal eds_data : std_logic_vector(39 downto 0);\r
+signal eds_start : std_logic;\r
+signal next_eds_start : std_logic;\r
+signal eds_we : std_logic;\r
+signal next_eds_we : std_logic;\r
+signal next_eds_ready : std_logic;\r
+signal eds_ready : std_logic; -- end signal, release busy by sending TERM and clean up misc stuff\r
+signal apv_trg_finished : std_logic;\r
+signal next_accept : std_logic; -- we can accept a trigger\r
+signal accept : std_logic;\r
+signal next_missed_trg : std_logic;\r
+signal missed_trg : std_logic;\r
+signal missing_trg : std_logic;\r
+signal next_rst_status : std_logic;\r
+signal rst_status : std_logic;\r
+\r
+signal time_trg : std_logic_vector(3 downto 0);\r
+\r
+-- Information to be collected for the EDS\r
+signal trg_dectrg_reg : std_logic_vector(3 downto 0); -- priority encoded timing trigger (4bit)\r
+signal trg_frmctr_reg : std_logic_vector(3 downto 0); -- frame counter start value (4bit)\r
+signal trg_frmnum_reg : std_logic_vector(3 downto 0); -- number of frames in this event (4bit)\r
+\r
+signal next_store_local : std_logic;\r
+signal store_local : std_logic;\r
+signal next_rst_local : std_logic;\r
+signal rst_local : std_logic;\r
+\r
+signal time_trg_on : std_logic_vector(3 downto 0);\r
+signal time_trg_inv : std_logic_vector(3 downto 0);\r
+\r
+signal big_event_comb : std_logic;\r
+signal tag_sector_match_comb : std_logic;\r
+signal suppress_data_comb : std_logic;\r
+\r
+signal trg_len_ctr : unsigned(8 downto 0); -- 9bit = 5.12us max\r
+signal trg_len_rst : std_logic; \r
+signal trg_len_ce : std_logic; \r
+signal trg_len_done : std_logic;\r
+signal trg_too_long : std_logic;\r
+\r
+signal bsm_x : std_logic_vector(7 downto 0);\r
+\r
+begin\r
+\r
+-- Aliasing the control bits\r
+time_trg_on(3) <= TRG_SETUP_IN(7);\r
+time_trg_inv(3) <= TRG_SETUP_IN(3);\r
+time_trg_on(2) <= TRG_SETUP_IN(6);\r
+time_trg_inv(2) <= TRG_SETUP_IN(2);\r
+time_trg_on(1) <= TRG_SETUP_IN(5);\r
+time_trg_inv(1) <= TRG_SETUP_IN(1);\r
+time_trg_on(0) <= TRG_SETUP_IN(4);\r
+time_trg_inv(0) <= TRG_SETUP_IN(0);\r
+\r
+------------------------------------------------------------\r
+-- Synchronize the external trigger inputs\r
+------------------------------------------------------------\r
+THE_TIME_TRG_3_SYNC: state_sync\r
+port map(\r
+ STATE_A_IN => TIME_TRG_IN(3),\r
+ CLK_B_IN => CLK_IN,\r
+ RESET_B_IN => RESET_IN,\r
+ STATE_B_OUT => time_trg(3)\r
+);\r
+THE_TIME_TRG_2_SYNC: state_sync\r
+port map(\r
+ STATE_A_IN => TIME_TRG_IN(2),\r
+ CLK_B_IN => CLK_IN,\r
+ RESET_B_IN => RESET_IN,\r
+ STATE_B_OUT => time_trg(2)\r
+);\r
+THE_TIME_TRG_1_SYNC: state_sync\r
+port map(\r
+ STATE_A_IN => TIME_TRG_IN(1),\r
+ CLK_B_IN => CLK_IN,\r
+ RESET_B_IN => RESET_IN,\r
+ STATE_B_OUT => time_trg(1)\r
+);\r
+THE_TIME_TRG_0_SYNC: state_sync\r
+port map(\r
+ STATE_A_IN => TIME_TRG_IN(0),\r
+ CLK_B_IN => CLK_IN,\r
+ RESET_B_IN => RESET_IN,\r
+ STATE_B_OUT => time_trg(0)\r
+);\r
+\r
+------------------------------------------------------------\r
+-- For all four possible hardware triggers we combine hardware and TRB inputs\r
+-- TRB slow control trigger inputs are already synchronized to SYSCLK.\r
+------------------------------------------------------------\r
+trg_comb(3) <= ((time_trg(3) xor time_trg_inv(3)) and time_trg_on(3)) or TRB_TRG_IN(3);\r
+trg_comb(2) <= ((time_trg(2) xor time_trg_inv(2)) and time_trg_on(2)) or TRB_TRG_IN(2);\r
+trg_comb(1) <= ((time_trg(1) xor time_trg_inv(1)) and time_trg_on(1)) or TRB_TRG_IN(1);\r
+trg_comb(0) <= ((time_trg(0) xor time_trg_inv(0)) and time_trg_on(0)) or TRB_TRG_IN(0);\r
+\r
+--------------------------------------------------------------------------------------------------\r
+-- trigger length surveillance\r
+--------------------------------------------------------------------------------------------------\r
+THE_TRG_LENGTH_CTR_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if ( (RESET_IN = '1') or (trg_len_rst = '1') ) then\r
+ trg_len_ctr <= (others => '0');\r
+ elsif( trg_len_ce = '1' ) then\r
+ trg_len_ctr <= trg_len_ctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_TRG_LENGTH_CTR_PROC;\r
+\r
+-- Count whenever trigger signal is high\r
+trg_len_ce <= trg_qqqq(0);\r
+-- Reset counter with each rising edge\r
+trg_len_rst <= trg_edge(0);\r
+-- Overflow of counter marks trigger length > 5us\r
+trg_len_done <= '1' when (trg_len_ctr = b"1_1111_1111") else '0';\r
+\r
+THE_TRG_TOO_LONG_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if ( (RESET_IN = '1') or (trg_len_rst = '1') ) then\r
+ trg_too_long <= '0';\r
+ elsif( trg_len_done = '1' ) then\r
+ trg_too_long <= '1';\r
+ end if;\r
+ end if;\r
+end process THE_TRG_TOO_LONG_PROC;\r
+\r
+--------------------------------------------------------------------------------------------------\r
+--------------------------------------------------------------------------------------------------\r
+\r
+------------------------------------------------------------\r
+-- Now we shift the synced signals into shift registers with four FF in a row.\r
+-- This gives us a 16bit pattern in total to decide which trigger input was active.\r
+------------------------------------------------------------\r
+THE_TRG_LENGTH_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ trg_qqqq <= (others => '0');\r
+ trg_qqq <= (others => '0');\r
+ trg_qq <= (others => '0');\r
+ trg_q <= (others => '0');\r
+ else\r
+ trg_qqqq <= trg_qqq;\r
+ trg_qqq <= trg_qq;\r
+ trg_qq <= trg_q;\r
+ trg_q <= trg_comb;\r
+ end if;\r
+ end if;\r
+end process THE_TRG_LENGTH_PROC;\r
+\r
+------------------------------------------------------------\r
+-- Check for rising edges in the signals, with a long steady state signal following.\r
+-- We accept only signals of three clock cycles minimum length (as sent by the TRB_TRG).\r
+------------------------------------------------------------\r
+THE_RISING_EDGES_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ trg_edge <= (others => '0');\r
+ else\r
+ trg_edge(3) <= not trg_qqqq(3) and trg_qqq(3) and trg_qq(3) and trg_q(3);\r
+ trg_edge(2) <= not trg_qqqq(2) and trg_qqq(2) and trg_qq(2) and trg_q(2);\r
+ trg_edge(1) <= not trg_qqqq(1) and trg_qqq(1) and trg_qq(1) and trg_q(1);\r
+ trg_edge(0) <= not trg_qqqq(0) and trg_qqq(0) and trg_qq(0) and trg_q(0);\r
+ end if;\r
+ end if;\r
+end process THE_RISING_EDGES_PROC;\r
+\r
+-- Now we are almost done.\r
+-- The detected edges are priorized.\r
+THE_TRG_PRIORITY_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ decoded_trg <= (others => '0');\r
+ todo_start <= (others => '0');\r
+ trg_found <= '0';\r
+ else\r
+ if( trg_edge(3) = '1' ) then\r
+ decoded_trg <= "1000";\r
+ todo_start <= TRG_3_TODO_IN;\r
+ trg_found <= '1';\r
+ elsif( trg_edge(3 downto 2) = "01" ) then\r
+ decoded_trg <= "0100";\r
+ todo_start <= TRG_2_TODO_IN;\r
+ trg_found <= '1';\r
+ elsif( trg_edge(3 downto 1) = "001" ) then\r
+ decoded_trg <= "0010";\r
+ todo_start <= TRG_1_TODO_IN;\r
+ trg_found <= '1';\r
+ elsif( trg_edge(3 downto 0) = "0001" ) then\r
+ decoded_trg <= "0001";\r
+ todo_start <= TRG_0_TODO_IN;\r
+ trg_found <= '1';\r
+ else\r
+ -- case of "timingtriggerless trigger"?\r
+ decoded_trg <= "0000";\r
+ todo_start <= "0000";\r
+ trg_found <= '0';\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process THE_TRG_PRIORITY_PROC;\r
+\r
+-- We need to store some information for the EDS... from local counters\r
+-- NB: after one cycle this information set is reset to zero!\r
+-- needed for missing timing trigger handling.\r
+THE_LOCALSTORE_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( (RESET_IN = '1') or (rst_local = '1') ) then\r
+ trg_frmctr_reg <= (others => '0');\r
+ trg_frmnum_reg <= (others => '0');\r
+ trg_dectrg_reg <= (others => '0');\r
+ elsif( (accept = '1') and (trg_found = '1') ) then -- the clock cycle before local_store pulse\r
+ trg_frmctr_reg <= std_logic_vector(frmctr);\r
+ trg_frmnum_reg <= todo_start;\r
+ trg_dectrg_reg <= decoded_trg;\r
+ end if;\r
+ end if;\r
+end process THE_LOCALSTORE_PROC;\r
+\r
+-- The ToDo counter: is loaded with the number of APV triggers, and counts down.\r
+THE_TODO_COUNTER_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if ( RESET_IN = '1' ) then\r
+ todo_ctr <= (others => '0');\r
+ elsif( store_local = '1' ) then\r
+ todo_ctr <= unsigned(trg_frmnum_reg);\r
+ elsif( ce_frmctr = '1' ) then\r
+ todo_ctr <= todo_ctr - 1;\r
+ end if;\r
+ end if;\r
+end process THE_TODO_COUNTER_PROC;\r
+next_todo_done <= '1' when (todo_ctr = x"0") else '0';\r
+\r
+THE_TRG_SYNC_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ todo_done <= '0';\r
+ else\r
+ todo_done <= next_todo_done;\r
+ end if;\r
+ end if;\r
+end process THE_TRG_SYNC_PROC;\r
+\r
+-- We store the end pulse from the APV trigger handler, as we need to wait for\r
+-- LVL1 in any case before we can take care of this signal.\r
+THE_TRGDONE_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ apv_trg_finished <= '0';\r
+ elsif( APV_TRGDONE_IN = '1' ) then\r
+ apv_trg_finished <= '1';\r
+ elsif( eds_ready = '1' ) then\r
+ apv_trg_finished <= '0';\r
+ end if;\r
+ end if;\r
+end process THE_TRGDONE_PROC;\r
+\r
+-- A statemachine handles all actions for filling out the trigger information sheet\r
+-- state registers\r
+STATE_MEM: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ ce_evtctr <= '0';\r
+ ce_frmctr <= '0';\r
+ eds_ready <= '0';\r
+ eds_we <= '0';\r
+ eds_start <= '0';\r
+ rst_local <= '0';\r
+ store_local <= '0';\r
+ apv_trgstart <= '0';\r
+ accept <= '1';\r
+ missed_trg <= '0';\r
+ rst_status <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ ce_evtctr <= next_ce_evtctr;\r
+ ce_frmctr <= next_ce_frmctr;\r
+ eds_ready <= next_eds_ready;\r
+ eds_we <= next_eds_we;\r
+ eds_start <= next_eds_start;\r
+ rst_local <= next_rst_local;\r
+ store_local <= next_store_local;\r
+ apv_trgstart <= next_apv_trgstart;\r
+ accept <= next_accept;\r
+ missed_trg <= next_missed_trg;\r
+ rst_status <= next_rst_status;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- state transitions\r
+STATE_TRANSFORM: process( CURRENT_STATE, trg_found, todo_done, TRB_TRGRCVD_IN, apv_trg_finished, \r
+ BUSY_RELEASE_IN, TRB_TTYPE_IN(3), TRB_TINFO_IN(7) )\r
+begin\r
+ NEXT_STATE <= SLEEP; -- avoid latches\r
+ next_ce_evtctr <= '0';\r
+ next_ce_frmctr <= '0';\r
+ next_eds_ready <= '0';\r
+ next_eds_we <= '0';\r
+ next_eds_start <= '0';\r
+ next_rst_local <= '0';\r
+ next_store_local <= '0';\r
+ next_apv_trgstart <= '0';\r
+ next_accept <= '0';\r
+ next_missed_trg <= '0';\r
+ next_rst_status <= '0';\r
+ case CURRENT_STATE is\r
+ -- not good. if no timing trigger was received but a trb trigger arrives, we must do something!\r
+ when SLEEP => if ( trg_found = '1' ) then\r
+ -- normal way: timing trigger found\r
+ NEXT_STATE <= STORE;\r
+ next_store_local <= '1';\r
+ next_eds_start <= '1';\r
+ elsif( (trg_found = '0') and (TRB_TRGRCVD_IN = '1') and (TRB_TTYPE_IN(3) = '1') and (TRB_TINFO_IN(7) = '1') ) then\r
+ NEXT_STATE <= TTLTRG;\r
+ elsif( (trg_found = '0') and (TRB_TRGRCVD_IN = '1') and ((TRB_TTYPE_IN(3) = '0') or (TRB_TINFO_IN(7) = '0')) ) then\r
+ NEXT_STATE <= BADTRG;\r
+ next_missed_trg <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ next_accept <= '1';\r
+ end if;\r
+ when TTLTRG => NEXT_STATE <= TRBS;\r
+ when BADTRG => NEXT_STATE <= TRBS;\r
+ when STORE => NEXT_STATE <= START;\r
+ next_apv_trgstart <= '1';\r
+ when START => NEXT_STATE <= CHECK;\r
+ when CHECK => if( todo_done = '1' ) then\r
+ NEXT_STATE <= WAPV;\r
+ else\r
+ NEXT_STATE <= COUNT;\r
+ next_ce_frmctr <= '1';\r
+ end if;\r
+ when COUNT => NEXT_STATE <= RELAX;\r
+ when RELAX => NEXT_STATE <= CHECK;\r
+ when WAPV => if( apv_trg_finished = '1' ) then\r
+ NEXT_STATE <= WLVL1;\r
+ else\r
+ NEXT_STATE <= WAPV;\r
+ end if;\r
+ when WLVL1 => if( TRB_TRGRCVD_IN = '1' ) then\r
+ NEXT_STATE <= TRBS;\r
+ else\r
+ NEXT_STATE <= WLVL1;\r
+ end if;\r
+ when TRBS => NEXT_STATE <= WEDS;\r
+ next_eds_we <= '1';\r
+ next_rst_local <= '1';\r
+ when WEDS => NEXT_STATE <= CNTEVT;\r
+ next_ce_evtctr <= '1';\r
+ when CNTEVT => NEXT_STATE <= WDEL0;\r
+ when WDEL0 => NEXT_STATE <= WDEL1;\r
+ when WDEL1 => NEXT_STATE <= WBUSY;\r
+ when WBUSY => if( BUSY_RELEASE_IN = '1' ) then\r
+ NEXT_STATE <= DONE;\r
+ next_eds_ready <= '1';\r
+ else\r
+ NEXT_STATE <= WBUSY;\r
+ end if;\r
+ when DONE => if( TRB_TRGRCVD_IN = '0' ) then -- mind the state synchronizer delay!!!\r
+ NEXT_STATE <= SLEEP;\r
+ next_accept <= '1';\r
+ next_rst_status <= '1';\r
+ else\r
+ NEXT_STATE <= DONE;\r
+ end if;\r
+ when others => NEXT_STATE <= SLEEP;\r
+ next_accept <= '1';\r
+ end case;\r
+end process STATE_TRANSFORM;\r
+\r
+-- state decoding\r
+STATE_DECODE: process( CURRENT_STATE )\r
+begin\r
+ case CURRENT_STATE is\r
+ when SLEEP => bsm_x <= x"00";\r
+ when STORE => bsm_x <= x"01";\r
+ when START => bsm_x <= x"02";\r
+ when CHECK => bsm_x <= x"03";\r
+ when COUNT => bsm_x <= x"04";\r
+ when RELAX => bsm_x <= x"14";\r
+ when WAPV => bsm_x <= x"05";\r
+ when WLVL1 => bsm_x <= x"06";\r
+ when TRBS => bsm_x <= x"07";\r
+ when WEDS => bsm_x <= x"0b";\r
+ when WDEL0 => bsm_x <= x"0c";\r
+ when WDEL1 => bsm_x <= x"0d";\r
+ when WBUSY => bsm_x <= x"0e";\r
+ when DONE => bsm_x <= x"0f";\r
+ when CNTEVT => bsm_x <= x"10";\r
+ when BADTRG => bsm_x <= x"11";\r
+ when TTLTRG => bsm_x <= x"12";\r
+ when others => bsm_x <= x"ff";\r
+ end case;\r
+end process STATE_DECODE;\r
+\r
+\r
+-- The event counter: is incremented with each accepted trigger\r
+THE_EVENT_COUNTER_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if ( RESET_IN = '1' ) then\r
+ evtctr <= (others => '0');\r
+ elsif( LVL1_LD_COUNTER_IN = '1' ) then\r
+ evtctr <= unsigned(LVL1_COUNTER_IN); -- update with value from TRBnet counter\r
+ elsif( ce_evtctr = '1' ) then\r
+ evtctr <= evtctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_EVENT_COUNTER_PROC;\r
+\r
+-- The frame counter: is incremented with each 1-0-0 trigger sent to APV\r
+THE_FRAME_COUNTER_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ frmctr <= (others => '0');\r
+ elsif( ce_frmctr = '1' ) then\r
+ frmctr <= frmctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_FRAME_COUNTER_PROC;\r
+\r
+-- If a timing trigger was missing, we simply ignore this LVL1 trigger\r
+THE_MISSED_TRG_REG: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( (RESET_IN = '1') or (rst_status = '1') ) then\r
+ missing_trg <= '0';\r
+ elsif( missed_trg = '1' ) then\r
+ missing_trg <= '1';\r
+ end if;\r
+ end if;\r
+end process THE_MISSED_TRG_REG;\r
+\r
+-- Now for something completely different: as we have two sectors connected\r
+-- to one GbE hub in the final setup, we must do a trick to stay below 64kB \r
+-- subevent size.\r
+-- So in all cases where 128 channels per event are requested, only those ADCM\r
+-- will produce data where the last bit of sector number and trigger number matches.\r
+-- I.e.: odd sectors fire on odd trigger numbers, even sectors on even trigger numbers.\r
+\r
+-- potentially dangerous (aka big) event\r
+big_event_comb <= '1' when (TRB_TINFO_IN(10 downto 8) = b"000") or -- RAW128\r
+ (TRB_TINFO_IN(10 downto 8) = b"001") or -- PED128\r
+ (TRB_TINFO_IN(10 downto 8) = b"010") or -- PED128THR\r
+ (TRB_TINFO_IN(10 downto 8) = b"100") -- NC64PED64\r
+ else '0';\r
+\r
+-- sector number matches trigger number\r
+tag_sector_match_comb <= '1' when ( SECTOR_IN(0) = TRB_TTAG_IN(0) ) else '0';\r
+\r
+-- when to drop data\r
+suppress_data_comb <= (big_event_comb and not tag_sector_match_comb) or TRB_TINFO_IN(0);\r
+\r
+-- EDS bits:\r
+eds_data(39 downto 36) <= trg_frmctr_reg;\r
+eds_data(35 downto 32) <= trg_frmnum_reg;\r
+eds_data(31 downto 16) <= TRB_TTAG_IN;\r
+eds_data(15 downto 8) <= TRB_TRND_IN;\r
+eds_data(7 downto 4) <= TRB_TTYPE_IN;\r
+eds_data(3) <= suppress_data_comb; --trb_tinfo_in(0); -- suppress output bit\r
+eds_data(2 downto 0) <= TRB_TINFO_IN(10 downto 8); -- RICH data configuration bits\r
+\r
+-- output signals\r
+APV_TRGSTART_OUT <= apv_trgstart;\r
+APV_TRGSEL_OUT <= trg_dectrg_reg;\r
+\r
+EDS_DATA_OUT <= eds_data;\r
+EDS_START_OUT <= eds_start;\r
+EDS_WE_OUT <= eds_we;\r
+EDS_READY_OUT <= eds_ready;\r
+TRB_MISSING_OUT <= missing_trg;\r
+LVL1_COUNTER_OUT <= std_logic_vector(evtctr);\r
+TRG_FOUND_OUT <= trg_found;\r
+TRG_TOO_LONG_OUT <= trg_too_long;\r
+\r
+-- Debug signals\r
+BSM_OUT <= bsm_x;\r
+\r
+DEBUG_OUT(63 downto 32) <= (others => '0');\r
+DEBUG_OUT(31 downto 24) <= std_logic_vector(evtctr(7 downto 0));\r
+DEBUG_OUT(23 downto 16) <= TRB_TTAG_IN(7 downto 0);\r
+DEBUG_OUT(15) <= ce_evtctr;\r
+DEBUG_OUT(14) <= '0';\r
+DEBUG_OUT(13) <= missing_trg;\r
+DEBUG_OUT(12) <= accept;\r
+DEBUG_OUT(11) <= '0';\r
+DEBUG_OUT(10) <= '0';\r
+DEBUG_OUT(9) <= TRB_TRGRCVD_IN;\r
+DEBUG_OUT(8) <= trg_found;\r
+DEBUG_OUT(7 downto 0) <= bsm_x;\r
+\r
+DBG_FRMCTR_OUT <= std_logic_vector(frmctr);\r
+\r
+end behavioral;\r
+\r
SD_LOS_IN : in std_logic;
ONEWIRE_INOUT : inout std_logic;
-- common regIO status / control registers
- COMMON_STAT_REG_IN : in std_logic_vector(8*32-1 downto 0); -- common status register, bit definitions like in WIKI
- COMMON_CTRL_REG_OUT : out std_logic_vector(3*32-1 downto 0); -- common control register, bit definitions like in WIKI
+ COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI
+ COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI
-- status register input to regIO / control register output from regIO
CONTROL_OUT : out std_logic_vector(63 downto 0);
STATUS_IN : in std_logic_vector(127 downto 0);
REGIO_INIT_BOARD_INFO => x"5aa5_3cc3",
REGIO_INIT_ENDPOINT_ID => x"0001",
REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
- -- REGIO_COMPILE_VERSION => x"0003",
+ REGIO_COMPILE_VERSION => x"0003",
REGIO_HARDWARE_VERSION => x"3300_0000", -- ADCMv3 signature
REGIO_USE_1WIRE_INTERFACE => c_YES,
TIMING_TRIGGER_RAW => c_YES,
MED_READ_OUT => med_read_out_int,
MED_STAT_OP_IN => med_stat_op,
MED_CTRL_OP_OUT => med_ctrl_op,
-
- -- LVL1 trigger APL
+ -- LVL1 trigger APL
LVL1_TRG_VALID_TIMING_OUT => open, --valid timing trigger has been received
LVL1_TRG_VALID_NOTIMING_OUT => open, --valid trigger without timing trigger has been received
LVL1_TRG_INVALID_OUT => open, --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN,
LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN,
LVL1_INT_TRG_NUMBER_OUT => open, -- internal trigger number from LVL1 endpoint
-
- -- IPU Port
+ -- IPU Port
IPU_NUMBER_OUT => IPU_NUMBER_OUT,
IPU_READOUT_TYPE_OUT => open, -- 4bit readout type
IPU_INFORMATION_OUT => IPU_INFORMATION_OUT,
IPU_READ_OUT => IPU_READ_OUT,
IPU_LENGTH_IN => IPU_LENGTH_IN,
IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN,
-
- -- Slow Control Data Port
+ -- Slow Control Data Port
REGIO_COMMON_STAT_REG_IN => common_stat_reg,
REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg,
REGIO_REGISTERS_IN => regio_stat_regs,
COMMON_CTRL_REG_STROBE => common_ctrl_reg_strobe, -- [1] means update on internal trigger number
STAT_REG_STROBE => open,
CTRL_REG_STROBE => open,
-
- --following ports only used when using internal data port
+ --following ports only used when using internal data port
REGIO_ADDR_OUT => REGIO_ADDR_OUT,
REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT,
REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT,
REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN,
REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN,
REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT,
-
- --IDRAM is used if no 1-wire interface, onewire used otherwise
+ --IDRAM is used if no 1-wire interface, onewire used otherwise
REGIO_IDRAM_DATA_IN => x"0000", -- not used
REGIO_IDRAM_DATA_OUT => open, -- not used
REGIO_IDRAM_ADDR_IN => "000", -- not used
REGIO_ONEWIRE_INOUT => ONEWIRE_INOUT,
REGIO_ONEWIRE_MONITOR_IN => '1', -- not used
REGIO_ONEWIRE_MONITOR_OUT => open, -- not used
-
- -- New stuff
+ -- New stuff
GLOBAL_TIME_OUT => open,
LOCAL_TIME_OUT => open,
TIME_SINCE_LAST_TRG_OUT => open,
TIMER_TICKS_OUT(1) => tick_1ms, -- ms ticks
TIMER_TICKS_OUT(0) => open, -- us ticks
-
- -- Status and debug
+ -- Status and debug
STAT_DEBUG_IPU => open,
STAT_DEBUG_1 => stat_debug_1, --open,
STAT_DEBUG_2 => open,
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.numeric_std.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.version.all;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.adcmv3_components.all;
+
+entity rich_trb is
+port(
+ CLK100M_IN : in std_logic; -- SerDes exclusive clock
+ SYSCLK_IN : in std_logic; -- fabric clock
+ RESET_IN : in std_logic; -- synchronous reset
+ -- SFP connections
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_PRESENT_IN : in std_logic;
+ SD_TXDIS_OUT : out std_logic;
+ SD_LOS_IN : in std_logic;
+ ONEWIRE_INOUT : inout std_logic;
+ -- common regIO status / control registers
+ COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI
+ COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI
+ -- status register input to regIO / control register output from regIO
+ CONTROL_OUT : out std_logic_vector(63 downto 0);
+ STATUS_IN : in std_logic_vector(127 downto 0);
+ -- LVL1 signals
+ LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);
+ LVL1_TRG_RECEIVED_OUT : out std_logic;
+ LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
+ LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);
+ LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);
+ LVL1_TRG_RELEASE_IN : in std_logic;
+ LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
+ LVL1_INT_TRG_UPDATE_OUT : out std_logic;
+ TIMING_TRG_FOUND_IN : in std_logic;
+ -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-)
+ IPU_NUMBER_OUT : out std_logic_vector(15 downto 0); -- trigger tag
+ IPU_INFORMATION_OUT : out std_logic_vector(7 downto 0); -- trigger information
+ IPU_START_READOUT_OUT : out std_logic; -- gimme data!
+ IPU_DATA_IN : in std_logic_vector(31 downto 0); -- detector data, equipped with DHDR
+ IPU_DATAREADY_IN : in std_logic; -- data is valid
+ IPU_READOUT_FINISHED_IN : in std_logic; -- no more data, end transfer, send TRM
+ IPU_READ_OUT : out std_logic; -- read strobe, low every second cycle
+ IPU_LENGTH_IN : in std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)
+ IPU_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern
+ -- regIO bus
+ REGIO_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);
+ REGIO_READ_ENABLE_OUT : out std_logic;
+ REGIO_WRITE_ENABLE_OUT : out std_logic;
+ REGIO_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);
+ REGIO_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);
+ REGIO_DATAREADY_IN : in std_logic;
+ REGIO_NO_MORE_DATA_IN : in std_logic;
+ REGIO_WRITE_ACK_IN : in std_logic;
+ REGIO_UNKNOWN_ADDR_IN : in std_logic;
+ REGIO_TIMEOUT_OUT : out std_logic;
+ -- status LEDs
+ LED_LINK_STAT : out std_logic;
+ LED_LINK_TXD : out std_logic;
+ LED_LINK_RXD : out std_logic;
+ LINK_BSM_OUT : out std_logic_vector(3 downto 0);
+ RESET_OUT : out std_logic;
+ TICK_10S_OUT : out std_logic;
+ -- Debug
+ DEBUG : out std_logic_vector(63 downto 0)
+);
+end entity;
+
+architecture rich_arch of rich_trb is
+
+-- Placer Directives
+attribute HGROUP : string;
+-- for whole architecture
+attribute HGROUP of rich_arch : architecture is "RICH_TRB_group";
+
+-- Signals
+signal clk_en : std_logic;
+signal med_data_in_int : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+signal med_packet_num_in_int : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+signal med_dataready_in_int : std_logic;
+signal med_read_out_int : std_logic;
+signal med_data_out_int : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+signal med_packet_num_out_int : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+signal med_dataready_out_int : std_logic;
+signal med_read_in_int : std_logic;
+signal med_stat_debug : std_logic_vector(63 downto 0);
+signal med_ctrl_op : std_logic_vector(15 downto 0);
+signal med_stat_op : std_logic_vector(15 downto 0);
+
+-- general purpose control and status registers in regIO
+signal regio_ctrl_regs : std_logic_vector(32*2-1 downto 0);
+signal regio_stat_regs : std_logic_vector(32*4-1 downto 0);
+
+signal common_stat_reg : std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0);
+signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0);
+signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+
+signal debug_x : std_logic_vector(63 downto 0);
+
+signal stat_debug_1 : std_logic_vector(31 downto 0);
+
+signal tick_1ms : std_logic;
+signal counter_10s : unsigned(13 downto 0);
+signal next_rst_counter_10s : std_logic;
+signal rst_counter_10s : std_logic;
+signal ce_counter_10s : std_logic;
+signal next_tick_10s : std_logic;
+signal tick_10s : std_logic;
+
+begin
+
+-- Debug
+debug <= debug_x;
+
+-- Clock assignment. We don't use CLK_EN really in our designs.
+clk_en <= '1';
+
+------------------------------------------------------------------------------------
+-- Serdes
+------------------------------------------------------------------------------------
+THE_MEDIA_INTERFACE : trb_net16_med_ecp_sfp_gbe
+generic map(
+ SERDES_NUM => 2
+)
+port map(
+ CLK => CLK100M_IN,
+ SYSCLK => SYSCLK_IN,
+ RESET => RESET_IN,
+ CLEAR => '0',
+ CLK_EN => clk_en,
+ --Internal Connection
+ MED_DATA_IN => med_data_out_int,
+ MED_PACKET_NUM_IN => med_packet_num_out_int,
+ MED_DATAREADY_IN => med_dataready_out_int,
+ MED_READ_OUT => med_read_in_int,
+ MED_DATA_OUT => med_data_in_int,
+ MED_PACKET_NUM_OUT => med_packet_num_in_int,
+ MED_DATAREADY_OUT => med_dataready_in_int,
+ MED_READ_IN => med_read_out_int,
+ REFCLK2CORE_OUT => open,
+ --SFP Connection
+ SD_RXD_P_IN => SD_RXD_P_IN,
+ SD_RXD_N_IN => SD_RXD_N_IN,
+ SD_TXD_P_OUT => SD_TXD_P_OUT,
+ SD_TXD_N_OUT => SD_TXD_N_OUT,
+ SD_REFCLK_P_IN => '1',
+ SD_REFCLK_N_IN => '0',
+ SD_PRSNT_N_IN => SD_PRESENT_IN,
+ SD_LOS_IN => SD_LOS_IN,
+ SD_TXDIS_OUT => SD_TXDIS_OUT,
+ -- Status and control port
+ STAT_OP => med_stat_op,
+ CTRL_OP => med_ctrl_op, -- input
+ STAT_DEBUG => med_stat_debug,
+ CTRL_DEBUG => (others => '0')
+);
+
+------------------------------------------------------------------------------------
+-- Debug signals
+------------------------------------------------------------------------------------
+debug_x(63 downto 47) <= med_stat_debug(63 downto 47);
+debug_x(46 downto 42) <= (others => '0');
+debug_x(41) <= med_read_out_int; -- MED_READ_IN
+debug_x(40) <= med_dataready_in_int; -- MED_DATAREADY_OUT
+debug_x(39 downto 37) <= med_packet_num_in_int; -- MED_PACKET_NUM_OUT
+debug_x(36 downto 21) <= med_data_in_int; -- MED_DATA_OUT
+debug_x(20) <= med_read_in_int; -- MED_READ_OUT
+debug_x(19) <= med_dataready_out_int; -- MED_DATAREADY_IN
+debug_x(18 downto 16) <= med_packet_num_out_int; -- MED_PACKET_NUM_IN
+--debug_x(15 downto 0) <= med_data_out; -- MED_DATA_IN
+debug_x(15 downto 7) <= (others => '0');
+debug_x(6 downto 0) <= med_stat_debug(30 downto 24);
+
+------------------------------------------------------------------------------------
+-- Full featured HADES endpoint
+------------------------------------------------------------------------------------
+THE_UNIFIED_ENDPOINT: trb_net16_endpoint_hades_full
+generic map(
+ USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
+ INIT_CAN_SEND_DATA => (c_NO,c_NO,c_NO,c_NO), -- was c_YES before?
+ REPLY_CAN_SEND_DATA => (c_YES,c_YES,c_YES,c_YES),
+ REPLY_CAN_RECEIVE_DATA => (c_NO,c_NO,c_NO,c_NO),
+ BROADCAST_BITMASK => x"fb", -- RICH uses 0xfffb as subnet mask for broadcasts
+ REGIO_NUM_STAT_REGS => 2, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0]
+ REGIO_NUM_CTRL_REGS => 1, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0]
+ --standard values for output registers
+ REGIO_INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" &
+ x"00000000_00000000_00000000_00000000" &
+ x"00000000_00000000_00000000_00000000" &
+ x"00000000_00000000_00000000_00000000",
+ --set to 0 for unused ctrl registers to save resources
+ REGIO_USED_CTRL_REGS => "0000000000000001",
+ --set to 0 for each unused bit in a register
+ REGIO_USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
+ x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
+ x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
+ x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF",
+ REGIO_USE_DAT_PORT => c_YES,
+ REGIO_INIT_ADDRESS => x"fb00", -- useless, as no preload is done in this register!
+ REGIO_INIT_UNIQUE_ID => x"dead_beef_affe_d00f",
+ REGIO_INIT_BOARD_INFO => x"5aa5_3cc3",
+ REGIO_INIT_ENDPOINT_ID => x"0001",
+ REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
+ REGIO_COMPILE_VERSION => x"0003",
+ REGIO_HARDWARE_VERSION => x"3300_0000", -- ADCMv3 signature
+ REGIO_USE_1WIRE_INTERFACE => c_YES,
+ CLOCK_FREQUENCY => 100
+)
+port map(
+ CLK => SYSCLK_IN,
+ RESET => RESET_IN,
+ CLK_EN => clk_en,
+ -- Media direction port
+ MED_DATAREADY_OUT => med_dataready_out_int,
+ MED_DATA_OUT => med_data_out_int,
+ MED_PACKET_NUM_OUT => med_packet_num_out_int,
+ MED_READ_IN => med_read_in_int,
+ MED_DATAREADY_IN => med_dataready_in_int,
+ MED_DATA_IN => med_data_in_int,
+ MED_PACKET_NUM_IN => med_packet_num_in_int,
+ MED_READ_OUT => med_read_out_int,
+ MED_STAT_OP_IN => med_stat_op,
+ MED_CTRL_OP_OUT => med_ctrl_op,
+ -- LVL1 trigger APL
+ LVL1_TRG_VALID_TIMING_OUT => open, --valid timing trigger has been received
+ LVL1_TRG_VALID_NOTIMING_OUT => open, --valid trigger without timing trigger has been received
+ LVL1_TRG_INVALID_OUT => open, --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
+ LVL1_TRG_DATA_VALID_OUT => LVL1_TRG_RECEIVED_OUT,
+ TRG_TIMING_TRG_RECEIVED_IN => TIMING_TRG_FOUND_IN,
+ LVL1_TRG_TYPE_OUT => LVL1_TRG_TYPE_OUT,
+ LVL1_TRG_NUMBER_OUT => LVL1_TRG_NUMBER_OUT,
+ LVL1_TRG_CODE_OUT => LVL1_TRG_CODE_OUT,
+ LVL1_TRG_INFORMATION_OUT => LVL1_TRG_INFORMATION_OUT,
+ LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN,
+ LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN,
+ LVL1_INT_TRG_NUMBER_OUT => open, -- internal trigger number from LVL1 endpoint
+ -- IPU Port
+ IPU_NUMBER_OUT => IPU_NUMBER_OUT,
+ IPU_READOUT_TYPE_OUT => open, -- 4bit readout type
+ IPU_INFORMATION_OUT => IPU_INFORMATION_OUT,
+ IPU_START_READOUT_OUT => IPU_START_READOUT_OUT,
+ IPU_DATA_IN => IPU_DATA_IN,
+ IPU_DATAREADY_IN => IPU_DATAREADY_IN,
+ IPU_READOUT_FINISHED_IN => IPU_READOUT_FINISHED_IN,
+ IPU_READ_OUT => IPU_READ_OUT,
+ IPU_LENGTH_IN => IPU_LENGTH_IN,
+ IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN,
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg,
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg,
+ REGIO_REGISTERS_IN => regio_stat_regs,
+ REGIO_REGISTERS_OUT => regio_ctrl_regs,
+ COMMON_STAT_REG_STROBE => open,
+ COMMON_CTRL_REG_STROBE => common_ctrl_reg_strobe, -- [1] means update on internal trigger number
+ STAT_REG_STROBE => open,
+ CTRL_REG_STROBE => open,
+ --following ports only used when using internal data port
+ REGIO_ADDR_OUT => REGIO_ADDR_OUT,
+ REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT,
+ REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT,
+ REGIO_DATA_OUT => REGIO_DATA_OUT,
+ REGIO_DATA_IN => REGIO_DATA_IN,
+ REGIO_DATAREADY_IN => REGIO_DATAREADY_IN,
+ REGIO_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN,
+ REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN,
+ REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN,
+ REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT,
+ --IDRAM is used if no 1-wire interface, onewire used otherwise
+ REGIO_IDRAM_DATA_IN => x"0000", -- not used
+ REGIO_IDRAM_DATA_OUT => open, -- not used
+ REGIO_IDRAM_ADDR_IN => "000", -- not used
+ REGIO_IDRAM_WR_IN => '0', -- not used
+ REGIO_ONEWIRE_INOUT => ONEWIRE_INOUT,
+ REGIO_ONEWIRE_MONITOR_IN => '1', -- not used
+ REGIO_ONEWIRE_MONITOR_OUT => open, -- not used
+ -- New stuff
+ GLOBAL_TIME_OUT => open,
+ LOCAL_TIME_OUT => open,
+ TIME_SINCE_LAST_TRG_OUT => open,
+ TIMER_TICKS_OUT(1) => tick_1ms, -- ms ticks
+ TIMER_TICKS_OUT(0) => open, -- us ticks
+ -- Status and debug
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => stat_debug_1, --open,
+ STAT_DEBUG_2 => open,
+ MED_STAT_OP => open,
+ CTRL_MPLEX => x"00000000",
+ IOBUF_CTRL_GEN => x"00000000_00000000_00000000_00000000",
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open
+);
+
+------------------------------------------------------------------------------------
+-- 10s counter
+------------------------------------------------------------------------------------
+THE_TEN_SEC_CTR_PROC: process( SYSCLK_IN )
+begin
+ if( rising_edge(SYSCLK_IN) ) then
+ if ( rst_counter_10s = '1' ) then
+ counter_10s <= (others => '0');
+ elsif( ce_counter_10s = '1' ) then
+ counter_10s <= counter_10s + 1;
+ end if;
+ rst_counter_10s <= next_rst_counter_10s;
+ tick_10s <= next_tick_10s;
+ end if;
+end process THE_TEN_SEC_CTR_PROC;
+
+ce_counter_10s <= tick_1ms;
+
+next_rst_counter_10s <= '1' when (((counter_10s = 9765) and (ce_counter_10s = '1')) or (RESET_IN = '1')) else '0';
+
+next_tick_10s <= rst_counter_10s;
+
+------------------------------------------------------------------------------------
+-- Control register assignment
+------------------------------------------------------------------------------------
+
+-- Common status register
+common_stat_reg(COMMON_STAT_REG'left downto 32) <= COMMON_STAT_REG_IN(63 downto 32);
+common_stat_reg(31 downto 20) <= (others => '0'); -- already taken by TEMP of 1WID
+common_stat_reg(19 downto 0) <= COMMON_STAT_REG_IN(19 downto 0);
+
+-- Common control register
+COMMON_CTRL_REG_OUT <= common_ctrl_reg;
+
+-- User status register
+regio_stat_regs <= STATUS_IN;
+CONTROL_OUT <= regio_ctrl_regs;
+LVL1_INT_TRG_UPDATE_OUT <= common_ctrl_reg_strobe(1);
+LVL1_INT_TRG_NUMBER_OUT <= common_ctrl_reg(47 downto 32);
+
+-- FPGA LEDs
+LED_LINK_STAT <= not med_stat_op(9); -- link status
+LED_LINK_RXD <= not med_stat_op(10); -- not med_packet_num_in(2); -- data receive
+LED_LINK_TXD <= not med_stat_op(11); -- data transmit
+
+-- Output signals
+LINK_BSM_OUT <= med_stat_op(7 downto 4); -- LSM state bits
+RESET_OUT <= med_stat_op(13); -- TRB generated reset
+
+end architecture;
+
\ No newline at end of file
architecture Behavioral of slave_bus is\r
\r
-- Signals\r
-constant NUM_PORTS : integer := 18;\r
-signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0);\r
-signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0);\r
+signal slv_read : std_logic_vector(18-1 downto 0);\r
+signal slv_write : std_logic_vector(18-1 downto 0);\r
signal slv_busy : std_logic_vector(18-1 downto 0);\r
-signal slv_no_more_data : std_logic_vector(NUM_PORTS-1 downto 0);\r
-signal slv_ack : std_logic_vector(NUM_PORTS-1 downto 0);\r
-signal slv_addr : std_logic_vector(NUM_PORTS*16-1 downto 0);\r
-signal slv_data_rd : std_logic_vector(NUM_PORTS*32-1 downto 0);\r
-signal slv_data_wr : std_logic_vector(NUM_PORTS*32-1 downto 0);\r
-signal slv_unknown_addr : std_logic_vector(NUM_PORTS-1 downto 0);\r
+signal slv_ack : std_logic_vector(18-1 downto 0);\r
+signal slv_addr : std_logic_vector(18*16-1 downto 0);\r
+signal slv_data_rd : std_logic_vector(18*32-1 downto 0);\r
+signal slv_data_wr : std_logic_vector(18*32-1 downto 0);\r
\r
-- SPI controller BRAM lines\r
signal spi_bram_addr : std_logic_vector(7 downto 0);\r
-- Bus handler: acts as bridge between RegIO and the FPGA internal slave bus\r
THE_BUS_HANDLER: trb_net16_regio_bus_handler\r
generic map(\r
- PORT_NUMBER => NUM_PORTS,\r
+ PORT_NUMBER => 18,\r
PORT_ADDRESSES => ( 0 => x"a000", -- pedestal memories\r
1 => x"a800", -- threshold memories\r
2 => x"8040", -- I2C master\r
15 => 4, -- FIFO status registers\r
16 => 0, -- LVL1 release status register\r
17 => 0, -- IPU handler status register\r
- others => 0),\r
- PORT_MASK_ENABLE => 1\r
- )\r
+ others => 0)\r
+)\r
port map(\r
CLK => CLK_IN,\r
RESET => RESET_IN,\r
DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_OUT,\r
DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_OUT,\r
DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT,\r
-\r
- -- All Slow Control Ports\r
- BUS_READ_ENABLE_OUT => slv_read,\r
- BUS_WRITE_ENABLE_OUT => slv_write,\r
- BUS_DATA_OUT => slv_data_wr,\r
- BUS_DATA_IN => slv_data_rd,\r
- BUS_ADDR_OUT => slv_addr,\r
- BUS_TIMEOUT_OUT => open,\r
- BUS_DATAREADY_IN => slv_ack,\r
- BUS_WRITE_ACK_IN => slv_ack,\r
- BUS_NO_MORE_DATA_IN => slv_no_more_data,\r
- BUS_UNKNOWN_ADDR_IN => slv_unknown_addr,\r
-\r
+ -- pedestal memories\r
+ BUS_READ_ENABLE_OUT(0) => slv_read(0),\r
+ BUS_WRITE_ENABLE_OUT(0) => slv_write(0),\r
+ BUS_DATA_OUT(0*32+31 downto 0*32) => slv_data_wr(0*32+31 downto 0*32),\r
+ BUS_DATA_IN(0*32+31 downto 0*32) => slv_data_rd(0*32+31 downto 0*32),\r
+ BUS_ADDR_OUT(0*16+15 downto 0*16) => slv_addr(0*16+15 downto 0*16),\r
+ BUS_TIMEOUT_OUT(0) => open,\r
+ BUS_DATAREADY_IN(0) => slv_ack(0),\r
+ BUS_WRITE_ACK_IN(0) => slv_ack(0),\r
+ BUS_NO_MORE_DATA_IN(0) => slv_busy(0),\r
+ BUS_UNKNOWN_ADDR_IN(0) => '0',\r
+ -- threshold memories\r
+ BUS_READ_ENABLE_OUT(1) => slv_read(1),\r
+ BUS_WRITE_ENABLE_OUT(1) => slv_write(1),\r
+ BUS_DATA_OUT(1*32+31 downto 1*32) => slv_data_wr(1*32+31 downto 1*32),\r
+ BUS_DATA_IN(1*32+31 downto 1*32) => slv_data_rd(1*32+31 downto 1*32),\r
+ BUS_ADDR_OUT(1*16+15 downto 1*16) => slv_addr(1*16+15 downto 1*16),\r
+ BUS_TIMEOUT_OUT(1) => open,\r
+ BUS_DATAREADY_IN(1) => slv_ack(1),\r
+ BUS_WRITE_ACK_IN(1) => slv_ack(1),\r
+ BUS_NO_MORE_DATA_IN(1) => slv_busy(1),\r
+ BUS_UNKNOWN_ADDR_IN(1) => '0',\r
+ -- I2C master\r
+ BUS_READ_ENABLE_OUT(2) => slv_read(2),\r
+ BUS_WRITE_ENABLE_OUT(2) => slv_write(2),\r
+ BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32),\r
+ BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32),\r
+ BUS_ADDR_OUT(2*16+15 downto 2*16) => open,\r
+ BUS_TIMEOUT_OUT(2) => open,\r
+ BUS_DATAREADY_IN(2) => slv_ack(2),\r
+ BUS_WRITE_ACK_IN(2) => slv_ack(2),\r
+ BUS_NO_MORE_DATA_IN(2) => slv_busy(2),\r
+ BUS_UNKNOWN_ADDR_IN(2) => '0',\r
+ -- OneWire master\r
+ BUS_READ_ENABLE_OUT(3) => slv_read(3),\r
+ BUS_WRITE_ENABLE_OUT(3) => slv_write(3),\r
+ BUS_DATA_OUT(3*32+31 downto 3*32) => slv_data_wr(3*32+31 downto 3*32),\r
+ BUS_DATA_IN(3*32+31 downto 3*32) => slv_data_rd(3*32+31 downto 3*32),\r
+ BUS_ADDR_OUT(3*16+15 downto 3*16) => slv_addr(3*16+15 downto 3*16),\r
+ BUS_TIMEOUT_OUT(3) => open,\r
+ BUS_DATAREADY_IN(3) => slv_ack(3),\r
+ BUS_WRITE_ACK_IN(3) => slv_ack(3),\r
+ BUS_NO_MORE_DATA_IN(3) => slv_busy(3),\r
+ BUS_UNKNOWN_ADDR_IN(3) => '0',\r
+ -- SPI control registers\r
+ BUS_READ_ENABLE_OUT(4) => slv_read(4),\r
+ BUS_WRITE_ENABLE_OUT(4) => slv_write(4),\r
+ BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32),\r
+ BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32),\r
+ BUS_ADDR_OUT(4*16+15 downto 4*16) => slv_addr(4*16+15 downto 4*16),\r
+ BUS_TIMEOUT_OUT(4) => open,\r
+ BUS_DATAREADY_IN(4) => slv_ack(4),\r
+ BUS_WRITE_ACK_IN(4) => slv_ack(4),\r
+ BUS_NO_MORE_DATA_IN(4) => slv_busy(4),\r
+ BUS_UNKNOWN_ADDR_IN(4) => '0',\r
+ -- SPI data memory\r
+ BUS_READ_ENABLE_OUT(5) => slv_read(5),\r
+ BUS_WRITE_ENABLE_OUT(5) => slv_write(5),\r
+ BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32),\r
+ BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32),\r
+ BUS_ADDR_OUT(5*16+15 downto 5*16) => slv_addr(5*16+15 downto 5*16),\r
+ BUS_TIMEOUT_OUT(5) => open,\r
+ BUS_DATAREADY_IN(5) => slv_ack(5),\r
+ BUS_WRITE_ACK_IN(5) => slv_ack(5),\r
+ BUS_NO_MORE_DATA_IN(5) => slv_busy(5),\r
+ BUS_UNKNOWN_ADDR_IN(5) => '0',\r
+ -- ADC 0 SPI control registers\r
+ BUS_READ_ENABLE_OUT(6) => slv_read(6),\r
+ BUS_WRITE_ENABLE_OUT(6) => slv_write(6),\r
+ BUS_DATA_OUT(6*32+31 downto 6*32) => slv_data_wr(6*32+31 downto 6*32),\r
+ BUS_DATA_IN(6*32+31 downto 6*32) => slv_data_rd(6*32+31 downto 6*32),\r
+ BUS_ADDR_OUT(6*16+15 downto 6*16) => open,\r
+ BUS_TIMEOUT_OUT(6) => open,\r
+ BUS_DATAREADY_IN(6) => slv_ack(6),\r
+ BUS_WRITE_ACK_IN(6) => slv_ack(6),\r
+ BUS_NO_MORE_DATA_IN(6) => slv_busy(6),\r
+ BUS_UNKNOWN_ADDR_IN(6) => '0',\r
+ -- ADC 1 SPI control registers\r
+ BUS_READ_ENABLE_OUT(7) => slv_read(7),\r
+ BUS_WRITE_ENABLE_OUT(7) => slv_write(7),\r
+ BUS_DATA_OUT(7*32+31 downto 7*32) => slv_data_wr(7*32+31 downto 7*32),\r
+ BUS_DATA_IN(7*32+31 downto 7*32) => slv_data_rd(7*32+31 downto 7*32),\r
+ BUS_ADDR_OUT(7*16+15 downto 7*16) => open,\r
+ BUS_TIMEOUT_OUT(7) => open,\r
+ BUS_DATAREADY_IN(7) => slv_ack(7),\r
+ BUS_WRITE_ACK_IN(7) => slv_ack(7),\r
+ BUS_NO_MORE_DATA_IN(7) => slv_busy(7),\r
+ BUS_UNKNOWN_ADDR_IN(7) => '0',\r
+ -- APV control / status registers\r
+ BUS_READ_ENABLE_OUT(8) => slv_read(8),\r
+ BUS_WRITE_ENABLE_OUT(8) => slv_write(8),\r
+ BUS_DATA_OUT(8*32+31 downto 8*32) => slv_data_wr(8*32+31 downto 8*32),\r
+ BUS_DATA_IN(8*32+31 downto 8*32) => slv_data_rd(8*32+31 downto 8*32),\r
+ BUS_ADDR_OUT(8*16+15 downto 8*16) => slv_addr(8*16+15 downto 8*16),\r
+ BUS_TIMEOUT_OUT(8) => open,\r
+ BUS_DATAREADY_IN(8) => slv_ack(8),\r
+ BUS_WRITE_ACK_IN(8) => slv_ack(8),\r
+ BUS_NO_MORE_DATA_IN(8) => slv_busy(8),\r
+ BUS_UNKNOWN_ADDR_IN(8) => '0',\r
+ -- ADC / PLL / trigger ctrl register\r
+ BUS_READ_ENABLE_OUT(11 downto 9) => slv_read(11 downto 9),\r
+ BUS_WRITE_ENABLE_OUT(11 downto 9) => slv_write(11 downto 9),\r
+ BUS_DATA_OUT(11*32+31 downto 9*32) => slv_data_wr(11*32+31 downto 9*32),\r
+ BUS_DATA_IN(11*32+31 downto 9*32) => slv_data_rd(11*32+31 downto 9*32),\r
+ BUS_ADDR_OUT(11*16+15 downto 9*16) => open,\r
+ BUS_TIMEOUT_OUT(11 downto 9) => open,\r
+ BUS_DATAREADY_IN(11 downto 9) => slv_ack(11 downto 9),\r
+ BUS_WRITE_ACK_IN(11 downto 9) => slv_ack(11 downto 9),\r
+ BUS_NO_MORE_DATA_IN(11 downto 9) => slv_busy(11 downto 9),\r
+ BUS_UNKNOWN_ADDR_IN(11 downto 9) => (others => '0'),\r
+ -- ADC0 snooper\r
+ BUS_READ_ENABLE_OUT(12) => slv_read(12),\r
+ BUS_WRITE_ENABLE_OUT(12) => slv_write(12),\r
+ BUS_DATA_OUT(12*32+31 downto 12*32) => slv_data_wr(12*32+31 downto 12*32),\r
+ BUS_DATA_IN(12*32+31 downto 12*32) => slv_data_rd(12*32+31 downto 12*32),\r
+ BUS_ADDR_OUT(12*16+15 downto 12*16) => slv_addr(12*16+15 downto 12*16),\r
+ BUS_TIMEOUT_OUT(12) => open,\r
+ BUS_DATAREADY_IN(12) => slv_ack(12),\r
+ BUS_WRITE_ACK_IN(12) => slv_ack(12),\r
+ BUS_NO_MORE_DATA_IN(12) => slv_busy(12),\r
+ BUS_UNKNOWN_ADDR_IN(12) => '0',\r
+ -- ADC1 snooper\r
+ BUS_READ_ENABLE_OUT(13) => slv_read(13),\r
+ BUS_WRITE_ENABLE_OUT(13) => slv_write(13),\r
+ BUS_DATA_OUT(13*32+31 downto 13*32) => slv_data_wr(13*32+31 downto 13*32),\r
+ BUS_DATA_IN(13*32+31 downto 13*32) => slv_data_rd(13*32+31 downto 13*32),\r
+ BUS_ADDR_OUT(13*16+15 downto 13*16) => slv_addr(13*16+15 downto 13*16),\r
+ BUS_TIMEOUT_OUT(13) => open,\r
+ BUS_DATAREADY_IN(13) => slv_ack(13),\r
+ BUS_WRITE_ACK_IN(13) => slv_ack(13),\r
+ BUS_NO_MORE_DATA_IN(13) => slv_busy(13),\r
+ BUS_UNKNOWN_ADDR_IN(13) => '0',\r
+ -- Test register\r
+ BUS_READ_ENABLE_OUT(14) => slv_read(14),\r
+ BUS_WRITE_ENABLE_OUT(14) => slv_write(14),\r
+ BUS_DATA_OUT(14*32+31 downto 14*32) => slv_data_wr(14*32+31 downto 14*32),\r
+ BUS_DATA_IN(14*32+31 downto 14*32) => slv_data_rd(14*32+31 downto 14*32),\r
+ BUS_ADDR_OUT(14*16+15 downto 14*16) => open,\r
+ BUS_TIMEOUT_OUT(14) => open,\r
+ BUS_DATAREADY_IN(14) => slv_ack(14),\r
+ BUS_WRITE_ACK_IN(14) => slv_ack(14),\r
+ BUS_NO_MORE_DATA_IN(14) => slv_busy(14),\r
+ BUS_UNKNOWN_ADDR_IN(14) => '0',\r
+ -- data buffer status registers\r
+ BUS_READ_ENABLE_OUT(15) => slv_read(15),\r
+ BUS_WRITE_ENABLE_OUT(15) => slv_write(15),\r
+ BUS_DATA_OUT(15*32+31 downto 15*32) => slv_data_wr(15*32+31 downto 15*32),\r
+ BUS_DATA_IN(15*32+31 downto 15*32) => slv_data_rd(15*32+31 downto 15*32),\r
+ BUS_ADDR_OUT(15*16+15 downto 15*16) => slv_addr(15*16+15 downto 15*16),\r
+ BUS_TIMEOUT_OUT(15) => open,\r
+ BUS_DATAREADY_IN(15) => slv_ack(15),\r
+ BUS_WRITE_ACK_IN(15) => slv_ack(15),\r
+ BUS_NO_MORE_DATA_IN(15) => slv_busy(15),\r
+ BUS_UNKNOWN_ADDR_IN(15) => '0',\r
+ -- LVL1 release status register\r
+ BUS_READ_ENABLE_OUT(16) => slv_read(16),\r
+ BUS_WRITE_ENABLE_OUT(16) => slv_write(16),\r
+ BUS_DATA_OUT(16*32+31 downto 16*32) => slv_data_wr(16*32+31 downto 16*32),\r
+ BUS_DATA_IN(16*32+31 downto 16*32) => slv_data_rd(16*32+31 downto 16*32),\r
+ BUS_ADDR_OUT(16*16+15 downto 16*16) => slv_addr(16*16+15 downto 16*16),\r
+ BUS_TIMEOUT_OUT(16) => open,\r
+ BUS_DATAREADY_IN(16) => slv_ack(16),\r
+ BUS_WRITE_ACK_IN(16) => slv_ack(16),\r
+ BUS_NO_MORE_DATA_IN(16) => slv_busy(16),\r
+ BUS_UNKNOWN_ADDR_IN(16) => '0',\r
+ -- IPU handler status register\r
+ BUS_READ_ENABLE_OUT(17) => slv_read(17),\r
+ BUS_WRITE_ENABLE_OUT(17) => slv_write(17),\r
+ BUS_DATA_OUT(17*32+31 downto 17*32) => slv_data_wr(17*32+31 downto 17*32),\r
+ BUS_DATA_IN(17*32+31 downto 17*32) => slv_data_rd(17*32+31 downto 17*32),\r
+ BUS_ADDR_OUT(17*16+15 downto 17*16) => slv_addr(17*16+15 downto 17*16),\r
+ BUS_TIMEOUT_OUT(17) => open,\r
+ BUS_DATAREADY_IN(17) => slv_ack(17),\r
+ BUS_WRITE_ACK_IN(17) => slv_ack(17),\r
+ BUS_NO_MORE_DATA_IN(17) => slv_busy(17),\r
+ BUS_UNKNOWN_ADDR_IN(17) => '0',\r
-- debug\r
- STAT_DEBUG => stat\r
- );\r
+ STAT_DEBUG => stat\r
+);\r
\r
\r
------------------------------------------------------------------------------------\r
MEM_15_D_OUT => PED_DATA_15_OUT,\r
-- Status lines\r
STAT => open\r
- );\r
+);\r
slv_busy(0) <= '0';\r
\r
------------------------------------------------------------------------------------\r
);\r
\r
\r
+\r
+\r
-- unusable pins\r
debug(63 downto 43) <= (others => '0');\r
-- connected pins\r
-[pbs1]
+[pbs2]
system = linux
corenum = 2
-env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
-workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
-[pbs2]
+env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/
+
+[pbs1]
system = linux
corenum = 2
-env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
-workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/
+
[pbs3]
system = linux
corenum = 2
-env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
-workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/
+
[pbs4]
system = linux
corenum = 2
-env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
-workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/
+
[pbs5]
system = linux
corenum = 2
-env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
-workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/
+
[pbs6]
system = linux
corenum = 2
-env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
-workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/
+
[pbs7]
system = linux
corenum = 2
-env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
-workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/
+
[pbs8]
system = linux
corenum = 2
-env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
-workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
-[pbs9]
-system = linux
-corenum = 2
-env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
-workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
-[pbs10]
-system = linux
-corenum = 2
-env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
-workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/
+++ /dev/null
-/home/hadaq/license/lattice_license.log: 1:19:02 (lmgrd) lmgrd tcp-port 1702
-/home/hadaq/license/lattice_license.log: 1:19:02 (lmgrd) Started lattice (internet tcp_port 51765 pid 30916)
+++ /dev/null
-/cad/licenses/log/ams_lm.log:15:55:49 (lmgrd) lmgrd tcp-port 26745
-/cad/licenses/log/ams_lm.log:15:55:49 (lmgrd) Started amslmd (internet tcp_port 64814 pid 21110)
-/cad/licenses/log/atr_license.log:9:52:13 (lmgrd) lmgrd tcp-port 27005
-/cad/licenses/log/atr_license.log:9:52:13 (lmgrd) Started atrenta (internet tcp_port 46943 pid 18866)
-/cad/licenses/log/cds_license.log:13:46:39 (lmgrd) lmgrd tcp-port 5280
-/cad/licenses/log/cds_license.log:13:46:39 (lmgrd) Started cdslmd (internet tcp_port 50309 pid 32758)
-/cad/licenses/log/mentor_license.log:14:42:53 (lmgrd) lmgrd tcp-port 1710
-/cad/licenses/log/mentor_license.log:14:42:53 (lmgrd) Started mgcld (internet tcp_port 42914 pid 8237)
-/cad/licenses/log/mg_license.log:13:26:04 (lmgrd) lmgrd tcp-port 1717
-/cad/licenses/log/mg_license.log:13:26:04 (lmgrd) Started mgcld (internet tcp_port 39276 pid 11086)
-/cad/licenses/log/mgcld_lm.log:16:44:20 (lmgrd) lmgrd tcp-port 1710
-/cad/licenses/log/mgcld_lm.log:16:44:20 (lmgrd) Started mgcld (internet tcp_port 64863 pid 24087)
-/cad/licenses/log/syn_license.log:10:29:33 (lmgrd) lmgrd tcp-port 27000
-/cad/licenses/log/syn_license.log:10:29:33 (lmgrd) Started snpslmd (internet tcp_port 54219 pid 24990)
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-package adcmv3_componets is
-
- type debug_array_t is array(integer range <>) of
- std_logic_vector(15 downto 0);
-
- component debug_multiplexer
- generic (
- NUM_PORTS : integer range 1 to 32);
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- DEBUG_LINE_IN : in debug_array_t(0 to NUM_PORTS-1);
- DEBUG_LINE_OUT : out std_logic_vector(15 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic
- );
- end component;
-
-end package;
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.adcmv3_componets.all;
-
-entity debug_multiplexer is
- generic (
- NUM_PORTS : integer range 1 to 32 := 1
- );
- port(
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
-
- DEBUG_LINE_IN : in debug_array_t(0 to NUM_PORTS-1);
- DEBUG_LINE_OUT : out std_logic_vector(15 downto 0);
-
- -- Slave bus
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic
-
- );
-end entity;
-
-architecture Behavioral of debug_multiplexer is
-
- signal port_select : std_logic_vector(7 downto 0);
- signal debug_line_o : std_logic_vector(15 downto 0);
-
- signal slv_data_out_o : std_logic_vector(31 downto 0);
- signal slv_no_more_data_o : std_logic;
- signal slv_unknown_addr_o : std_logic;
- signal slv_ack_o : std_logic;
-
-begin
-
- PROC_MULTIPLEXER: process(port_select,
- DEBUG_LINE_IN)
- begin
- if (unsigned(port_select) < NUM_PORTS) then
- debug_line_o <=
- DEBUG_LINE_IN(to_integer(unsigned(port_select)));
- elsif (unsigned(port_select) = NUM_PORTS) then
- -- Checkerboard
- for I in 0 to 7 loop
- debug_line_o(I * 2) <= CLK_IN;
- debug_line_o(I * 2 + 1) <= not CLK_IN;
- end loop;
- else
- debug_line_o <= (others => '1');
- end if;
- end process PROC_MULTIPLEXER;
-
- PROC_SLAVE_BUS: process(CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- if( RESET_IN = '1' ) then
- slv_data_out_o <= (others => '0');
- slv_no_more_data_o <= '0';
- slv_unknown_addr_o <= '0';
- slv_ack_o <= '0';
- port_select <= (others => '0');
- else
- slv_ack_o <= '1';
- slv_unknown_addr_o <= '0';
- slv_no_more_data_o <= '0';
- slv_data_out_o <= (others => '0');
-
- if (SLV_WRITE_IN = '1') then
- case SLV_ADDR_IN is
- when x"0000" =>
- if (unsigned(SLV_DATA_IN(7 downto 0)) < NUM_PORTS + 1) then
- port_select <= SLV_DATA_IN(7 downto 0);
- end if;
- slv_ack_o <= '1';
-
- when others =>
- slv_unknown_addr_o <= '1';
- slv_ack_o <= '0';
- end case;
-
- elsif (SLV_READ_IN = '1') then
- case SLV_ADDR_IN is
- when x"0000" =>
- slv_data_out_o(7 downto 0) <= port_select;
- slv_data_out_o(31 downto 8) <= (others => '0');
-
- when others =>
- slv_unknown_addr_o <= '1';
- slv_ack_o <= '0';
- end case;
-
- else
- slv_ack_o <= '0';
- end if;
- end if;
- end if;
- end process PROC_SLAVE_BUS;
-
- -----------------------------------------------------------------------------
- -- Output Signals
- -----------------------------------------------------------------------------
-
- SLV_DATA_OUT <= slv_data_out_o;
- SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
- SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
- SLV_ACK_OUT <= slv_ack_o;
-
- DEBUG_LINE_OUT <= debug_line_o;
-
-end Behavioral;
Starting: /usr/local/opt/lattice_diamond/diamond/3.4/synpbase/linux_a_64/mbin/synbatch
Install: /usr/local/opt/lattice_diamond/diamond/3.4/synpbase
Hostname: brett
-Date: Wed Aug 26 17:56:58 2015
+Date: Fri Aug 28 15:32:35 2015
Version: J-2014.09L
Arguments: -product synplify_pro -batch adcmv3.prj
-log file: "/home/rich/TRB/nXyter/trb3/adcm/workdir/adcmv3.srr"
+log file: "/home/rich/TRB/nXyter/ADCM/adcm/workdir/adcmv3.srr"
Running: Compile Input on adcmv3|workdir
-Copied /home/rich/TRB/nXyter/trb3/adcm/workdir/synwork/adcmv3_comp.srs to /home/rich/TRB/nXyter/trb3/adcm/workdir/adcmv3.srs
+Copied /home/rich/TRB/nXyter/ADCM/adcm/workdir/synwork/adcmv3_comp.srs to /home/rich/TRB/nXyter/ADCM/adcm/workdir/adcmv3.srs
compiler Completed
Return Code: 0
-Run Time:00h:00m:20s
+Run Time:00h:00m:19s
Running: Multi-srs Generator on adcmv3|workdir
-Copied /home/rich/TRB/nXyter/trb3/adcm/workdir/synwork/adcmv3_comp.srs to /home/rich/TRB/nXyter/trb3/adcm/workdir/synwork/adcmv3_s.srs
+Copied /home/rich/TRB/nXyter/ADCM/adcm/workdir/synwork/adcmv3_comp.srs to /home/rich/TRB/nXyter/ADCM/adcm/workdir/synwork/adcmv3_s.srs
multi_srs_gen Completed
Return Code: 0
Run Time:00h:00m:02s
-Copied /home/rich/TRB/nXyter/trb3/adcm/workdir/synwork/adcmv3_mult.srs to /home/rich/TRB/nXyter/trb3/adcm/workdir/adcmv3.srs
+Copied /home/rich/TRB/nXyter/ADCM/adcm/workdir/synwork/adcmv3_mult.srs to /home/rich/TRB/nXyter/ADCM/adcm/workdir/adcmv3.srs
Complete: Compile Process on adcmv3|workdir
premap Completed with warnings
Return Code: 1
-Run Time:00h:00m:07s
+Run Time:00h:00m:05s
Complete: Compile on adcmv3|workdir
Running: Map & Optimize on adcmv3|workdir
-Copied /home/rich/TRB/nXyter/trb3/adcm/workdir/synwork/adcmv3_m.srm to /home/rich/TRB/nXyter/trb3/adcm/workdir/adcmv3.srm
+Copied /home/rich/TRB/nXyter/ADCM/adcm/workdir/synwork/adcmv3_m.srm to /home/rich/TRB/nXyter/ADCM/adcm/workdir/adcmv3.srm
fpga_mapper Completed with warnings
Return Code: 1
-Run Time:00h:04m:29s
+Run Time:00h:03m:47s
Complete: Map on adcmv3|workdir
jspc29 / adcm.git / commitdiff