APL_HOLD_TRM: in STD_LOGIC;
APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0) -- see NewTriggerBusNetworkDescr
-
+ APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0) -- My own address (temporary solution!!!)
-- Status and control port
-- not needed now, but later
end component;
-- signals for the test buffer
-signal next_APL_DTYPE_OUT, reg_APL_DTYPE_OUT: std_logic;
-signal next_APL_ERROR_PATTERN_OUT, reg_APL_ERROR_PATTERN_OUT: std_logic;
-signal next_APL_SEQNR_OUT, reg_APL_SEQNR_OUT: std_logic;
+signal next_APL_DTYPE_OUT, reg_APL_DTYPE_OUT: std_logic_vector(3 downto 0);
+signal next_APL_ERROR_PATTERN_OUT, reg_APL_ERROR_PATTERN_OUT: std_logic_vector(31 downto 0);
+signal next_APL_SEQNR_OUT, reg_APL_SEQNR_OUT: std_logic_vector(7 downto 0);
signal next_APL_GOT_TRM, reg_APL_GOT_TRM: std_logic;
signal fifo_term_buffer_data_in : std_logic_vector(50 downto 0);
APL_GOT_TRM <= reg_APL_GOT_TRM;
- FIFO_TERM_BUFFER_CTRL: process (tb_current_state, INT_INIT_DATA_IN,
- INT_INIT_DATAREADY_IN, tb_next_registered_trailer,
+ FIFO_TERM_BUFFER_CTRL: process (tb_current_state, INT_DATA_IN,
+ INT_DATAREADY_IN, tb_next_registered_trailer,
tb_registered_trailer,
fifo_term_buffer_empty, fifo_term_buffer_data_out,
- INT_REPLY_READ_IN, tb_registered_target,
+ INT_READ_IN, tb_registered_target,
reg_APL_DTYPE_OUT, reg_APL_ERROR_PATTERN_OUT,
reg_APL_SEQNR_OUT, reg_APL_GOT_TRM)
begin -- process
- INT_INIT_READ_OUT <= '0';
+ INT_READ_OUT <= '0';
fifo_term_buffer_data_in(TYPE_POSITION) <= TYPE_ILLEGAL;
fifo_term_buffer_data_in(DWORD_POSITION) <= (others => '0');
fifo_term_buffer_write <= '0';
tb_next_registered_trailer <= tb_registered_trailer;
tb_next_registered_target <= tb_registered_target;
fifo_term_buffer_read<= '0';
- INT_REPLY_DATAREADY_OUT <= '0';
- INT_REPLY_DATA_OUT(DWORD_POSITION) <= (others => '0');
- INT_REPLY_DATA_OUT(TYPE_POSITION) <= TYPE_ILLEGAL;
+ INT_DATAREADY_OUT <= '0';
+ INT_DATA_OUT(DWORD_POSITION) <= (others => '0');
+ INT_DATA_OUT(TYPE_POSITION) <= TYPE_ILLEGAL;
next_APL_DTYPE_OUT <= reg_APL_DTYPE_OUT;
next_APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT;
next_APL_SEQNR_OUT <= reg_APL_SEQNR_OUT;
-- IDLE
-----------------------------------------------------------------------
if tb_current_state = IDLE then
- INT_INIT_READ_OUT <= '1'; -- I always can read
+ INT_READ_OUT <= '1'; -- I always can read
tb_next_state <= IDLE;
- if INT_INIT_DATA_IN(TYPE_POSITION) = TYPE_HDR and INT_INIT_DATAREADY_IN = '1' then
+ if INT_DATA_IN(TYPE_POSITION) = TYPE_HDR and INT_DATAREADY_IN = '1' then
-- switch source and target adress
- fifo_term_buffer_data_in(SOURCE_POSITION) <= INT_INIT_DATA_IN(TARGET_POSITION);
- fifo_term_buffer_data_in(TARGET_POSITION) <= INT_INIT_DATA_IN(SOURCE_POSITION);
- fifo_term_buffer_data_in(F3_POSITION) <= INT_INIT_DATA_IN(F3_POSITION);
+ fifo_term_buffer_data_in(SOURCE_POSITION) <= INT_DATA_IN(TARGET_POSITION);
+ fifo_term_buffer_data_in(TARGET_POSITION) <= INT_DATA_IN(SOURCE_POSITION);
+ fifo_term_buffer_data_in(F3_POSITION) <= INT_DATA_IN(F3_POSITION);
fifo_term_buffer_data_in(TYPE_POSITION) <= TYPE_HDR;
- tb_next_registered_target <= INT_INIT_DATA_IN(TARGET_POSITION);
- if fifo_term_buffer_full = '0' and (INT_INIT_DATA_IN(TARGET_POSITION) = APL_MY_ADDRESS_IN
- or INT_INIT_DATA_IN(TARGET_POSITION) = BROADCAST_ADRESS) then
+ tb_next_registered_target <= INT_DATA_IN(TARGET_POSITION);
+ if fifo_term_buffer_full = '0' and (INT_DATA_IN(TARGET_POSITION) = APL_MY_ADDRESS_IN
+ or INT_DATA_IN(TARGET_POSITION) = BROADCAST_ADRESS) then
fifo_term_buffer_write <= '1';
else
fifo_term_buffer_write <= '0';
end if;
- elsif INT_INIT_DATA_IN(TYPE_POSITION) <= TYPE_DAT and INT_INIT_DATAREADY_IN = '1' then
- fifo_term_buffer_data_in <= INT_INIT_DATA_IN;
+ elsif INT_DATA_IN(TYPE_POSITION) <= TYPE_DAT and INT_DATAREADY_IN = '1' then
+ fifo_term_buffer_data_in <= INT_DATA_IN;
if fifo_term_buffer_full = '0' and (tb_registered_target = APL_MY_ADDRESS_IN
or tb_registered_target = BROADCAST_ADRESS) then
fifo_term_buffer_write <= '1';
else
fifo_term_buffer_write <= '0';
end if;
- elsif INT_INIT_DATA_IN(TYPE_POSITION) <= TYPE_TRM and INT_INIT_DATAREADY_IN = '1' then
+ elsif INT_DATA_IN(TYPE_POSITION) <= TYPE_TRM and INT_DATAREADY_IN = '1' then
--tb_next_registered_trailer <= INT_INIT_DATA_IN(DWORD_POSITION);
--keep trailer for later use
-- in addition, write out some debug info
- next_APL_DTYPE_OUT <= INT_INIT_DATA_IN(DTYPE_POSITION);
- next_APL_ERROR_PATTERN_OUT <= INT_INIT_DATA_IN(ERRORPATTERN_POSITION);
- next_APL_SEQNR_OUT <= INT_INIT_DATA_IN(SEQNR_POSITION);
+ next_APL_DTYPE_OUT <= INT_DATA_IN(DTYPE_POSITION);
+ next_APL_ERROR_PATTERN_OUT <= INT_DATA_IN(ERRORPATTERN_POSITION);
+ next_APL_SEQNR_OUT <= INT_DATA_IN(SEQNR_POSITION);
next_APL_GOT_TRM <= '1';
tb_next_state <= RUNNING;
end if;
elsif tb_current_state = RUNNING then
tb_next_state <= RUNNING;
if fifo_term_buffer_empty = '0' then -- Have buffered stuff
- INT_REPLY_DATAREADY_OUT <= '1';
- INT_REPLY_DATA_OUT <= fifo_term_buffer_data_out;
- if (INT_REPLY_READ_IN = '1') then
+ INT_DATAREADY_OUT <= '1';
+ INT_DATA_OUT <= fifo_term_buffer_data_out;
+ if (INT_READ_IN = '1') then
fifo_term_buffer_read <= '1';
end if;
elsif APL_HOLD_TRM = '1' then
-----------------------------------------------------------------------
elsif tb_current_state = SEND_TRAILER then
tb_next_state <= SEND_TRAILER ;
- INT_REPLY_DATAREADY_OUT <= '1';
- INT_REPLY_DATA_OUT(DWORD_POSITION) <= tb_registered_trailer;
- INT_REPLY_DATA_OUT(TYPE_POSITION) <= TYPE_TRM;
- if (INT_REPLY_READ_IN = '1') then
+ INT_DATAREADY_OUT <= '1';
+ INT_DATA_OUT(DWORD_POSITION) <= tb_registered_trailer;
+ INT_DATA_OUT(TYPE_POSITION) <= TYPE_TRM;
+ if (INT_READ_IN = '1') then
tb_next_state <= IDLE;
tb_next_registered_target <= ILLEGAL_ADRESS;
next_APL_GOT_TRM <= '0';
APL_HOLD_TRM: in STD_LOGIC;
APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0) -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
-- Status and control port => just coming from the iobuf for debugging
STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
-- Internal direction port
-- This is just a clone from trb_net_iobuf
- INT_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
INT_DATAREADY_OUT: out STD_LOGIC;
INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
INT_READ_IN: in STD_LOGIC;
INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY,
INT_DATA_IN => buf_to_apl_INIT_DATA,
- INT_READ_OUT => buf_to_apl_INIT_READ,
-
+ INT_READ_OUT => buf_to_apl_INIT_READ
+
-- Status and control port
-- not needed now, but later
);
INT_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY,
INT_DATA_IN => buf_to_apl_REPLY_DATA,
- INT_READ_OUT => buf_to_apl_REPLY_READ,
-
+ INT_READ_OUT => buf_to_apl_REPLY_READ
-- Status and control port
-- not needed now, but later
);