-*~
-*.log
-*.rpt
-netlists
version.vhd
-*.jhd
-*.naf
-*.sort
-*.srp
-*.sym
-*tmpl.vhd
-*.log
-workdir
-workdir_*
-*.bit
-*.kate-swp*
-*.kate-swap*
-.run_manager.ini
-reportview.xml
-.kateproject.d
-cts/project*
-cbmnet/project*
-cbmnet/sim*
-
--- /dev/null
+# Call . /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
+
+TARGET=adcmv3
+FAMILYNAME=LatticeECP3
+DEVICENAME=LFE3-150EA
+PACKAGE=FPBGA672
+SPEEDGRADE=8
+
+TIMESTAMP=$(shell date '+%s')
+VERSION=$(shell cat version-major-minor.txt)
+
+# ------------------------------------------------------------------------------------
+
+.PHONY: all
+all: workdir/$(TARGET).bit
+
+.PHONY: clean
+clean:
+ rm -rf workdir/*
+
+.PHONY: distclean
+distclean:
+ rm -rf workdir/*
+
+.PHONY: checkenv
+checkenv:
+ @echo ""
+ @echo "----------------------------------------------------------------------"
+ @echo "--------------- Check Lattice Environment ---------------"
+ @echo "----------------------------------------------------------------------"
+ @if [ -n "${LM_LICENSE_FILE}" ] ; then \
+ echo "Lattice Environment is: ${LM_LICENSE_FILE}"; \
+ else \
+ echo "------> Lattice Environment is not set"; \
+ exit 1; \
+ fi
+
+# ------------------------------------------------------------------------------------
+
+# Bitgen
+workdir/$(TARGET).bit: workdir/$(TARGET).ncd
+ @echo ""
+ @echo "----------------------------------------------------------------------"
+ @echo "-------------- Bitgen ------------------------------------------------"
+ @echo "----------------------------------------------------------------------"
+ cd workdir && \
+ bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $(TARGET).ncd \
+ $(TARGET).bit $(TARGET).prf
+ @$(MAKE) report
+ @$(MAKE) error
+
+# Place and Route (multipar)
+workdir/$(TARGET).ncd: workdir/$(TARGET)_map.ncd
+ @echo ""
+ @echo "----------------------------------------------------------------------"
+ @echo "-------------- Place and Route (multipar)-----------------------------"
+ @echo "----------------------------------------------------------------------"
+ rm -rf workdir/$(TARGET).ncd workdir/$(TARGET).dir
+ cd workdir && \
+ par -f ../$(TARGET).p2t $(TARGET)_map.ncd $(TARGET).dir $(TARGET).prf
+ cp workdir/$(TARGET).dir/*.ncd workdir/$(TARGET).ncd
+
+# Mapper
+workdir/$(TARGET)_map.ncd: workdir/$(TARGET).ngd $(TARGET).lpf
+ @echo ""
+ @echo "----------------------------------------------------------------------"
+ @echo "-------------- Mapper ------------------------------------------------"
+ @echo "----------------------------------------------------------------------"
+ cd workdir && \
+ map -retime -split_node -a $(FAMILYNAME) -p $(DEVICENAME) \
+ -t $(PACKAGE) -s $(SPEEDGRADE) $(TARGET).ngd -pr $(TARGET).prf \
+ -o $(TARGET)_map.ncd -mp $(TARGET).mrp $(TARGET).lpf
+
+# EDIF 2 NGD
+workdir/$(TARGET).ngd: workdir/$(TARGET).edf
+ @echo ""
+ @echo "----------------------------------------------------------------------"
+ @echo "-------------- EDIF 2 NGD---------------------------------------------"
+ @echo "----------------------------------------------------------------------"
+ cd workdir && \
+ edif2ngd -l $(FAMILYNAME) -d $(DEVICENAME) \$(TARGET).edf $(TARGET).ngo
+ cd workdir && \
+ edfupdate -t $(TARGET).tcy -w $(TARGET).ngo -m $(TARGET).ngo \
+ $(TARGET).ngx
+ cd workdir && \
+ ngdbuild -a $(FAMILYNAME) -d $(DEVICENAME) -dt $(TARGET).ngo \
+ $(TARGET).ngd
+
+# VHDL / Verilog Compiler
+workdir/$(TARGET).edf:
+ @echo ""
+ @echo "----------------------------------------------------------------------"
+ @echo "--------------- Build All --------------------------------------------"
+ @echo "----------------------------------------------------------------------"
+ @$(MAKE) checkenv
+ @$(MAKE) workdir
+ @$(MAKE) version
+
+ @echo ""
+ @echo "----------------------------------------------------------------------"
+ @echo "--------------- VHDL Compiler ----------------------------------------"
+ @echo "----------------------------------------------------------------------"
+ synpwrap -prj $(TARGET).prj || \
+ (grep "@E" workdir/$(TARGET).srr && exit 2)
+
+# ------------------------------------------------------------------------------------
+
+# Version File
+.PHONY: version
+version:
+ @echo ""
+ @echo "----------------------------------------------------------------------"
+ @echo "--------------- Version File -----------------------------------------"
+ @echo "----------------------------------------------------------------------"
+ @echo "-- attention, automatically generated. Don't change by hand." > version.vhd
+ @echo "library ieee;" >> version.vhd
+ @echo "USE IEEE.std_logic_1164.ALL;" >> version.vhd
+ @echo "USE IEEE.std_logic_ARITH.ALL;" >> version.vhd
+ @echo "USE IEEE.std_logic_UNSIGNED.ALL;" >> version.vhd
+ @echo "use ieee.numeric_std.all;" >> version.vhd
+ @echo "" >> version.vhd
+ @echo "package version is" >> version.vhd
+ @echo "" >> version.vhd
+ @echo " constant VERSION_NUMBER_TIME : integer := $(TIMESTAMP);" >> version.vhd
+ @echo -n " constant VERSION_NUMBER : integer := " >> version.vhd
+ @echo "to_integer(x\"$(VERSION)\");" >> version.vhd
+ @echo "" >> version.vhd
+ @echo "end package version;" >> version.vhd
+ @cat version.vhd
+
+# Setup Workdir
+.PHONY: workdir
+workdir:
+ @echo ""
+ @echo "----------------------------------------------------------------------"
+ @echo "-------------- Setup Workdir -----------------------------------------"
+ @echo "----------------------------------------------------------------------"
+ mkdir -p workdir
+ cd workdir && ../../base/linkdesignfiles.sh
+ cp $(TARGET).lpf workdir/$(TARGET).lpf
+# cat $(TARGET)_constraints.lpf >> workdir/$(TARGET).lpf
+ cp nodelist.txt workdir/
+
+# Timing Report
+.PHONY: report
+report:
+ @echo ""
+ @echo "----------------------------------------------------------------------"
+ @echo "-------------- Timing Report -----------------------------------------"
+ @echo "----------------------------------------------------------------------"
+ cd workdir && \
+ iotiming -s $(TARGET).ncd $(TARGET).prf
+ cd workdir && \
+ trce -c -v 15 -o $(TARGET).twr.setup $(TARGET).ncd $(TARGET).prf
+ cd workdir && \
+ trce -hld -c -v 5 -o $(TARGET).twr.hold $(TARGET).ncd $(TARGET).prf
+ cd workdir && \
+ ltxt2ptxt $(TARGET).ncd
+
+# Error Check
+.PHONY: error
+error:
+ @echo ""
+ @echo "----------------------------------------------------------------------"
+ @echo "-------------- Error Check -----------------------------------------"
+ @echo "----------------------------------------------------------------------"
+ @echo -e "\n$(TARGET).mrp:"
+ @grep "Semantic error" ./workdir/$(TARGET).mrp || exit 0
+
+ @echo -e "\n$(TARGET).twr.setup:"
+ @grep 'Error: The following path exceeds requirements by' ./workdir/$(TARGET).twr.setup \
+ || exit 0
+
+ @echo -e "\n$(TARGET).twr.hold:"
+ @grep "Error:" ./workdir/$(TARGET).twr.hold || exit 0
+
+ @echo -e "\nCircuit Loops:"
+ @grep "potential circuit loops" ./workdir/* || exit 0
+
+# ------------------------------------------------------------------------------------
+# Extract dependencies from project file
+#.PHONY: $(TARGET).dep
+#$(TARGET).dep:
+# @echo ""
+# @echo "----------------------------------------------------------------------"
+# @echo "--------------- Extract Dependencies from Project File ---------------"
+# @echo "----------------------------------------------------------------------"
+# grep 'add_file' $(TARGET).prj | grep -v '#' | sed -r 's/^.*"(.*)"$$/\1/' \
+# | xargs echo "workdir/$(TARGET).edf:" > $(TARGET).dep
+# grep 'map_dep' $(TARGET).prj | grep -v '#' | sed -r 's/^.*"(.*)"$$/\1/' \
+# | xargs echo "workdir/$(TARGET)_map.ncd:" >> $(TARGET).dep
+#
+#-include $(TARGET).dep
+
# add_file options
add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
add_file -vhdl -lib work "source/adcmv3_components.vhd"
add_file -vhdl -lib work "source/adcmv3_components2.vhd"
add_file -vhdl -lib work "cores/slv_onewire_dpram.vhd"
# TrbNet design files
-add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd"
-add_file -vhdl -lib work "../trbnet/special/spi_databus_memory.vhd"
-add_file -vhdl -lib work "../trbnet/special/spi_slim.vhd"
-add_file -vhdl -lib work "../trbnet/special/spi_master.vhd"
-add_file -vhdl -lib work "../trbnet/special/handler_lvl1.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_regio_bus_handler.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_sbuf.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_sbuf5.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_sbuf6.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_sbuf.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_priority_encoder.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_priority_arbiter.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_io_multiplexer.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd"
-add_file -vhdl -lib work "../trbnet/basics/ram_16x16_dp.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_pattern_gen.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_regIO.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_api_base.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_obuf.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_obuf_nodata.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_ibuf.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_iobuf.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_ipudata.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_trigger.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd"
-add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd"
-add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
-add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd"
-add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd"
-# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd"
+# add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd"
# add_file -vhdl -lib work "source/sfp_rx_handler.vhd"
# implementation: "workdir"
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Wed Nov 04 16:11:12 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem -memformat orca -e
+ Circuit name : adc_apv_map_mem
+ Module type : rom
+ Module Version : 2.4
+ Address width : 7
+ Ports :
+ Inputs : Address[6:0]
+ Outputs : Q[3:0]
+ I/O buffer : not inserted
+ Memory file : i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem
+ EDIF output : suppressed
+ VHDL output : adc_apv_map_mem.vhd
+ VHDL template : adc_apv_map_mem_tmpl.vhd
+ VHDL testbench : tb_adc_apv_map_mem_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : adc_apv_map_mem.srp
+ Element Usage :
+ ROM128X1 : 4
+ Estimated Resource Usage:
+ LUT : 16
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Wed Nov 04 16:11:12 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem -memformat orca -e \r
+ Circuit name : adc_apv_map_mem\r
+ Module type : rom\r
+ Module Version : 2.4\r
+ Address width : 7\r
+ Data width : 4\r
+ Ports : \r
+ Inputs : Address[6:0]\r
+ Outputs : Q[3:0]\r
+ I/O buffer : not inserted\r
+ Memory file : i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem\r
+ EDIF output : suppressed\r
+ VHDL output : adc_apv_map_mem.vhd\r
+ VHDL template : adc_apv_map_mem_tmpl.vhd\r
+ VHDL testbench : tb_adc_apv_map_mem_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : adc_apv_map_mem.srp\r
+ Estimated Resource Usage:\r
+ LUT : 16\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: ..\src\adc_apv_map_mem.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 2.4
+-- Wed Nov 04 16:11:12 2009
+
+-- parameterized module component declaration
+component adc_apv_map_mem
+ port (Address: in std_logic_vector(6 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : adc_apv_map_mem
+ port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__);
--- /dev/null
+SCUBA, Version ispLever_v72_PROD_Build (44)
+Fri Apr 24 11:41:10 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_ch_in -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type iol -mode in -width 1 -gear 1 -del 16 -e
+ Circuit name : adc_ch_in
+ Module type : iol
+ Module Version : 3.6
+ Ports :
+ Inputs : Del[3:0], ECLK, SCLK, Rst, Data[0:0]
+ Outputs : Q[1:0]
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : adc_ch_in.vhd
+ VHDL template : adc_ch_in_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : adc_ch_in.srp
+ Element Usage :
+ IB : 1
+ IDDRFXA : 1
+ DELAYB : 1
+ Estimated Resource Usage:
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 3.6
+-- Fri Apr 24 11:41:10 2009
+
+-- parameterized module component declaration
+component adc_ch_in
+ port (Del: in std_logic_vector(3 downto 0); ECLK: in std_logic;
+ SCLK: in std_logic; Rst: in std_logic;
+ Data: in std_logic_vector(0 downto 0);
+ Q: out std_logic_vector(1 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : adc_ch_in
+ port map (Del(3 downto 0)=>__, ECLK=>__, SCLK=>__, Rst=>__, Data(0 downto 0)=>__,
+ Q(1 downto 0)=>__);
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Thu Nov 05 10:27:05 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_onewire_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem -memformat orca -e
+ Circuit name : adc_onewire_map_mem
+ Module type : rom
+ Module Version : 2.4
+ Address width : 7
+ Ports :
+ Inputs : Address[6:0]
+ Outputs : Q[3:0]
+ I/O buffer : not inserted
+ Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem
+ EDIF output : suppressed
+ VHDL output : adc_onewire_map_mem.vhd
+ VHDL template : adc_onewire_map_mem_tmpl.vhd
+ VHDL testbench : tb_adc_onewire_map_mem_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : adc_onewire_map_mem.srp
+ Element Usage :
+ ROM128X1 : 4
+ Estimated Resource Usage:
+ LUT : 16
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Thu Nov 05 10:27:05 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_onewire_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem -memformat orca -e \r
+ Circuit name : adc_onewire_map_mem\r
+ Module type : rom\r
+ Module Version : 2.4\r
+ Address width : 7\r
+ Data width : 4\r
+ Ports : \r
+ Inputs : Address[6:0]\r
+ Outputs : Q[3:0]\r
+ I/O buffer : not inserted\r
+ Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem\r
+ EDIF output : suppressed\r
+ VHDL output : adc_onewire_map_mem.vhd\r
+ VHDL template : adc_onewire_map_mem_tmpl.vhd\r
+ VHDL testbench : tb_adc_onewire_map_mem_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : adc_onewire_map_mem.srp\r
+ Estimated Resource Usage:\r
+ LUT : 16\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: adc_onewire_map_mem.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 2.4
+-- Thu Nov 05 10:27:05 2009
+
+-- parameterized module component declaration
+component adc_onewire_map_mem
+ port (Address: in std_logic_vector(6 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : adc_onewire_map_mem
+ port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__);
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 4.2
+-- Thu Apr 16 11:20:59 2009
+
+-- parameterized module component declaration
+component adc_pll
+ port (CLK: in std_logic; RESET: in std_logic; CLKOP: out std_logic;
+ LOCK: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : adc_pll
+ port map (CLK=>__, RESET=>__, CLKOP=>__, LOCK=>__);
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Tue Oct 13 16:03:30 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_snoop_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 10 -rwidth 16 -waddr_width 10 -wwidth 16 -rnum_words 1024 -wnum_words 1024 -outdata REGISTERED -resetmode SYNC -cascade -1 -e
+ Circuit name : adc_snoop_mem
+ Module type : RAM_DP
+ Module Version : 6.1
+ Ports :
+ Inputs : WrAddress[9:0], RdAddress[9:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
+ Outputs : Q[15:0]
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : adc_snoop_mem.vhd
+ VHDL template : adc_snoop_mem_tmpl.vhd
+ VHDL testbench : tb_adc_snoop_mem_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : adc_snoop_mem.srp
+ Element Usage :
+ DP16KB : 1
+ Estimated Resource Usage:
+ EBR : 1
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Tue Oct 13 16:03:30 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_snoop_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 10 -rwidth 16 -waddr_width 10 -wwidth 16 -rnum_words 1024 -wnum_words 1024 -outdata REGISTERED -resetmode SYNC -cascade -1 -e \r
+ Circuit name : adc_snoop_mem\r
+ Module type : RAM_DP\r
+ Module Version : 6.1\r
+ Ports : \r
+ Inputs : WrAddress[9:0], RdAddress[9:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn\r
+ Outputs : Q[15:0]\r
+ I/O buffer : not inserted\r
+ EDIF output : suppressed\r
+ VHDL output : adc_snoop_mem.vhd\r
+ VHDL template : adc_snoop_mem_tmpl.vhd\r
+ VHDL testbench : tb_adc_snoop_mem_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : adc_snoop_mem.srp\r
+ Estimated Resource Usage:\r
+ EBR : 1\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: adc_snoop_mem.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 6.1
+-- Tue Oct 13 16:03:30 2009
+
+-- parameterized module component declaration
+component adc_snoop_mem
+ port (WrAddress: in std_logic_vector(9 downto 0);
+ RdAddress: in std_logic_vector(9 downto 0);
+ Data: in std_logic_vector(15 downto 0); WE: in std_logic;
+ RdClock: in std_logic; RdClockEn: in std_logic;
+ Reset: in std_logic; WrClock: in std_logic;
+ WrClockEn: in std_logic; Q: out std_logic_vector(15 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : adc_snoop_mem
+ port map (WrAddress(9 downto 0)=>__, RdAddress(9 downto 0)=>__, Data(15 downto 0)=>__,
+ WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__, WrClock=>__,
+ WrClockEn=>__, Q(15 downto 0)=>__);
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Wed Nov 04 16:10:56 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_adc_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem -memformat orca -e
+ Circuit name : apv_adc_map_mem
+ Module type : rom
+ Module Version : 2.4
+ Address width : 7
+ Ports :
+ Inputs : Address[6:0]
+ Outputs : Q[3:0]
+ I/O buffer : not inserted
+ Memory file : i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem
+ EDIF output : suppressed
+ VHDL output : apv_adc_map_mem.vhd
+ VHDL template : apv_adc_map_mem_tmpl.vhd
+ VHDL testbench : tb_apv_adc_map_mem_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : apv_adc_map_mem.srp
+ Element Usage :
+ ROM128X1 : 4
+ Estimated Resource Usage:
+ LUT : 16
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Wed Nov 04 16:10:56 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_adc_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem -memformat orca -e \r
+ Circuit name : apv_adc_map_mem\r
+ Module type : rom\r
+ Module Version : 2.4\r
+ Address width : 7\r
+ Data width : 4\r
+ Ports : \r
+ Inputs : Address[6:0]\r
+ Outputs : Q[3:0]\r
+ I/O buffer : not inserted\r
+ Memory file : i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem\r
+ EDIF output : suppressed\r
+ VHDL output : apv_adc_map_mem.vhd\r
+ VHDL template : apv_adc_map_mem_tmpl.vhd\r
+ VHDL testbench : tb_apv_adc_map_mem_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : apv_adc_map_mem.srp\r
+ Estimated Resource Usage:\r
+ LUT : 16\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: ..\src\apv_adc_map_mem.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 2.4
+-- Wed Nov 04 16:10:56 2009
+
+-- parameterized module component declaration
+component apv_adc_map_mem
+ port (Address: in std_logic_vector(6 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : apv_adc_map_mem
+ port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__);
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Wed Oct 14 17:47:59 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv2/src/apv_mapping.mem -memformat orca -e
+ Circuit name : apv_map_mem
+ Module type : rom
+ Module Version : 2.4
+ Address width : 7
+ Ports :
+ Inputs : Address[6:0]
+ Outputs : Q[3:0]
+ I/O buffer : not inserted
+ Memory file : i:/vhdl_pro/adcmv2/src/apv_mapping.mem
+ EDIF output : suppressed
+ VHDL output : apv_map_mem.vhd
+ VHDL template : apv_map_mem_tmpl.vhd
+ VHDL testbench : tb_apv_map_mem_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : apv_map_mem.srp
+ Element Usage :
+ ROM128X1 : 4
+ Estimated Resource Usage:
+ LUT : 16
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Wed Oct 14 17:47:59 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv2/src/apv_mapping.mem -memformat orca -e \r
+ Circuit name : apv_map_mem\r
+ Module type : rom\r
+ Module Version : 2.4\r
+ Address width : 7\r
+ Data width : 4\r
+ Ports : \r
+ Inputs : Address[6:0]\r
+ Outputs : Q[3:0]\r
+ I/O buffer : not inserted\r
+ Memory file : i:/vhdl_pro/adcmv2/src/apv_mapping.mem\r
+ EDIF output : suppressed\r
+ VHDL output : apv_map_mem.vhd\r
+ VHDL template : apv_map_mem_tmpl.vhd\r
+ VHDL testbench : tb_apv_map_mem_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : apv_map_mem.srp\r
+ Estimated Resource Usage:\r
+ LUT : 16\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: ..\src\apv_map_mem.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 2.4
+-- Wed Oct 14 17:47:59 2009
+
+-- parameterized module component declaration
+component apv_map_mem
+ port (Address: in std_logic_vector(6 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : apv_map_mem
+ port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__);
--- /dev/null
+SCUBA, Version ispLever_v72_PROD_Build (44)
+Fri Nov 20 11:16:48 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n crossover -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -pfu_fifo -addr_width 4 -data_width 96 -num_words 16 -rdata_width 96 -no_enable -pe -1 -pf -1 -rfill -fill -e
+ Circuit name : crossover
+ Module type : ebfifo
+ Module Version : 5.0
+ Ports :
+ Inputs : Data[95:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
+ Outputs : Q[95:0], WCNT[4:0], RCNT[4:0], Empty, Full
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : crossover.vhd
+ VHDL template : crossover_tmpl.vhd
+ VHDL testbench : tb_crossover_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : crossover.srp
+ Element Usage :
+ AGEB2 : 6
+ AND2 : 2
+ CU2 : 6
+ FADD2B : 8
+ FSUB2B : 6
+ FD1P3BX : 2
+ FD1P3DX : 124
+ FD1S3BX : 1
+ FD1S3DX : 31
+ INV : 2
+ OR2 : 1
+ ROM16X1 : 13
+ DPR16X4A : 24
+ XOR2 : 10
+ Estimated Resource Usage:
+ LUT : 78
+ DRAM : 24
+ Reg : 158
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_PROD_Build (44)\r
+Fri Nov 20 11:16:48 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n crossover -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -pfu_fifo -addr_width 4 -data_width 96 -num_words 16 -rdata_width 96 -no_enable -pe -1 -pf -1 -rfill -fill -e \r
+ Circuit name : crossover\r
+ Module type : ebfifo\r
+ Module Version : 5.0\r
+ Ports : \r
+ Inputs : Data[95:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset\r
+ Outputs : Q[95:0], WCNT[4:0], RCNT[4:0], Empty, Full\r
+ I/O buffer : not inserted\r
+ EDIF output : suppressed\r
+ VHDL output : crossover.vhd\r
+ VHDL template : crossover_tmpl.vhd\r
+ VHDL testbench : tb_crossover_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : crossover.srp\r
+ Estimated Resource Usage:\r
+ LUT : 78\r
+ DRAM : 24\r
+ Reg : 158\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: ..\src\crossover.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44)
+-- Module Version: 5.0
+-- Fri Nov 20 11:16:48 2009
+
+-- parameterized module component declaration
+component crossover
+ port (Data: in std_logic_vector(95 downto 0);
+ WrClock: in std_logic; RdClock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ RPReset: in std_logic; Q: out std_logic_vector(95 downto 0);
+ WCNT: out std_logic_vector(4 downto 0);
+ RCNT: out std_logic_vector(4 downto 0); Empty: out std_logic;
+ Full: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : crossover
+ port map (Data(95 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
+ RdEn=>__, Reset=>__, RPReset=>__, Q(95 downto 0)=>__, WCNT(4 downto 0)=>__,
+ RCNT(4 downto 0)=>__, Empty=>__, Full=>__);
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 2.4
+-- Tue Mar 03 09:38:59 2009
+
+-- parameterized module component declaration
+component decoder_8bit
+ port (Address: in std_logic_vector(7 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : decoder_8bit
+ port map (Address(7 downto 0)=>__, Q(3 downto 0)=>__);
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44)
+-- Module Version: 3.2
+-- Thu Jan 29 18:49:16 2009
+
+-- parameterized module component declaration
+component dll_100m
+ port (clk: in std_logic; resetn: in std_logic;
+ aluhold: in std_logic; clkop: out std_logic;
+ clkos: out std_logic; lock: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : dll_100m
+ port map (clk=>__, resetn=>__, aluhold=>__, clkop=>__, clkos=>__,
+ lock=>__);
--- /dev/null
+SCUBA, Version ispLever_v72_PROD_Build (44)
+Fri Nov 20 19:14:28 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n dpram_8x19 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 19 -waddr_width 4 -wwidth 19 -rnum_words 16 -wnum_words 16 -outData UNREGISTERED -e
+ Circuit name : dpram_8x19
+ Module type : sdpram
+ Module Version : 3.4
+ Address width : 4
+ Ports :
+ Inputs : WrAddress[3:0], Data[18:0], WrClock, WE, WrClockEn, RdAddress[3:0]
+ Outputs : Q[18:0]
+ I/O buffer : not inserted
+ Clock edge : rising edge
+ EDIF output : suppressed
+ VHDL output : dpram_8x19.vhd
+ VHDL template : dpram_8x19_tmpl.vhd
+ VHDL testbench : tb_dpram_8x19_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : dpram_8x19.srp
+ Element Usage :
+ ROM16X1 : 1
+ DPR16X4A : 5
+ Estimated Resource Usage:
+ LUT : 1
+ DRAM : 5
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_PROD_Build (44)\r
+Fri Nov 20 19:14:28 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n dpram_8x19 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 19 -waddr_width 4 -wwidth 19 -rnum_words 16 -wnum_words 16 -outData UNREGISTERED -e \r
+ Circuit name : dpram_8x19\r
+ Module type : sdpram\r
+ Module Version : 3.4\r
+ Address width : 4\r
+ Data width : 19\r
+ Ports : \r
+ Inputs : WrAddress[3:0], Data[18:0], WrClock, WE, WrClockEn, RdAddress[3:0]\r
+ Outputs : Q[18:0]\r
+ I/O buffer : not inserted\r
+ Clock edge : rising edge\r
+ EDIF output : suppressed\r
+ VHDL output : dpram_8x19.vhd\r
+ VHDL template : dpram_8x19_tmpl.vhd\r
+ VHDL testbench : tb_dpram_8x19_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : dpram_8x19.srp\r
+ Estimated Resource Usage:\r
+ LUT : 1\r
+ DRAM : 5\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: ..\src\dpram_8x19.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44)
+-- Module Version: 3.4
+-- Fri Nov 20 19:14:28 2009
+
+-- parameterized module component declaration
+component dpram_8x19
+ port (WrAddress: in std_logic_vector(3 downto 0);
+ Data: in std_logic_vector(18 downto 0); WrClock: in std_logic;
+ WE: in std_logic; WrClockEn: in std_logic;
+ RdAddress: in std_logic_vector(3 downto 0);
+ Q: out std_logic_vector(18 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : dpram_8x19
+ port map (WrAddress(3 downto 0)=>__, Data(18 downto 0)=>__, WrClock=>__,
+ WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, Q(18 downto 0)=>__);
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v71_PROD_Build (58)
+-- Module Version: 3.3
+-- Fri Aug 29 14:24:36 2008
+
+-- parameterized module component declaration
+component eds_buffer_dpram
+ port (WrAddress: in std_logic_vector(3 downto 0);
+ Data: in std_logic_vector(39 downto 0); WrClock: in std_logic;
+ WE: in std_logic; WrClockEn: in std_logic;
+ RdAddress: in std_logic_vector(3 downto 0);
+ RdClock: in std_logic; RdClockEn: in std_logic;
+ Reset: in std_logic; Q: out std_logic_vector(39 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : eds_buffer_dpram
+ port map (WrAddress(3 downto 0)=>__, Data(39 downto 0)=>__, WrClock=>__,
+ WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, RdClock=>__,
+ RdClockEn=>__, Reset=>__, Q(39 downto 0)=>__);
--- /dev/null
+SCUBA, Version ispLever_v8.0_PROD_Build (41)
+Thu Mar 11 10:33:40 2010
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_16x11 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifoblk -pfu_fifo -addr_width 4 -data_width 11 -num_words 16 -no_enable -pe -1 -pf -1 -fill -e
+ Circuit name : fifo_16x11
+ Module type : fifoblk
+ Module Version : 4.7
+ Ports :
+ Inputs : Data[10:0], Clock, WrEn, RdEn, Reset
+ Outputs : Q[10:0], WCNT[4:0], Empty, Full
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : fifo_16x11.vhd
+ VHDL template : fifo_16x11_tmpl.vhd
+ VHDL testbench : tb_fifo_16x11_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : fifo_16x11.srp
+ Element Usage :
+ AGEB2 : 3
+ ALEB2 : 3
+ AND2 : 3
+ CU2 : 6
+ CB2 : 3
+ FADD2B : 7
+ FD1P3DX : 26
+ FD1S3BX : 1
+ FD1S3DX : 1
+ INV : 4
+ ROM16X1 : 3
+ DPR16X4A : 3
+ XOR2 : 1
+ Estimated Resource Usage:
+ LUT : 51
+ DRAM : 3
+ Reg : 28
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v8.0_PROD_Build (41)\r
+Thu Mar 11 10:33:40 2010\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_16x11 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifoblk -pfu_fifo -addr_width 4 -data_width 11 -num_words 16 -no_enable -pe -1 -pf -1 -fill -e \r
+ Circuit name : fifo_16x11\r
+ Module type : fifoblk\r
+ Module Version : 4.7\r
+ Ports : \r
+ Inputs : Data[10:0], Clock, WrEn, RdEn, Reset\r
+ Outputs : Q[10:0], WCNT[4:0], Empty, Full\r
+ I/O buffer : not inserted\r
+ EDIF output : suppressed\r
+ VHDL output : fifo_16x11.vhd\r
+ VHDL template : fifo_16x11_tmpl.vhd\r
+ VHDL testbench : tb_fifo_16x11_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : fifo_16x11.srp\r
+ Estimated Resource Usage:\r
+ LUT : 51\r
+ DRAM : 3\r
+ Reg : 28\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: ..\src\fifo_16x11.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 4.7
+-- Thu Mar 11 10:33:40 2010
+
+-- parameterized module component declaration
+component fifo_16x11
+ port (Data: in std_logic_vector(10 downto 0); Clock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ Q: out std_logic_vector(10 downto 0);
+ WCNT: out std_logic_vector(4 downto 0); Empty: out std_logic;
+ Full: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : fifo_16x11
+ port map (Data(10 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__,
+ Reset=>__, Q(10 downto 0)=>__, WCNT(4 downto 0)=>__, Empty=>__,
+ Full=>__);
--- /dev/null
+SCUBA, Version ispLever_v8.0_PROD_Build (41)
+Thu Apr 29 14:49:48 2010
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_1kx18 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifoblk -addr_width 10 -data_width 18 -num_words 1024 -no_enable -pe -1 -pf 1020 -fill -e
+ Circuit name : fifo_1kx18
+ Module type : fifoblk
+ Module Version : 4.8
+ Ports :
+ Inputs : Data[17:0], Clock, WrEn, RdEn, Reset
+ Outputs : Q[17:0], WCNT[10:0], Empty, Full, AlmostFull
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : fifo_1kx18.vhd
+ VHDL template : fifo_1kx18_tmpl.vhd
+ VHDL testbench : tb_fifo_1kx18_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : fifo_1kx18.srp
+ Element Usage :
+ AGEB2 : 12
+ ALEB2 : 6
+ AND2 : 4
+ CU2 : 12
+ CB2 : 6
+ FADD2B : 9
+ FD1P3DX : 33
+ FD1S3BX : 1
+ FD1S3DX : 2
+ INV : 9
+ ROM16X1 : 2
+ XOR2 : 1
+ DP16KB : 1
+ Estimated Resource Usage:
+ LUT : 97
+ EBR : 1
+ Reg : 36
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v8.0_PROD_Build (41)\r
+Thu Apr 29 14:49:48 2010\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_1kx18 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifoblk -addr_width 10 -data_width 18 -num_words 1024 -no_enable -pe -1 -pf 1020 -fill -e \r
+ Circuit name : fifo_1kx18\r
+ Module type : fifoblk\r
+ Module Version : 4.8\r
+ Ports : \r
+ Inputs : Data[17:0], Clock, WrEn, RdEn, Reset\r
+ Outputs : Q[17:0], WCNT[10:0], Empty, Full, AlmostFull\r
+ I/O buffer : not inserted\r
+ EDIF output : suppressed\r
+ VHDL output : fifo_1kx18.vhd\r
+ VHDL template : fifo_1kx18_tmpl.vhd\r
+ VHDL testbench : tb_fifo_1kx18_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : fifo_1kx18.srp\r
+ Estimated Resource Usage:\r
+ LUT : 97\r
+ EBR : 1\r
+ Reg : 36\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: ..\src\fifo_1kx18.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 4.8
+-- Thu Apr 29 14:49:48 2010
+
+-- parameterized module component declaration
+component fifo_1kx18
+ port (Data: in std_logic_vector(17 downto 0); Clock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ Q: out std_logic_vector(17 downto 0);
+ WCNT: out std_logic_vector(10 downto 0); Empty: out std_logic;
+ Full: out std_logic; AlmostFull: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : fifo_1kx18
+ port map (Data(17 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__,
+ Reset=>__, Q(17 downto 0)=>__, WCNT(10 downto 0)=>__, Empty=>__,
+ Full=>__, AlmostFull=>__);
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 4.5
+-- Fri Feb 27 12:01:58 2009
+
+-- parameterized module component declaration
+component fifo_2kx27
+ port (Data: in std_logic_vector(26 downto 0); Clock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ Q: out std_logic_vector(26 downto 0);
+ WCNT: out std_logic_vector(11 downto 0); Empty: out std_logic;
+ Full: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : fifo_2kx27
+ port map (Data(26 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__,
+ Reset=>__, Q(26 downto 0)=>__, WCNT(11 downto 0)=>__, Empty=>__,
+ Full=>__);
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Mon Sep 14 13:08:21 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n frame_status_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 12 -waddr_width 4 -wwidth 12 -rnum_words 16 -wnum_words 16 -outData REGISTERED -e
+ Circuit name : frame_status_mem
+ Module type : sdpram
+ Module Version : 3.5
+ Address width : 4
+ Ports :
+ Inputs : WrAddress[3:0], Data[11:0], WrClock, WE, WrClockEn, RdAddress[3:0], RdClock, RdClockEn, Reset
+ Outputs : Q[11:0]
+ I/O buffer : not inserted
+ Clock edge : rising edge
+ EDIF output : suppressed
+ VHDL output : frame_status_mem.vhd
+ VHDL template : frame_status_mem_tmpl.vhd
+ VHDL testbench : tb_frame_status_mem_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : frame_status_mem.srp
+ Element Usage :
+ FD1P3DX : 12
+ ROM16X1 : 1
+ DPR16X4A : 3
+ Estimated Resource Usage:
+ LUT : 1
+ DRAM : 3
+ Reg : 12
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Mon Sep 14 13:08:21 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n frame_status_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 12 -waddr_width 4 -wwidth 12 -rnum_words 16 -wnum_words 16 -outData REGISTERED -e \r
+ Circuit name : frame_status_mem\r
+ Module type : sdpram\r
+ Module Version : 3.5\r
+ Address width : 4\r
+ Data width : 12\r
+ Ports : \r
+ Inputs : WrAddress[3:0], Data[11:0], WrClock, WE, WrClockEn, RdAddress[3:0], RdClock, RdClockEn, Reset\r
+ Outputs : Q[11:0]\r
+ I/O buffer : not inserted\r
+ Clock edge : rising edge\r
+ EDIF output : suppressed\r
+ VHDL output : frame_status_mem.vhd\r
+ VHDL template : frame_status_mem_tmpl.vhd\r
+ VHDL testbench : tb_frame_status_mem_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : frame_status_mem.srp\r
+ Estimated Resource Usage:\r
+ LUT : 1\r
+ DRAM : 3\r
+ Reg : 12\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: frame_status_mem.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 3.5
+-- Mon Sep 14 13:08:21 2009
+
+-- parameterized module component declaration
+component frame_status_mem
+ port (WrAddress: in std_logic_vector(3 downto 0);
+ Data: in std_logic_vector(11 downto 0); WrClock: in std_logic;
+ WE: in std_logic; WrClockEn: in std_logic;
+ RdAddress: in std_logic_vector(3 downto 0);
+ RdClock: in std_logic; RdClockEn: in std_logic;
+ Reset: in std_logic; Q: out std_logic_vector(11 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : frame_status_mem
+ port map (WrAddress(3 downto 0)=>__, Data(11 downto 0)=>__, WrClock=>__,
+ WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, RdClock=>__,
+ RdClockEn=>__, Reset=>__, Q(11 downto 0)=>__);
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Mon Sep 14 12:58:01 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n input_bram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 11 -rwidth 18 -waddr_width 11 -wwidth 18 -rnum_words 2048 -wnum_words 2048 -outdata REGISTERED -resetmode SYNC -cascade -1 -e
+ Circuit name : input_bram
+ Module type : RAM_DP
+ Module Version : 6.1
+ Ports :
+ Inputs : WrAddress[10:0], RdAddress[10:0], Data[17:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
+ Outputs : Q[17:0]
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : input_bram.vhd
+ VHDL template : input_bram_tmpl.vhd
+ VHDL testbench : tb_input_bram_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : input_bram.srp
+ Element Usage :
+ DP16KB : 2
+ Estimated Resource Usage:
+ EBR : 2
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Mon Sep 14 12:58:01 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n input_bram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 11 -rwidth 18 -waddr_width 11 -wwidth 18 -rnum_words 2048 -wnum_words 2048 -outdata REGISTERED -resetmode SYNC -cascade -1 -e \r
+ Circuit name : input_bram\r
+ Module type : RAM_DP\r
+ Module Version : 6.1\r
+ Ports : \r
+ Inputs : WrAddress[10:0], RdAddress[10:0], Data[17:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn\r
+ Outputs : Q[17:0]\r
+ I/O buffer : not inserted\r
+ EDIF output : suppressed\r
+ VHDL output : input_bram.vhd\r
+ VHDL template : input_bram_tmpl.vhd\r
+ VHDL testbench : tb_input_bram_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : input_bram.srp\r
+ Estimated Resource Usage:\r
+ EBR : 2\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: ..\src\input_bram.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 6.1
+-- Mon Sep 14 12:58:01 2009
+
+-- parameterized module component declaration
+component input_bram
+ port (WrAddress: in std_logic_vector(10 downto 0);
+ RdAddress: in std_logic_vector(10 downto 0);
+ Data: in std_logic_vector(17 downto 0); WE: in std_logic;
+ RdClock: in std_logic; RdClockEn: in std_logic;
+ Reset: in std_logic; WrClock: in std_logic;
+ WrClockEn: in std_logic; Q: out std_logic_vector(17 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : input_bram
+ port map (WrAddress(10 downto 0)=>__, RdAddress(10 downto 0)=>__,
+ Data(17 downto 0)=>__, WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__,
+ WrClock=>__, WrClockEn=>__, Q(17 downto 0)=>__);
--- /dev/null
+SCUBA, Version ispLever_v8.0_PROD_Build (41)\r
+Thu May 20 14:41:10 2010\r
+ \r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.\r
+ \r
+BEGIN SCUBA Module Synthesis\r
+ \r
+ Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n test_fifo2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifoblk -addr_width 10 -data_width 18 -num_words 1024 -no_enable -pe -1 -pf -1 -e \r
+ Circuit name : test_fifo2\r
+ Module type : fifoblk\r
+ Module Version : 4.8\r
+ Ports : \r
+ Inputs : Data[17:0], Clock, WrEn, RdEn, Reset\r
+ Outputs : Q[17:0], Empty, Full\r
+ I/O buffer : not inserted\r
+ EDIF output : suppressed\r
+ VHDL output : test_fifo2.vhd\r
+ VHDL template : test_fifo2_tmpl.vhd\r
+ VHDL testbench : tb_test_fifo2_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : test_fifo2.srp\r
+ Estimated Resource Usage:\r
+ LUT : 80\r
+ EBR : 1\r
+ Reg : 35\r
+ \r
+END SCUBA Module Synthesis\r
+\r
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Thu Oct 29 11:23:03 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n mult_3x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type dspmult -simple_portname -pfu_mult -widtha 3 -widthb 8 -widthp 11 -PL_stages 0 -output_reg -clk0 -ce0 -rst0 -e
+ Circuit name : mult_3x8
+ Module type : dspmult_a
+ Module Version : 4.3
+ Ports :
+ Inputs : Clock, ClkEn, Aclr, DataA[2:0], DataB[7:0]
+ Outputs : Result[10:0]
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : mult_3x8.vhd
+ VHDL template : mult_3x8_tmpl.vhd
+ VHDL testbench : tb_mult_3x8_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : mult_3x8.srp
+ Element Usage :
+ AND2 : 9
+ FADD2B : 6
+ FD1P3DX : 11
+ MULT2 : 4
+ Estimated Resource Usage:
+ LUT : 29
+ Reg : 11
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Thu Oct 29 11:23:03 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n mult_3x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type dspmult -simple_portname -pfu_mult -widtha 3 -widthb 8 -widthp 11 -PL_stages 0 -output_reg -clk0 -ce0 -rst0 -e \r
+ Circuit name : mult_3x8\r
+ Module type : dspmult_a\r
+ Module Version : 4.3\r
+ Ports : \r
+ Inputs : Clock, ClkEn, Aclr, DataA[2:0], DataB[7:0]\r
+ Outputs : Result[10:0]\r
+ I/O buffer : not inserted\r
+ EDIF output : suppressed\r
+ VHDL output : mult_3x8.vhd\r
+ VHDL template : mult_3x8_tmpl.vhd\r
+ VHDL testbench : tb_mult_3x8_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : mult_3x8.srp\r
+ Estimated Resource Usage:\r
+ LUT : 29\r
+ Reg : 11\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: ..\src\mult_3x8.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 4.3
+-- Thu Oct 29 11:23:03 2009
+
+-- parameterized module component declaration
+component mult_3x8
+ port (Clock: in std_logic; ClkEn: in std_logic;
+ Aclr: in std_logic; DataA: in std_logic_vector(2 downto 0);
+ DataB: in std_logic_vector(7 downto 0);
+ Result: out std_logic_vector(10 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : mult_3x8
+ port map (Clock=>__, ClkEn=>__, Aclr=>__, DataA(2 downto 0)=>__,
+ DataB(7 downto 0)=>__, Result(10 downto 0)=>__);
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Thu Nov 05 15:51:35 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n onewire_spare_one -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 3 -num_words 8 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem -memformat orca -e
+ Circuit name : onewire_spare_one
+ Module type : rom
+ Module Version : 2.4
+ Address width : 3
+ Ports :
+ Inputs : Address[2:0]
+ Outputs : Q[3:0]
+ I/O buffer : not inserted
+ Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem
+ EDIF output : suppressed
+ VHDL output : onewire_spare_one.vhd
+ VHDL template : onewire_spare_one_tmpl.vhd
+ VHDL testbench : tb_onewire_spare_one_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : onewire_spare_one.srp
+ Element Usage :
+ ROM16X1 : 4
+ Estimated Resource Usage:
+ LUT : 4
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Thu Nov 05 15:51:35 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n onewire_spare_one -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 3 -num_words 8 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem -memformat orca -e \r
+ Circuit name : onewire_spare_one\r
+ Module type : rom\r
+ Module Version : 2.4\r
+ Address width : 3\r
+ Data width : 4\r
+ Ports : \r
+ Inputs : Address[2:0]\r
+ Outputs : Q[3:0]\r
+ I/O buffer : not inserted\r
+ Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem\r
+ EDIF output : suppressed\r
+ VHDL output : onewire_spare_one.vhd\r
+ VHDL template : onewire_spare_one_tmpl.vhd\r
+ VHDL testbench : tb_onewire_spare_one_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : onewire_spare_one.srp\r
+ Estimated Resource Usage:\r
+ LUT : 4\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: onewire_spare_one.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 2.4
+-- Thu Nov 05 15:51:35 2009
+
+-- parameterized module component declaration
+component onewire_spare_one
+ port (Address: in std_logic_vector(2 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : onewire_spare_one
+ port map (Address(2 downto 0)=>__, Q(3 downto 0)=>__);
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Mon Sep 14 12:54:09 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n ped_thr_true -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ramdp -device LFE2M100E -aaddr_width 7 -widtha 18 -baddr_width 7 -widthb 18 -anum_words 128 -bnum_words 128 -outdataA REGISTERED -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -cascade -1 -e
+ Circuit name : ped_thr_true
+ Module type : RAM_DP_TRUE
+ Module Version : 7.1
+ Ports :
+ Inputs : DataInA[17:0], DataInB[17:0], AddressA[6:0], AddressB[6:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
+ Outputs : QA[17:0], QB[17:0]
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : ped_thr_true.vhd
+ VHDL template : ped_thr_true_tmpl.vhd
+ VHDL testbench : tb_ped_thr_true_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : ped_thr_true.srp
+ Element Usage :
+ DP16KB : 1
+ Estimated Resource Usage:
+ EBR : 1
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 7.1
+-- Mon Sep 14 12:54:09 2009
+
+-- parameterized module component declaration
+component ped_thr_true
+ port (DataInA: in std_logic_vector(17 downto 0);
+ DataInB: in std_logic_vector(17 downto 0);
+ AddressA: in std_logic_vector(6 downto 0);
+ AddressB: in std_logic_vector(6 downto 0);
+ ClockA: in std_logic; ClockB: in std_logic;
+ ClockEnA: in std_logic; ClockEnB: in std_logic;
+ WrA: in std_logic; WrB: in std_logic; ResetA: in std_logic;
+ ResetB: in std_logic; QA: out std_logic_vector(17 downto 0);
+ QB: out std_logic_vector(17 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : ped_thr_true
+ port map (DataInA(17 downto 0)=>__, DataInB(17 downto 0)=>__,
+ AddressA(6 downto 0)=>__, AddressB(6 downto 0)=>__, ClockA=>__,
+ ClockB=>__, ClockEnA=>__, ClockEnB=>__, WrA=>__, WrB=>__, ResetA=>__,
+ ResetB=>__, QA(17 downto 0)=>__, QB(17 downto 0)=>__);
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44)
+-- Module Version: 4.2
+-- Fri Jan 30 10:01:31 2009
+
+-- parameterized module component declaration
+component pll_40m
+ port (CLK: in std_logic; RESET: in std_logic; DPAMODE: in std_logic;
+ DPHASE0: in std_logic; DPHASE1: in std_logic; DPHASE2: in std_logic;
+ DPHASE3: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic;
+ LOCK: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : pll_40m
+ port map (CLK=>__, RESET=>__, DPAMODE=>__, DPHASE0=>__, DPHASE1=>__,
+ DPHASE2=>__, DPHASE3=>__, CLKOP=>__, CLKOS=>__, LOCK=>__);
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Tue Aug 11 14:48:40 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n slv_onewire_dpram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 6 -rwidth 32 -waddr_width 7 -wwidth 16 -rnum_words 64 -wnum_words 128 -resetmode SYNC -cascade -1 -e
+ Circuit name : slv_onewire_dpram
+ Module type : RAM_DP
+ Module Version : 6.1
+ Ports :
+ Inputs : WrAddress[6:0], RdAddress[5:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
+ Outputs : Q[31:0]
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : slv_onewire_dpram.vhd
+ VHDL template : slv_onewire_dpram_tmpl.vhd
+ VHDL testbench : tb_slv_onewire_dpram_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : slv_onewire_dpram.srp
+ Element Usage :
+ DP16KB : 1
+ Estimated Resource Usage:
+ EBR : 1
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Tue Aug 11 14:48:40 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n slv_onewire_dpram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 6 -rwidth 32 -waddr_width 7 -wwidth 16 -rnum_words 64 -wnum_words 128 -resetmode SYNC -cascade -1 -e \r
+ Circuit name : slv_onewire_dpram\r
+ Module type : RAM_DP\r
+ Module Version : 6.1\r
+ Ports : \r
+ Inputs : WrAddress[6:0], RdAddress[5:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn\r
+ Outputs : Q[31:0]\r
+ I/O buffer : not inserted\r
+ EDIF output : suppressed\r
+ VHDL output : slv_onewire_dpram.vhd\r
+ VHDL template : slv_onewire_dpram_tmpl.vhd\r
+ VHDL testbench : tb_slv_onewire_dpram_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : slv_onewire_dpram.srp\r
+ Estimated Resource Usage:\r
+ EBR : 1\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: slv_onewire_dpram.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 6.1
+-- Tue Aug 11 14:48:40 2009
+
+-- parameterized module component declaration
+component slv_onewire_dpram
+ port (WrAddress: in std_logic_vector(6 downto 0);
+ RdAddress: in std_logic_vector(5 downto 0);
+ Data: in std_logic_vector(15 downto 0); WE: in std_logic;
+ RdClock: in std_logic; RdClockEn: in std_logic;
+ Reset: in std_logic; WrClock: in std_logic;
+ WrClockEn: in std_logic; Q: out std_logic_vector(31 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : slv_onewire_dpram
+ port map (WrAddress(6 downto 0)=>__, RdAddress(5 downto 0)=>__, Data(15 downto 0)=>__,
+ WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__, WrClock=>__,
+ WrClockEn=>__, Q(31 downto 0)=>__);
--- /dev/null
+SCUBA, Version ispLever_v8.0_PROD_Build (41)
+Wed Apr 28 15:46:17 2010
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n sync_pll_40m -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 40 -phase_cntl STATIC -fclkop 40 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode INTERNAL -extcap DISABLED -noclkos -noclkok -use_rst -e
+ Circuit name : sync_pll_40m
+ Module type : pll
+ Module Version : 5.1
+ Ports :
+ Inputs : CLK, RESET
+ Outputs : CLKOP, LOCK
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : sync_pll_40m.vhd
+ VHDL template : sync_pll_40m_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : not used
+ Report output : sync_pll_40m.srp
+ Element Usage :
+ EPLLD : 1
+ Estimated Resource Usage:
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v8.0_PROD_Build (41)\r
+Wed Apr 28 15:46:17 2010\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n sync_pll_40m -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 40 -phase_cntl STATIC -fclkop 40 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode INTERNAL -extcap DISABLED -noclkos -noclkok -use_rst -e \r
+ Circuit name : sync_pll_40m\r
+ Module type : pll\r
+ Module Version : 5.1\r
+ Ports : \r
+ Inputs : CLK, RESET\r
+ Outputs : CLKOP, LOCK\r
+ I/O buffer : not inserted\r
+ EDIF output : suppressed\r
+ VHDL output : sync_pll_40m.vhd\r
+ VHDL template : sync_pll_40m_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : not used\r
+ Report output : sync_pll_40m.srp\r
+ Estimated Resource Usage:\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: sync_pll_40m.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 5.1
+-- Wed Apr 28 15:46:17 2010
+
+-- parameterized module component declaration
+component sync_pll_40m
+ port (CLK: in std_logic; RESET: in std_logic; CLKOP: out std_logic;
+ LOCK: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : sync_pll_40m
+ port map (CLK=>__, RESET=>__, CLKOP=>__, LOCK=>__);
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v80_SP1_Build
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component test_fifo2
+ port (Data : in std_logic_vector(17 downto 0);
+ Clock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
+ Reset: in std_logic; Q : out std_logic_vector(17 downto 0);
+ Empty: out std_logic; Full: out std_logic
+ );
+ end component;
+
+ signal Data : std_logic_vector(17 downto 0) := (others => '0');
+ signal Clock: std_logic := '0';
+ signal WrEn: std_logic := '0';
+ signal RdEn: std_logic := '0';
+ signal Reset: std_logic := '0';
+ signal Q : std_logic_vector(17 downto 0);
+ signal Empty: std_logic;
+ signal Full: std_logic;
+begin
+ u1 : test_fifo2
+ port map (Data => Data, Clock => Clock, WrEn => WrEn, RdEn => RdEn,
+ Reset => Reset, Q => Q, Empty => Empty, Full => Full
+ );
+
+ process
+
+ begin
+ Data <= (others => '0') ;
+ for i in 0 to 1028 loop
+ wait until Clock'event and Clock = '1';
+ Data <= Data + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ Clock <= not Clock after 5.00 ns;
+
+ process
+
+ begin
+ WrEn <= '0' ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 1028 loop
+ wait until Clock'event and Clock = '1';
+ WrEn <= '1' after 1 ns;
+ end loop;
+ WrEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RdEn <= '0' ;
+ wait until Reset = '0';
+ wait until WrEn = '1';
+ wait until WrEn = '0';
+ for i in 0 to 1026 loop
+ wait until Clock'event and Clock = '1';
+ RdEn <= '1' after 1 ns;
+ end loop;
+ RdEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ Reset <= '1' ;
+ wait for 100 ns;
+ Reset <= '0' ;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+MODULE test_fifo2 DEFIN test_fifo2.vhd\r
+ SUBMODULE CU2\r
+ INSTANCE r_ctr_5\r
+ SUBMODULE VLO\r
+ INSTANCE scuba_vlo_inst\r
+ SUBMODULE CU2\r
+ INSTANCE r_ctr_4\r
+ SUBMODULE CU2\r
+ INSTANCE r_ctr_3\r
+ SUBMODULE CU2\r
+ INSTANCE r_ctr_2\r
+ SUBMODULE CU2\r
+ INSTANCE r_ctr_1\r
+ SUBMODULE CU2\r
+ INSTANCE r_ctr_0\r
+ SUBMODULE FADD2B\r
+ INSTANCE r_ctr_cia\r
+ SUBMODULE VHI\r
+ INSTANCE scuba_vhi_inst\r
+ SUBMODULE CU2\r
+ INSTANCE w_ctr_5\r
+ SUBMODULE CU2\r
+ INSTANCE w_ctr_4\r
+ SUBMODULE CU2\r
+ INSTANCE w_ctr_3\r
+ SUBMODULE CU2\r
+ INSTANCE w_ctr_2\r
+ SUBMODULE CU2\r
+ INSTANCE w_ctr_1\r
+ SUBMODULE CU2\r
+ INSTANCE w_ctr_0\r
+ SUBMODULE FADD2B\r
+ INSTANCE w_ctr_cia\r
+ SUBMODULE FADD2B\r
+ INSTANCE a1\r
+ SUBMODULE AGEB2\r
+ INSTANCE g_cmp_5\r
+ SUBMODULE AGEB2\r
+ INSTANCE g_cmp_4\r
+ SUBMODULE AGEB2\r
+ INSTANCE g_cmp_3\r
+ SUBMODULE AGEB2\r
+ INSTANCE g_cmp_2\r
+ SUBMODULE AGEB2\r
+ INSTANCE g_cmp_1\r
+ SUBMODULE AGEB2\r
+ INSTANCE g_cmp_0\r
+ SUBMODULE FADD2B\r
+ INSTANCE g_cmp_ci_a\r
+ SUBMODULE FADD2B\r
+ INSTANCE a0\r
+ SUBMODULE ALEB2\r
+ INSTANCE e_cmp_5\r
+ SUBMODULE ALEB2\r
+ INSTANCE e_cmp_4\r
+ SUBMODULE ALEB2\r
+ INSTANCE e_cmp_3\r
+ SUBMODULE ALEB2\r
+ INSTANCE e_cmp_2\r
+ SUBMODULE ALEB2\r
+ INSTANCE e_cmp_1\r
+ SUBMODULE ALEB2\r
+ INSTANCE e_cmp_0\r
+ SUBMODULE FADD2B\r
+ INSTANCE e_cmp_ci_a\r
+ SUBMODULE CB2\r
+ INSTANCE bdcnt_bctr_5\r
+ SUBMODULE CB2\r
+ INSTANCE bdcnt_bctr_4\r
+ SUBMODULE CB2\r
+ INSTANCE bdcnt_bctr_3\r
+ SUBMODULE CB2\r
+ INSTANCE bdcnt_bctr_2\r
+ SUBMODULE CB2\r
+ INSTANCE bdcnt_bctr_1\r
+ SUBMODULE CB2\r
+ INSTANCE bdcnt_bctr_0\r
+ SUBMODULE FADD2B\r
+ INSTANCE bdcnt_bctr_cia\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_0\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_1\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_2\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_3\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_4\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_5\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_6\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_7\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_8\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_9\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_10\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_11\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_12\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_13\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_14\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_15\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_16\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_17\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_18\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_19\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_20\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_21\r
+ SUBMODULE FD1S3DX\r
+ INSTANCE FF_22\r
+ SUBMODULE FD1S3BX\r
+ INSTANCE FF_23\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_24\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_25\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_26\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_27\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_28\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_29\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_30\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_31\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_32\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_33\r
+ SUBMODULE FD1P3DX\r
+ INSTANCE FF_34\r
+ SUBMODULE DP16KB\r
+ INSTANCE pdp_ram_0_0_0\r
+ SUBMODULE ROM16X1\r
+ INSTANCE LUT4_0\r
+ SUBMODULE ROM16X1\r
+ INSTANCE LUT4_1\r
+ SUBMODULE INV\r
+ INSTANCE INV_0\r
+ SUBMODULE INV\r
+ INSTANCE INV_1\r
+ SUBMODULE XOR2\r
+ INSTANCE XOR2_t0\r
+ SUBMODULE AND2\r
+ INSTANCE AND2_t1\r
+ SUBMODULE INV\r
+ INSTANCE INV_2\r
+ SUBMODULE AND2\r
+ INSTANCE AND2_t2\r
+ SUBMODULE INV\r
+ INSTANCE INV_3\r
+ SUBMODULE AND2\r
+ INSTANCE AND2_t3\r
--- /dev/null
+Data[17] i\r
+Data[16] i\r
+Data[15] i\r
+Data[14] i\r
+Data[13] i\r
+Data[12] i\r
+Data[11] i\r
+Data[10] i\r
+Data[9] i\r
+Data[8] i\r
+Data[7] i\r
+Data[6] i\r
+Data[5] i\r
+Data[4] i\r
+Data[3] i\r
+Data[2] i\r
+Data[1] i\r
+Data[0] i\r
+Clock i\r
+WrEn i\r
+RdEn i\r
+Reset i\r
+Q[17] o\r
+Q[16] o\r
+Q[15] o\r
+Q[14] o\r
+Q[13] o\r
+Q[12] o\r
+Q[11] o\r
+Q[10] o\r
+Q[9] o\r
+Q[8] o\r
+Q[7] o\r
+Q[6] o\r
+Q[5] o\r
+Q[4] o\r
+Q[3] o\r
+Q[2] o\r
+Q[1] o\r
+Q[0] o\r
+Empty o\r
+Full o\r
--- /dev/null
+SCUBA, Version ispLever_v8.0_PROD_Build (41)
+Thu May 20 14:41:10 2010
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n test_fifo2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifoblk -addr_width 10 -data_width 18 -num_words 1024 -no_enable -pe -1 -pf -1 -e
+ Circuit name : test_fifo2
+ Module type : fifoblk
+ Module Version : 4.8
+ Ports :
+ Inputs : Data[17:0], Clock, WrEn, RdEn, Reset
+ Outputs : Q[17:0], Empty, Full
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : test_fifo2.vhd
+ VHDL template : test_fifo2_tmpl.vhd
+ VHDL testbench : tb_test_fifo2_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : test_fifo2.srp
+ Element Usage :
+ AGEB2 : 6
+ ALEB2 : 6
+ AND2 : 3
+ CU2 : 12
+ CB2 : 6
+ FADD2B : 7
+ FD1P3DX : 33
+ FD1S3BX : 1
+ FD1S3DX : 1
+ INV : 4
+ ROM16X1 : 2
+ XOR2 : 1
+ DP16KB : 1
+ Estimated Resource Usage:
+ LUT : 80
+ EBR : 1
+ Reg : 35
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v8.0_PROD_Build (41)\r
+Thu May 20 14:41:10 2010\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n test_fifo2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifoblk -addr_width 10 -data_width 18 -num_words 1024 -no_enable -pe -1 -pf -1 -e \r
+ Circuit name : test_fifo2\r
+ Module type : fifoblk\r
+ Module Version : 4.8\r
+ Ports : \r
+ Inputs : Data[17:0], Clock, WrEn, RdEn, Reset\r
+ Outputs : Q[17:0], Empty, Full\r
+ I/O buffer : not inserted\r
+ EDIF output : suppressed\r
+ VHDL output : test_fifo2.vhd\r
+ VHDL template : test_fifo2_tmpl.vhd\r
+ VHDL testbench : tb_test_fifo2_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : test_fifo2.srp\r
+ Estimated Resource Usage:\r
+ LUT : 80\r
+ EBR : 1\r
+ Reg : 35\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: test_fifo2.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 4.8
+-- Thu May 20 14:41:10 2010
+
+-- parameterized module component declaration
+component test_fifo2
+ port (Data: in std_logic_vector(17 downto 0); Clock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ Q: out std_logic_vector(17 downto 0); Empty: out std_logic;
+ Full: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : test_fifo2
+ port map (Data(17 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__,
+ Reset=>__, Q(17 downto 0)=>__, Empty=>__, Full=>__);
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 4.7
+-- Mon Dec 14 14:54:16 2009
+
+-- parameterized module component declaration
+component test_fifo
+ port (Data: in std_logic_vector(17 downto 0); Clock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ Q: out std_logic_vector(17 downto 0); Empty: out std_logic;
+ Full: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : test_fifo
+ port map (Data(17 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__,
+ Reset=>__, Q(17 downto 0)=>__, Empty=>__, Full=>__);
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 5.2
+-- Wed Nov 18 17:17:38 2009
+
+-- parameterized module component declaration
+component testfifo
+ port (Data: in std_logic_vector(95 downto 0);
+ WrClock: in std_logic; RdClock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ RPReset: in std_logic; Q: out std_logic_vector(95 downto 0);
+ Empty: out std_logic; Full: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : testfifo
+ port map (Data(95 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
+ RdEn=>__, Reset=>__, RPReset=>__, Q(95 downto 0)=>__, Empty=>__,
+ Full=>__);
--- /dev/null
+MODULE adc_apv_map_mem\r
--- /dev/null
+MODULE adc_ch_in\r
--- /dev/null
+MODULE adc_onewire_map_mem\r
--- /dev/null
+MODULE adc_snoop_mem\r
--- /dev/null
+MODULE adder_16bit\r
--- /dev/null
+MODULE adder_5bit\r
--- /dev/null
+MODULE adder_6bit\r
--- /dev/null
+MODULE apv_adc_map_mem\r
--- /dev/null
+ispLEVER Auto-Make Log File\r
+---------------------------\r
+\r
+Starting: 'X:\Programme\ispTOOLS_80\ispcpld\BIN\checkini.exe -err=automake.err X:\Programme\ispTOOLS_80\ispcpld\config\ep5g00.ini'\r
+\r
+Done: completed successfully.\r
+\r
+Starting: 'X:\Programme\ispTOOLS_80\ispfpga\bin\nt\lci2prf.exe -oc adcmv3.lct adcmv3.lpf'\r
+\r
+BLOCK RESETPATHS;\r
+BLOCK ASYNCPATHS;\r
+Done: completed successfully.\r
--- /dev/null
+MODULE comp14bit\r
--- /dev/null
+MODULE comp4bit\r
--- /dev/null
+MODULE comp_12bit\r
--- /dev/null
+MODULE crossover\r
--- /dev/null
+MODULE decoder_8bit\r
--- /dev/null
+MODULE dll_100m\r
--- /dev/null
+MODULE eds_buffer_dpram\r
--- /dev/null
+MODULE fifo_1kx18\r
--- /dev/null
+MODULE fifo_2kx27\r
--- /dev/null
+MODULE frame_status_mem\r
--- /dev/null
+MODULE input_bram\r
--- /dev/null
+MODULE lattice_ecp2m_fifo_16bit_dualport\r
--- /dev/null
+MODULE lattice_ecp2m_fifo_18x1k\r
--- /dev/null
+MODULE onewire_spare_one\r
--- /dev/null
+MODULE ped_thr_true\r
--- /dev/null
+MODULE pll_40m\r
--- /dev/null
+MODULE serdes_gbe_2\r
--- /dev/null
+MODULE slv_onewire_dpram\r
--- /dev/null
+MODULE spi_dpram_32_to_8\r
--- /dev/null
+MODULE suber_12bit\r
--- /dev/null
+MODULE sync_pll_40m\r
--- /dev/null
+$ Start of Compile\r
+#Fri Jun 18 10:31:03 2010\r
+\r
+Synopsys VHDL Compiler, version comp350rcp1, Build 105R, built Jul 22 2009\r
+Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved\r
+\r
+@N: CD720 :"X:\Programme\ispTOOLS_80\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns\r
+@N:"I:\vhdl_pro\comp_adcmv3\design\sbuf.vhd":21:7:21:10|Top entity is set to sbuf.\r
+Process took 0h:00m:07s realtime, 0h:00m:02s cputime\r
+# Fri Jun 18 10:31:11 2010\r
+\r
+###########################################################]\r
--- /dev/null
+elbread.dll ver. 1.0.5.375 Wed Oct 12 10:43:07 2011
+\r
+\r
+--------------------------------------\r
+Entity | Architecture | Library\r
+--------------------------------------\r
+testbench | behavior | work\r
+spi_master | behavioral | work\r
+spi_slim | behavioral | work\r
+------------------------------------\r
+\r
+-------------------------------\r
+Package | Library\r
+-------------------------------\r
+standard | std\r
+TEXTIO | std\r
+std_logic_1164 | ieee\r
+std_logic_arith | ieee\r
+STD_LOGIC_UNSIGNED | ieee\r
+trb_net_std | work\r
+NUMERIC_STD | ieee\r
+trb_net_components | work\r
+-----------------------------\r
--- /dev/null
+adel -all\r
+# Library contents cleared.\r
+vcom ../../trbnet/trb_net_components.vhd\r
+# Compile...\r
+# File: I:\VHDL_Pro\trbnet\trb_net_components.vhd\r
+# Compile Package "trb_net_components"\r
+# Too many errors - compilation terminated\r
+# Error: COMP96_0055: trb_net_components.vhd : (6, 9): Cannot find referenced context element.\r
+# Error: COMP96_0078: trb_net_components.vhd : (19, 39): Unknown identifier "c_NO".\r
+# Error: COMP96_0133: trb_net_components.vhd : (19, 39): Cannot find object declaration.\r
+# Error: COMP96_0104: trb_net_components.vhd : (19, 39): Undefined type of expression.\r
+# Error: COMP96_0077: trb_net_components.vhd : (19, 39): Assignment target incompatible with right side. Expected type 'INTEGER'.\r
+# Error: COMP96_0078: trb_net_components.vhd : (20, 39): Unknown identifier "c_YES".\r
+# Error: COMP96_0133: trb_net_components.vhd : (20, 39): Cannot find object declaration.\r
+# Error: COMP96_0104: trb_net_components.vhd : (20, 39): Undefined type of expression.\r
+# Error: COMP96_0077: trb_net_components.vhd : (20, 39): Assignment target incompatible with right side. Expected type 'INTEGER'.\r
+# Error: COMP96_0078: trb_net_components.vhd : (29, 47): Unknown identifier "c_DATA_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (29, 47): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (29, 47): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (30, 47): Unknown identifier "c_NUM_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (30, 47): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (30, 47): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (33, 47): Unknown identifier "c_DATA_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (33, 47): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (33, 47): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (34, 47): Unknown identifier "c_NUM_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (34, 47): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (34, 47): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (105, 50): Unknown identifier "c_DATA_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (105, 50): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (105, 50): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (106, 49): Unknown identifier "c_NUM_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (106, 49): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (106, 49): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (113, 50): Unknown identifier "c_DATA_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (113, 50): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (113, 50): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (114, 50): Unknown identifier "c_NUM_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (114, 50): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (114, 50): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (132, 51): Unknown identifier "c_API_PASSIVE".\r
+# Error: COMP96_0133: trb_net_components.vhd : (132, 51): Cannot find object declaration.\r
+# Error: COMP96_0104: trb_net_components.vhd : (132, 51): Undefined type of expression.\r
+# Error: COMP96_0077: trb_net_components.vhd : (132, 51): Assignment target incompatible with right side. Expected type 'INTEGER'.\r
+# Error: COMP96_0078: trb_net_components.vhd : (135, 51): Unknown identifier "std_FORCE_REPLY".\r
+# Error: COMP96_0133: trb_net_components.vhd : (135, 51): Cannot find object declaration.\r
+# Error: COMP96_0104: trb_net_components.vhd : (135, 51): Undefined type of expression.\r
+# Error: COMP96_0077: trb_net_components.vhd : (135, 51): Assignment target incompatible with right side. Expected type 'INTEGER'.\r
+# Error: COMP96_0078: trb_net_components.vhd : (136, 51): Unknown identifier "std_SBUF_VERSION".\r
+# Error: COMP96_0133: trb_net_components.vhd : (136, 51): Cannot find object declaration.\r
+# Error: COMP96_0104: trb_net_components.vhd : (136, 51): Undefined type of expression.\r
+# Error: COMP96_0077: trb_net_components.vhd : (136, 51): Assignment target incompatible with right side. Expected type 'INTEGER'.\r
+# Error: COMP96_0078: trb_net_components.vhd : (137, 51): Unknown identifier "c_YES".\r
+# Error: COMP96_0133: trb_net_components.vhd : (137, 51): Cannot find object declaration.\r
+# Error: COMP96_0104: trb_net_components.vhd : (137, 51): Undefined type of expression.\r
+# Error: COMP96_0077: trb_net_components.vhd : (137, 51): Assignment target incompatible with right side. Expected type 'INTEGER'.\r
+# Error: COMP96_0078: trb_net_components.vhd : (138, 51): Unknown identifier "c_YES".\r
+# Error: COMP96_0133: trb_net_components.vhd : (138, 51): Cannot find object declaration.\r
+# Error: COMP96_0104: trb_net_components.vhd : (138, 51): Undefined type of expression.\r
+# Error: COMP96_0077: trb_net_components.vhd : (138, 51): Assignment target incompatible with right side. Expected type 'INTEGER'.\r
+# Error: COMP96_0078: trb_net_components.vhd : (139, 51): Unknown identifier "c_YES".\r
+# Error: COMP96_0133: trb_net_components.vhd : (139, 51): Cannot find object declaration.\r
+# Error: COMP96_0104: trb_net_components.vhd : (139, 51): Undefined type of expression.\r
+# Error: COMP96_0077: trb_net_components.vhd : (139, 51): Assignment target incompatible with right side. Expected type 'INTEGER'.\r
+# Error: COMP96_0078: trb_net_components.vhd : (140, 51): Unknown identifier "c_NO".\r
+# Error: COMP96_0133: trb_net_components.vhd : (140, 51): Cannot find object declaration.\r
+# Error: COMP96_0104: trb_net_components.vhd : (140, 51): Undefined type of expression.\r
+# Error: COMP96_0077: trb_net_components.vhd : (140, 51): Assignment target incompatible with right side. Expected type 'INTEGER'.\r
+# Error: COMP96_0078: trb_net_components.vhd : (153, 53): Unknown identifier "c_DATA_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (153, 53): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (153, 53): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (154, 53): Unknown identifier "c_NUM_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (154, 53): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (154, 53): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (163, 53): Unknown identifier "c_DATA_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (163, 53): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (163, 53): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (164, 53): Unknown identifier "c_NUM_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (164, 53): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (164, 53): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (180, 57): Unknown identifier "c_DATA_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (180, 57): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (180, 57): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (181, 57): Unknown identifier "c_NUM_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (181, 57): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (181, 57): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (184, 57): Unknown identifier "c_DATA_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (184, 57): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (184, 57): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (185, 57): Unknown identifier "c_NUM_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (185, 57): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (185, 57): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (188, 57): Unknown identifier "c_DATA_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (188, 57): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (188, 57): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (189, 57): Unknown identifier "c_NUM_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (189, 57): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (189, 57): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (192, 57): Unknown identifier "c_DATA_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (192, 57): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (192, 57): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (193, 57): Unknown identifier "c_NUM_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (193, 57): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (193, 57): Locally static expression is required in the range definition.\r
+# Error: COMP96_0078: trb_net_components.vhd : (213, 57): Unknown identifier "c_DATA_WIDTH".\r
+# Error: COMP96_0133: trb_net_components.vhd : (213, 57): Cannot find object declaration.\r
+# Error: COMP96_0094: trb_net_components.vhd : (213, 57): Locally static expression is required in the range definition.\r
+# Compile failure 100 Errors 0 Warnings Analysis time : 0.5 [s]\r
+vcom ../version.vhd\r
+# Compile...\r
+# File: I:\VHDL_Pro\comp_adcmv3\version.vhd\r
+# Compile Package "version"\r
+# Compile success 0 Errors 0 Warnings Analysis time : 63.0 [ms]\r
+vcom ../design/adcmv3_components.vhd\r
+# Compile...\r
+# File: I:\VHDL_Pro\comp_adcmv3\design\adcmv3_components.vhd\r
+# Compile Package "adcmv3_components"\r
+# Compile success 0 Errors 0 Warnings Analysis time : 0.2 [s]\r
+vcom ../../trbnet/trb_net_std.vhd\r
+# Compile...\r
+# File: I:\VHDL_Pro\trbnet\trb_net_std.vhd\r
+# Compile Package "trb_net_std"\r
+# Compile Package Body "trb_net_std"\r
+# Compile success 0 Errors 0 Warnings Analysis time : 0.3 [s]\r
+vcom ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd\r
+# Compile...\r
+# File: I:\VHDL_Pro\trbnet\lattice\ecp2m\lattice_ecp2m_fifo.vhd\r
+# Compile Package "lattice_ecp2m_fifo"\r
+# Compile success 0 Errors 0 Warnings Analysis time : 93.0 [ms]\r
+vcom ../../trbnet/trb_net_components.vhd\r
+# Compile...\r
+# File: I:\VHDL_Pro\trbnet\trb_net_components.vhd\r
+# Compile Package "trb_net_components"\r
+# Compile success 0 Errors 0 Warnings Analysis time : 0.4 [s]\r
+vcom ../version.vhd\r
+# Compile...\r
+# File: I:\VHDL_Pro\comp_adcmv3\version.vhd\r
+# Compile Package "version"\r
+# Compile success 0 Errors 0 Warnings Analysis time : 78.0 [ms]\r
+vcom ../design/adcmv3_components.vhd\r
+# Compile...\r
+# File: I:\VHDL_Pro\comp_adcmv3\design\adcmv3_components.vhd\r
+# Compile Package "adcmv3_components"\r
+# Compile success 0 Errors 0 Warnings Analysis time : 0.3 [s]\r
+vcom ../../trbnet/trb_net_std.vhd\r
+# Compile...\r
+# File: I:\VHDL_Pro\trbnet\trb_net_std.vhd\r
+# Compile Package "trb_net_std"\r
+# Compile Package Body "trb_net_std"\r
+# Compile success 0 Errors 0 Warnings Analysis time : 0.2 [s]\r
+vcom ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd\r
+# Compile...\r
+# File: I:\VHDL_Pro\trbnet\lattice\ecp2m\lattice_ecp2m_fifo.vhd\r
+# Compile Package "lattice_ecp2m_fifo"\r
+# Compile success 0 Errors 0 Warnings Analysis time : 78.0 [ms]\r
+vcom ../../trbnet/special/spi_slim.vhd\r
+# Compile...\r
+# File: I:\VHDL_Pro\trbnet\special\spi_slim.vhd\r
+# Compile Entity "spi_slim"\r
+# Warning: COMP96_0119: spi_slim.vhd : (14, 30): The range is 'null range'.\r
+# Compile Architecture "Behavioral" of Entity "spi_slim"\r
+# Compile success 0 Errors 1 Warnings Analysis time : 0.5 [s]\r
+vcom ../../trbnet/special/spi_master.vhd\r
+# Compile...\r
+# File: I:\VHDL_Pro\trbnet\special\spi_master.vhd\r
+# Compile Entity "spi_master"\r
+# Compile Architecture "Behavioral" of Entity "spi_master"\r
+# Compile success 0 Errors 0 Warnings Analysis time : 0.2 [s]\r
+vcom ../sim/tb_spi_master.vhd\r
+# Compile...\r
+# File: I:\VHDL_Pro\comp_adcmv3\sim\tb_spi_master.vhd\r
+# Compile Entity "testbench"\r
+# Compile Architecture "behavior" of Entity "testbench"\r
+# Compile success 0 Errors 0 Warnings Analysis time : 0.2 [s]\r
+vsim testbench -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+# ELBREAD: Elaboration process.\r
+# ELBREAD: Elaboration time 0.1 [s].\r
+# vsim: Stack memory: 32MB\r
+# vsim: Retval memory: 32MB\r
+# KERNEL: Main thread initiated.\r
+# KERNEL: Kernel process initialization phase.\r
+# KERNEL: Time resolution set to 1ps.\r
+# ELAB2: Elaboration final pass...\r
+# ELAB2: Create instances ...\r
+# ELAB2: Create instances complete.\r
+# ELAB2: You do not have a license to run VHDL performance optimized simulation. Contact Aldec for ordering information - sales@aldec.com.\r
+# ELAB2: Elaboration final pass complete - time: 0.1 [s].\r
+# KERNEL: Warning: You are using the Active-HDL Lattice Edition. The performance of simulation is running at a reduced rate.\r
+# KERNEL: Warning: Contact Aldec for available upgrade options - sales@aldec.com.\r
+# KERNEL: Kernel process initialization done.\r
+# Allocation: Simulator allocated 2547 kB (elbread=1023 elab2=1167 kernel=356 sdf=0)\r
+# 10:43, Mittwoch, 12. Oktober 2011\r
+# Simulation has been initialized\r
+# Selected Top-Level: testbench (behavior)\r
+do tb_spi_master_vhdf.udo testbench\r
+add wave *\r
+run 1000 ns\r
+# KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).\r
+# KERNEL: Time: 0 ps, Iteration: 0, Instance: /uut/THE_SPI_SLIM, Process: line__192.\r
+# KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).\r
+# KERNEL: Time: 0 ps, Iteration: 0, Instance: /uut/THE_SPI_SLIM, Process: line__192.\r
+# KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).\r
+# KERNEL: Time: 0 ps, Iteration: 0, Instance: /uut/THE_SPI_SLIM, Process: line__549.\r
+# KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).\r
+# KERNEL: Time: 0 ps, Iteration: 0, Instance: /uut/THE_SPI_SLIM, Process: line__614.\r
+# KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).\r
+# KERNEL: Time: 10 ns, Iteration: 1, Instance: /uut/THE_SPI_SLIM, Process: THE_CLOCK_DIVIDER.\r
+# KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).\r
+# KERNEL: Time: 10 ns, Iteration: 2, Instance: /uut/THE_SPI_SLIM, Process: line__192.\r
+# KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).\r
+# KERNEL: Time: 10 ns, Iteration: 2, Instance: /uut/THE_SPI_SLIM, Process: line__192.\r
+# KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).\r
+# KERNEL: Time: 20 ns, Iteration: 1, Instance: /uut/THE_SPI_SLIM, Process: THE_CLOCK_DIVIDER.\r
+# KERNEL: stopped at time: 1 us\r
+run 10us\r
+# KERNEL: stopped at time: 11 us\r
+run 10us\r
+# KERNEL: stopped at time: 21 us\r
+# Simulation has been stopped\r
--- /dev/null
+[pbs1]
+system = linux
+corenum = 2
+env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+[pbs2]
+system = linux
+corenum = 2
+env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+[pbs3]
+system = linux
+corenum = 2
+env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+[pbs4]
+system = linux
+corenum = 2
+env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+[pbs5]
+system = linux
+corenum = 2
+env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+[pbs6]
+system = linux
+corenum = 2
+env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+[pbs7]
+system = linux
+corenum = 2
+env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+[pbs8]
+system = linux
+corenum = 2
+env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+[pbs9]
+system = linux
+corenum = 2
+env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
+[pbs10]
+system = linux
+corenum = 2
+env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component adc_apv_map_mem
+ port (Address : in std_logic_vector(6 downto 0);
+ Q : out std_logic_vector(3 downto 0)
+ );
+ end component;
+
+ signal Address : std_logic_vector(6 downto 0) := (others => '0');
+ signal Q : std_logic_vector(3 downto 0);
+begin
+ u1 : adc_apv_map_mem
+ port map (Address => Address, Q => Q
+ );
+
+ process
+
+ begin
+ Address <= (others => '0') ;
+ wait for 100 ns;
+ wait for 10 ns;
+ for i in 0 to 131 loop
+ wait for 10 ns;
+ Address <= Address + '1' ;
+ end loop;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component adc_onewire_map_mem
+ port (Address : in std_logic_vector(6 downto 0);
+ Q : out std_logic_vector(3 downto 0)
+ );
+ end component;
+
+ signal Address : std_logic_vector(6 downto 0) := (others => '0');
+ signal Q : std_logic_vector(3 downto 0);
+begin
+ u1 : adc_onewire_map_mem
+ port map (Address => Address, Q => Q
+ );
+
+ process
+
+ begin
+ Address <= (others => '0') ;
+ wait for 100 ns;
+ wait for 10 ns;
+ for i in 0 to 131 loop
+ wait for 10 ns;
+ Address <= Address + '1' ;
+ end loop;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component apv_adc_map_mem
+ port (Address : in std_logic_vector(6 downto 0);
+ Q : out std_logic_vector(3 downto 0)
+ );
+ end component;
+
+ signal Address : std_logic_vector(6 downto 0) := (others => '0');
+ signal Q : std_logic_vector(3 downto 0);
+begin
+ u1 : apv_adc_map_mem
+ port map (Address => Address, Q => Q
+ );
+
+ process
+
+ begin
+ Address <= (others => '0') ;
+ wait for 100 ns;
+ wait for 10 ns;
+ for i in 0 to 131 loop
+ wait for 10 ns;
+ Address <= Address + '1' ;
+ end loop;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component apv_map_mem
+ port (Address : in std_logic_vector(6 downto 0);
+ Q : out std_logic_vector(3 downto 0)
+ );
+ end component;
+
+ signal Address : std_logic_vector(6 downto 0) := (others => '0');
+ signal Q : std_logic_vector(3 downto 0);
+begin
+ u1 : apv_map_mem
+ port map (Address => Address, Q => Q
+ );
+
+ process
+
+ begin
+ Address <= (others => '0') ;
+ wait for 100 ns;
+ wait for 10 ns;
+ for i in 0 to 131 loop
+ wait for 10 ns;
+ Address <= Address + '1' ;
+ end loop;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component comp4bit
+ port (DataA : in std_logic_vector(3 downto 0);
+ DataB : in std_logic_vector(3 downto 0); AGTB: out std_logic
+ );
+ end component;
+
+ signal DataA : std_logic_vector(3 downto 0) := (others => '0');
+ signal DataB : std_logic_vector(3 downto 0) := (others => '0');
+ signal AGTB: std_logic;
+begin
+ u1 : comp4bit
+ port map (DataA => DataA, DataB => DataB, AGTB => AGTB
+ );
+
+ process
+
+ begin
+ DataA <= (others => '0') ;
+ for i in 0 to 200 loop
+ wait for 10 ns;
+ DataA <= DataA + '1' ;
+ end loop;
+ wait;
+ end process;
+
+ process
+
+ begin
+ DataB <= (others => '0') ;
+ for i in 0 to 100 loop
+ wait for 10 ns;
+ DataB <= DataB + '1' ;
+ end loop;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component crossfifo
+ port (Data : in std_logic_vector(95 downto 0);
+ WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
+ RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
+ Q : out std_logic_vector(95 downto 0); Empty: out std_logic;
+ Full: out std_logic; AlmostEmpty: out std_logic
+ );
+ end component;
+
+ signal Data : std_logic_vector(95 downto 0) := (others => '0');
+ signal WrClock: std_logic := '0';
+ signal RdClock: std_logic := '0';
+ signal WrEn: std_logic := '0';
+ signal RdEn: std_logic := '0';
+ signal Reset: std_logic := '0';
+ signal RPReset: std_logic := '0';
+ signal Q : std_logic_vector(95 downto 0);
+ signal Empty: std_logic;
+ signal Full: std_logic;
+ signal AlmostEmpty: std_logic;
+begin
+ u1 : crossfifo
+ port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
+ WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
+ Q => Q, Empty => Empty, Full => Full, AlmostEmpty => AlmostEmpty
+ );
+
+ process
+
+ begin
+ Data <= (others => '0') ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 259 loop
+ wait until WrClock'event and WrClock = '1';
+ Data <= Data + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ WrClock <= not WrClock after 5.00 ns;
+
+ RdClock <= not RdClock after 5.00 ns;
+
+ process
+
+ begin
+ WrEn <= '0' ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 259 loop
+ wait until WrClock'event and WrClock = '1';
+ WrEn <= '1' after 1 ns;
+ end loop;
+ WrEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RdEn <= '0' ;
+ wait until Reset = '0';
+ wait until WrEn = '1';
+ wait until WrEn = '0';
+ for i in 0 to 259 loop
+ wait until RdClock'event and RdClock = '1';
+ RdEn <= '1' after 1 ns;
+ end loop;
+ RdEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ Reset <= '1' ;
+ wait for 100 ns;
+ Reset <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RPReset <= '1' ;
+ wait for 100 ns;
+ RPReset <= '0' ;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_PROD_Build (44)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component crossover
+ port (Data : in std_logic_vector(95 downto 0);
+ WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
+ RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
+ Q : out std_logic_vector(95 downto 0);
+ WCNT : out std_logic_vector(4 downto 0);
+ RCNT : out std_logic_vector(4 downto 0); Empty: out std_logic;
+ Full: out std_logic
+ );
+ end component;
+
+ signal Data : std_logic_vector(95 downto 0) := (others => '0');
+ signal WrClock: std_logic := '0';
+ signal RdClock: std_logic := '0';
+ signal WrEn: std_logic := '0';
+ signal RdEn: std_logic := '0';
+ signal Reset: std_logic := '0';
+ signal RPReset: std_logic := '0';
+ signal Q : std_logic_vector(95 downto 0);
+ signal WCNT : std_logic_vector(4 downto 0);
+ signal RCNT : std_logic_vector(4 downto 0);
+ signal Empty: std_logic;
+ signal Full: std_logic;
+begin
+ u1 : crossover
+ port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
+ WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
+ Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full
+ );
+
+ process
+
+ begin
+ Data <= (others => '0') ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 19 loop
+ wait until WrClock'event and WrClock = '1';
+ Data <= Data + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ WrClock <= not WrClock after 5.00 ns;
+
+ RdClock <= not RdClock after 5.00 ns;
+
+ process
+
+ begin
+ WrEn <= '0' ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 19 loop
+ wait until WrClock'event and WrClock = '1';
+ WrEn <= '1' after 1 ns;
+ end loop;
+ WrEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RdEn <= '0' ;
+ wait until Reset = '0';
+ wait until WrEn = '1';
+ wait until WrEn = '0';
+ for i in 0 to 19 loop
+ wait until RdClock'event and RdClock = '1';
+ RdEn <= '1' after 1 ns;
+ end loop;
+ RdEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ Reset <= '1' ;
+ wait for 100 ns;
+ Reset <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RPReset <= '1' ;
+ wait for 100 ns;
+ RPReset <= '0' ;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_PROD_Build (44)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component dpram_8x19
+ port (WrAddress : in std_logic_vector(3 downto 0);
+ Data : in std_logic_vector(18 downto 0); WrClock: in std_logic;
+ WE: in std_logic; WrClockEn: in std_logic;
+ RdAddress : in std_logic_vector(3 downto 0);
+ Q : out std_logic_vector(18 downto 0)
+ );
+ end component;
+
+ signal WrAddress : std_logic_vector(3 downto 0) := (others => '0');
+ signal Data : std_logic_vector(18 downto 0) := (others => '0');
+ signal WrClock: std_logic := '0';
+ signal WE: std_logic := '0';
+ signal WrClockEn: std_logic := '0';
+ signal RdAddress : std_logic_vector(3 downto 0) := (others => '0');
+ signal Q : std_logic_vector(18 downto 0);
+begin
+ u1 : dpram_8x19
+ port map (WrAddress => WrAddress, Data => Data, WrClock => WrClock,
+ WE => WE, WrClockEn => WrClockEn, RdAddress => RdAddress, Q => Q
+ );
+
+ process
+
+ begin
+ WrAddress <= (others => '0') ;
+ wait for 100 ns;
+ wait for 10 ns;
+ for i in 0 to 38 loop
+ wait until WrClock'event and WrClock = '1';
+ WrAddress <= WrAddress + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ process
+
+ begin
+ Data <= (others => '0') ;
+ wait for 100 ns;
+ wait for 10 ns;
+ for i in 0 to 19 loop
+ wait until WrClock'event and WrClock = '1';
+ Data <= Data + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ WrClock <= not WrClock after 5.00 ns;
+
+ process
+
+ begin
+ WE <= '0' ;
+ wait for 10 ns;
+ for i in 0 to 19 loop
+ wait until WrClock'event and WrClock = '1';
+ WE <= '1' after 1 ns;
+ end loop;
+ WE <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ WrClockEn <= '0' ;
+ wait for 100 ns;
+ wait for 10 ns;
+ WrClockEn <= '1' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RdAddress <= (others => '0') ;
+ wait for 100 ns;
+ wait for 10 ns;
+ for i in 0 to 38 loop
+ wait for 10 ns;
+ RdAddress <= RdAddress + '1' ;
+ end loop;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v8.0_PROD_Build (41)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component fifo_16x11
+ port (Data : in std_logic_vector(10 downto 0);
+ Clock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
+ Reset: in std_logic; Q : out std_logic_vector(10 downto 0);
+ WCNT : out std_logic_vector(4 downto 0); Empty: out std_logic;
+ Full: out std_logic
+ );
+ end component;
+
+ signal Data : std_logic_vector(10 downto 0) := (others => '0');
+ signal Clock: std_logic := '0';
+ signal WrEn: std_logic := '0';
+ signal RdEn: std_logic := '0';
+ signal Reset: std_logic := '0';
+ signal Q : std_logic_vector(10 downto 0);
+ signal WCNT : std_logic_vector(4 downto 0);
+ signal Empty: std_logic;
+ signal Full: std_logic;
+begin
+ u1 : fifo_16x11
+ port map (Data => Data, Clock => Clock, WrEn => WrEn, RdEn => RdEn,
+ Reset => Reset, Q => Q, WCNT => WCNT, Empty => Empty, Full => Full
+ );
+
+ process
+
+ begin
+ Data <= (others => '0') ;
+ for i in 0 to 20 loop
+ wait until Clock'event and Clock = '1';
+ Data <= Data + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ Clock <= not Clock after 5.00 ns;
+
+ process
+
+ begin
+ WrEn <= '0' ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 20 loop
+ wait until Clock'event and Clock = '1';
+ WrEn <= '1' after 1 ns;
+ end loop;
+ WrEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RdEn <= '0' ;
+ wait until Reset = '0';
+ wait until WrEn = '1';
+ wait until WrEn = '0';
+ for i in 0 to 18 loop
+ wait until Clock'event and Clock = '1';
+ RdEn <= '1' after 1 ns;
+ end loop;
+ RdEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ Reset <= '1' ;
+ wait for 100 ns;
+ Reset <= '0' ;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v80_SP1_Build
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component fifo_1kx18
+ port (Data : in std_logic_vector(17 downto 0);
+ Clock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
+ Reset: in std_logic; Q : out std_logic_vector(17 downto 0);
+ WCNT : out std_logic_vector(10 downto 0); Empty: out std_logic;
+ Full: out std_logic; AlmostFull: out std_logic
+ );
+ end component;
+
+ signal Data : std_logic_vector(17 downto 0) := (others => '0');
+ signal Clock: std_logic := '0';
+ signal WrEn: std_logic := '0';
+ signal RdEn: std_logic := '0';
+ signal Reset: std_logic := '0';
+ signal Q : std_logic_vector(17 downto 0);
+ signal WCNT : std_logic_vector(10 downto 0);
+ signal Empty: std_logic;
+ signal Full: std_logic;
+ signal AlmostFull: std_logic;
+begin
+ u1 : fifo_1kx18
+ port map (Data => Data, Clock => Clock, WrEn => WrEn, RdEn => RdEn,
+ Reset => Reset, Q => Q, WCNT => WCNT, Empty => Empty, Full => Full,
+ AlmostFull => AlmostFull
+ );
+
+ process
+
+ begin
+ Data <= (others => '0') ;
+ for i in 0 to 1028 loop
+ wait until Clock'event and Clock = '1';
+ Data <= Data + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ Clock <= not Clock after 5.00 ns;
+
+ process
+
+ begin
+ WrEn <= '0' ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 1028 loop
+ wait until Clock'event and Clock = '1';
+ WrEn <= '1' after 1 ns;
+ end loop;
+ WrEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RdEn <= '0' ;
+ wait until Reset = '0';
+ wait until WrEn = '1';
+ wait until WrEn = '0';
+ for i in 0 to 1026 loop
+ wait until Clock'event and Clock = '1';
+ RdEn <= '1' after 1 ns;
+ end loop;
+ RdEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ Reset <= '1' ;
+ wait for 100 ns;
+ Reset <= '0' ;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component mult_3x8
+ port (Clock: in std_logic; ClkEn: in std_logic;
+ Aclr: in std_logic; DataA : in std_logic_vector(2 downto 0);
+ DataB : in std_logic_vector(7 downto 0);
+ Result : out std_logic_vector(10 downto 0)
+ );
+ end component;
+
+ signal Clock: std_logic := '0';
+ signal ClkEn: std_logic := '0';
+ signal Aclr: std_logic := '0';
+ signal DataA : std_logic_vector(2 downto 0) := (others => '0');
+ signal DataB : std_logic_vector(7 downto 0) := (others => '0');
+ signal Result : std_logic_vector(10 downto 0);
+begin
+ u1 : mult_3x8
+ port map (Clock => Clock, ClkEn => ClkEn, Aclr => Aclr, DataA => DataA,
+ DataB => DataB, Result => Result
+ );
+
+ Clock <= not Clock after 5.00 ns;
+
+ process
+
+ begin
+ ClkEn <= '1' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ Aclr <= '1' ;
+ wait for 100 ns;
+ Aclr <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ DataA <= (others => '0') ;
+ for i in 0 to 200 loop
+ wait until Clock'event and Clock = '1';
+ DataA <= DataA + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ process
+
+ begin
+ DataB <= (others => '0') ;
+ for i in 0 to 200 loop
+ wait until Clock'event and Clock = '1';
+ DataB <= DataB + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component onewire_spare_one
+ port (Address : in std_logic_vector(2 downto 0);
+ Q : out std_logic_vector(3 downto 0)
+ );
+ end component;
+
+ signal Address : std_logic_vector(2 downto 0) := (others => '0');
+ signal Q : std_logic_vector(3 downto 0);
+begin
+ u1 : onewire_spare_one
+ port map (Address => Address, Q => Q
+ );
+
+ process
+
+ begin
+ Address <= (others => '0') ;
+ wait for 100 ns;
+ wait for 10 ns;
+ for i in 0 to 11 loop
+ wait for 10 ns;
+ Address <= Address + '1' ;
+ end loop;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component suber_12bit
+ port (DataA : in std_logic_vector(11 downto 0);
+ DataB : in std_logic_vector(11 downto 0); Clock: in std_logic;
+ Reset: in std_logic; ClockEn: in std_logic;
+ Result : out std_logic_vector(11 downto 0)
+ );
+ end component;
+
+ signal DataA : std_logic_vector(11 downto 0) := (others => '0');
+ signal DataB : std_logic_vector(11 downto 0) := (others => '0');
+ signal Clock: std_logic := '0';
+ signal Reset: std_logic := '0';
+ signal ClockEn: std_logic := '0';
+ signal Result : std_logic_vector(11 downto 0);
+begin
+ u1 : suber_12bit
+ port map (DataA => DataA, DataB => DataB, Clock => Clock, Reset => Reset,
+ ClockEn => ClockEn, Result => Result
+ );
+
+ process
+
+ begin
+ DataA <= (others => '0') ;
+ for i in 0 to 200 loop
+ wait until Clock'event and Clock = '1';
+ DataA <= DataA + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ process
+
+ begin
+ DataB <= (others => '0') ;
+ for i in 0 to 200 loop
+ wait until Clock'event and Clock = '1';
+ DataB <= DataB + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ Clock <= not Clock after 5.00 ns;
+
+ process
+
+ begin
+ Reset <= '1' ;
+ wait for 100 ns;
+ Reset <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ ClockEn <= '1' ;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package adcmv3_componets is
+
+ type debug_array_t is array(integer range <>) of
+ std_logic_vector(15 downto 0);
+
+ component debug_multiplexer
+ generic (
+ NUM_PORTS : integer range 1 to 32);
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ DEBUG_LINE_IN : in debug_array_t(0 to NUM_PORTS-1);
+ DEBUG_LINE_OUT : out std_logic_vector(15 downto 0);
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic
+ );
+ end component;
+
+end package;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.adcmv3_componets.all;
+
+entity debug_multiplexer is
+ generic (
+ NUM_PORTS : integer range 1 to 32 := 1
+ );
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ DEBUG_LINE_IN : in debug_array_t(0 to NUM_PORTS-1);
+ DEBUG_LINE_OUT : out std_logic_vector(15 downto 0);
+
+ -- Slave bus
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic
+
+ );
+end entity;
+
+architecture Behavioral of debug_multiplexer is
+
+ signal port_select : std_logic_vector(7 downto 0);
+ signal debug_line_o : std_logic_vector(15 downto 0);
+
+ signal slv_data_out_o : std_logic_vector(31 downto 0);
+ signal slv_no_more_data_o : std_logic;
+ signal slv_unknown_addr_o : std_logic;
+ signal slv_ack_o : std_logic;
+
+begin
+
+ PROC_MULTIPLEXER: process(port_select,
+ DEBUG_LINE_IN)
+ begin
+ if (unsigned(port_select) < NUM_PORTS) then
+ debug_line_o <=
+ DEBUG_LINE_IN(to_integer(unsigned(port_select)));
+ elsif (unsigned(port_select) = NUM_PORTS) then
+ -- Checkerboard
+ for I in 0 to 7 loop
+ debug_line_o(I * 2) <= CLK_IN;
+ debug_line_o(I * 2 + 1) <= not CLK_IN;
+ end loop;
+ else
+ debug_line_o <= (others => '1');
+ end if;
+ end process PROC_MULTIPLEXER;
+
+ PROC_SLAVE_BUS: process(CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ slv_data_out_o <= (others => '0');
+ slv_no_more_data_o <= '0';
+ slv_unknown_addr_o <= '0';
+ slv_ack_o <= '0';
+ port_select <= (others => '0');
+ else
+ slv_ack_o <= '1';
+ slv_unknown_addr_o <= '0';
+ slv_no_more_data_o <= '0';
+ slv_data_out_o <= (others => '0');
+
+ if (SLV_WRITE_IN = '1') then
+ case SLV_ADDR_IN is
+ when x"0000" =>
+ if (unsigned(SLV_DATA_IN(7 downto 0)) < NUM_PORTS + 1) then
+ port_select <= SLV_DATA_IN(7 downto 0);
+ end if;
+ slv_ack_o <= '1';
+
+ when others =>
+ slv_unknown_addr_o <= '1';
+ slv_ack_o <= '0';
+ end case;
+
+ elsif (SLV_READ_IN = '1') then
+ case SLV_ADDR_IN is
+ when x"0000" =>
+ slv_data_out_o(7 downto 0) <= port_select;
+ slv_data_out_o(31 downto 8) <= (others => '0');
+
+ when others =>
+ slv_unknown_addr_o <= '1';
+ slv_ack_o <= '0';
+ end case;
+
+ else
+ slv_ack_o <= '0';
+ end if;
+ end if;
+ end if;
+ end process PROC_SLAVE_BUS;
+
+ -----------------------------------------------------------------------------
+ -- Output Signals
+ -----------------------------------------------------------------------------
+
+ SLV_DATA_OUT <= slv_data_out_o;
+ SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
+ SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
+ SLV_ACK_OUT <= slv_ack_o;
+
+ DEBUG_LINE_OUT <= debug_line_o;
+
+end Behavioral;
REGIO_INIT_BOARD_INFO => x"5aa5_3cc3",
REGIO_INIT_ENDPOINT_ID => x"0001",
REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
- REGIO_COMPILE_VERSION => x"0003",
+ -- REGIO_COMPILE_VERSION => x"0003",
REGIO_HARDWARE_VERSION => x"3300_0000", -- ADCMv3 signature
REGIO_USE_1WIRE_INTERFACE => c_YES,
TIMING_TRIGGER_RAW => c_YES,
--- /dev/null
+line 5789, col 42: Option set not found: vcs_ECP4_lib.
+line 5803, col 44: Option set not found: vcs_ECP45M_lib.
+
+
+Running in Lattice mode
+
+
+Starting: /usr/local/opt/lattice_diamond/diamond/3.2/synpbase/linux_a_64/mbin/synbatch
+Install: /usr/local/opt/lattice_diamond/diamond/3.2/synpbase
+Date: Tue Feb 10 22:13:23 2015
+Version: I-2013.09L-SP1-1
+
+Arguments: -product synplify_pro -batch adcmv3.prj
+ProductType: synplify_pro
+
+
+
+
+
+
+log file: "/home/rich/TRB/nXyter/trb3/adcm/workdir/adcmv3.srr"
+
+
+
+
+
+Running adcmv3|workdir
+
+
+Running: Compile on adcmv3|workdir
+
+
+Running: Compile Process on adcmv3|workdir
+
+
+Running: Compile Input on adcmv3|workdir
+
+Copied /home/rich/TRB/nXyter/trb3/adcm/workdir/synwork/adcmv3_comp.srs to /home/rich/TRB/nXyter/trb3/adcm/workdir/adcmv3.srs
+
+compiler Completed
+Return Code: 0
+Run Time:00h:00m:28s
+
+
+Complete: Compile Process on adcmv3|workdir
+
+
+Running: Pre-mapping on adcmv3|workdir
+
+premap Completed with warnings
+Return Code: 1
+Run Time:00h:00m:06s
+
+
+Complete: Compile on adcmv3|workdir
+
+
+Running: Map on adcmv3|workdir
+
+
+Running: Map & Optimize on adcmv3|workdir
+
+fpga_mapper Completed with warnings
+Return Code: 1
+Run Time:00h:03m:16s
+
+
+Complete: Map on adcmv3|workdir
+
+Complete: Logic Synthesis on adcmv3|workdir
+
+exit status=0
+
+
+exit status=0
+
+
--- /dev/null
+-- attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+ constant VERSION_NUMBER_TIME : integer := 1423599792;
+ constant VERSION_NUMBER : integer := to_integer(x"");
+
+end package version;
jspc29 / adcm.git / commitdiff