If your CTS does not accept further events and has a full read-out queue, consider to check the
correct configuration of the read-out. For a in-depth discussion of the FSM states see \cite{penschuck12}.
-\subsubsection{Trigger Logic}
+\subsubsection{SubSubEvent Data Format}
+ The CTS's FEE offers two independent readout-ports (and therefore the subsubevent data consists of two blocks):
+ The first port is controlled by the CTS itself, while the second one may be connected to external trigger logic.
+ On the top-entity the default values of the signal connected to optional external trigger logic are chosen to
+ automatically disable the second port, if no external module is present.
+
+ The TrbNet does not automatically insert a header between the two sections, and as the amount of data sent by
+ the CTS is configurable, the subsubevent includes a header in its first word (see table
+ \ref{tab:cts_subsubevent_header}). It can be used to calculate the size of the CTS frame. All remaining words in the
+ subsubevent originate from the external trigger module adapter. A commented example frame is shown in table
+ \ref{ref:cts_subsubevent_example}.
+
+ \begin{table}
+ \begin{center}
+ \begin{tabularx}{\textwidth}{|r@{}@{}c@{}@{}l|lX|} \hline
+ \multicolumn{3}{|c|}{\textbf{Bit(s)}} &
+ \multicolumn{2}{c|}{\textbf{Description}} \\\hline\hline
+ \addr{15} & : & \addr{~0} & &{State of all Trigger Channels when trigger was accepted}\\
+ \multicolumn{3}{|c|}{\addr{19:16}} & &{Number of Input included (each input includes two words: the number of cycles asserted (lower address), number of rising edges (upper address))}\\
+ \multicolumn{3}{|c|}{\addr{24:20}} & &{Number of Trigger Channels used (two words per channel, same format as above)}\\
+ \multicolumn{3}{|c|}{\addr{25}} & &{Include \emph{last idle}, \emph{dead time} counters (two words)}\\
+ \multicolumn{3}{|c|}{\addr{26}} & &{Include Counters \emph{Trigger asserted}, \emph{Trigger Edges}, \emph{Triggers Accepted} (three words)}\\
+ \multicolumn{3}{|c|}{\addr{27}} & &{Timestamp with resolution of 10 ns / tick (one word) }\\\hline
+ \end{tabularx}
+ \caption[CTS SubSubEvent Header]{CTS SubSubEvent Header. The upper two bytes describe the package's content. Its total
+ length can be computed using the length denoted in the brackets behind each property. All
+ flags are high-active. The number of inputs and ITCs must be specified as it depends on the configuration
+ used during synthesis.}
+ \label{tab:cts_subsubevent_header}
+ \end{center}
+ \end{table}
+
+
+
+ \begin{table}[H]
+ \begin{tabular}{|r|r|l|}\hline
+ Addr & Value & Description \\\hline\hline
+
+ -1 & \texttt{0x002cf3c0} & SubSubEvent Header, indicating a length of 0x11 \\\hline
+ 0x00 & \texttt{0x06ee43c01} & CTS Header. \\
+ && ITC status bitmask: 0x3c01\\
+ && Number of Input Counters: 0x4\\
+ && Number of ITC Counters: 0xe\\
+ && Idle/Dead counters: yes\\
+ && Trigger statistics: yes\\
+ && Timestamp: yes \\\hline\hline
+ 0x01 & \texttt{0xcb1a3130} & Level Counter Input 0 (\# cycles input was asserted) \\\hline
+ 0x02 & \texttt{0x00000000} & Edge Counter Input 0 (\# rising edges) \\\hline
+ 0x03 & \texttt{0x004118ba} & Level Counter Input 1 (\# cycles input was asserted) \\\hline
+ 0x04 & \texttt{0x02741321} & Edge Counter Input 1 (\# rising edges) \\\hline
+ 0x05 & \texttt{0xcb1a3130} & Level Counter Input 2 (\# cycles input was asserted) \\\hline
+ 0x06 & \texttt{0x00000000} & Edge Counter Input 2 (\# rising edges) \\\hline
+ 0x07 & \texttt{0x004118ba} & Level Counter Input 3 (\# cycles input was asserted) \\\hline
+ 0x08 & \texttt{0x02741321} & Edge Counter Input 3 (\# rising edges) \\\hline\hline
+
+ 0x09 & \texttt{0x25e0fc0f} & Level Counter ITC 0 (\# cycles ITC was asserted) \\\hline
+ 0x0a & \texttt{0x000a00cd} & Edge Counter ITC 0 (\# rising edges) \\\hline
+ 0x0b & \texttt{0x0000000a} & Level Counter ITC 1 (\# cycles ITC was asserted) \\\hline
+ 0x0c & \texttt{0x4af40000} & Edge Counter ITC 1 (\# rising edges) \\\hline
+ \ldots & \ldots & \ldots \\\hline
+ 0x21 & \texttt{0xe96d2bd1} & Level Counter ITC 12 (\# cycles ITC was asserted) \\\hline
+ 0x22 & \texttt{0x00000000} & Edge Counter ITC 12 (\# rising edges) \\\hline
+ 0x23 & \texttt{0xe96d2bd1} & Level Counter ITC 13 (\# cycles ITC was asserted) \\\hline
+ 0x24 & \texttt{0x00000000} & Edge Counter ITC 13 (\# rising edges) \\\hline\hline
+
+ 0x25 & \texttt{0x00018c6a} & 16.2~ms Idle time (\# cycles CTS was idle before trigger was accepted) \\\hline
+ 0x26 & \texttt{0x00000082} & 1.3~$\mu$s Dead time (\# cycles CTS was busy in last event) \\\hline\hline
+
+ 0x27 & \texttt{0x000ba1c8} & Trigger Stats: Number of cycles trigger was asserted \\\hline
+ 0x28 & \texttt{0x000ba1c8} & Trigger Stats: Number of rising edges asserted \\\hline
+ 0x29 & \texttt{0x00005de9} & Trigger Stats: Number of events accepted \\\hline\hline
+
+ 0x2a & \texttt{0x35c3e3e1} & Timestamp \\\hline
+ \multicolumn{3}{c}{End of CTS Data. Remaining words are from External Trigger Logic}\\\hline
+
+ 0x2b & \texttt{0x10000000} & CBM-MBS word (see table \ref{tab:cts_cbm_data_word}) \\\hline
+ \end{tabular}
+
+ \caption{Example of CTS Package. The data in the subsubevent appears in the same order as the
+ properties in the header word}
+ \label{ref:cts_subsubevent_example}
+
+ \end{table}
+
+
+\subsection{Trigger Logic}
\begin{figure}
\centering
\includegraphics[width=\textwidth]{figures/cts_trigger_logic_overview.pdf}
\caption{Interface of \texttt{CTS} entity to connect to external logic}
\label{tab:cts_external_logic}
\end{table}
+
+
\subsubsection{Latency and Jitter}
\label{sec:cts_bb_cts_latency_and_jitter}
instances of the same module, they have to share a block, which can be indicated by the header's length information.
This decision reduces the amount of header words and thus speeds up the enumeration process. It further decreases
the code complexity of the client software.
-
- % TODO: module header table
- % \regtable{cts_trg_header}{Header used to identify an address block within the trigger logic's address range}{Trigger Module Header}
-
+
+ \begin{table}[H]
+ \begin{center}
+ \begin{tabularx}{\textwidth}{|r@{}@{}c@{}@{}l|lX|} \hline
+ \multicolumn{3}{|c|}{\textbf{Bit(s)}} &
+ \multicolumn{2}{c|}{\textbf{Description}} \\\hline\hline
+%
+ &&& \multicolumn{2}{X|}{Block identification header} \\
+ \multicolumn{3}{|c|}{\addr{7:0}} & &{Block type}\\
+ \addr{15} & : & \addr{~8} & &{Number of addresses in this block exclusively this header word}\\
+ \multicolumn{3}{|c|}{\addr{20:16}} & &{First internal trigger channel assigned to this block (0 if it does not apply)}\\
+ \multicolumn{3}{|c|}{\addr{25:21}} & &{Number of internal trigger channel assigned to this block (0 if it does not apply)}\\
+ \multicolumn{3}{|c|}{\addr{31}} & &{Last block indicator. Enumeration stops after reading this block}\\ \hline
+ \end{tabularx}
+ \caption[CTS Trigger Module Header]{Header used to identify an address block within the trigger logic's address range.}
+ \label{tab:cts_trigger_header}
+ \end{center}
+ \end{table}
+
+
+ \begin{table}
+ \begin{center}\small
+ \begin{spacing}{1.1}
+ \begin{tabularx}{\textwidth}{|l|r@{}@{}c@{}@{}l|lX|} \hline
+ \multicolumn{1}{|c|}{\textbf{Address}} &
+ \multicolumn{3}{c|}{\textbf{Bit(s)}} &
+ \multicolumn{2}{c|}{\textbf{Description}} \\\hline\hline
+%
+ \addr{0xa000}
+ & &&& \multicolumn{2}{X|}{Statistics: Number of clock cycles with trigger asserted} \\
+ \hline
+ \addr{0xa001}
+ & &&& \multicolumn{2}{X|}{Statistics: Number of trigger rising edges} \\
+ \hline
+ \addr{0xa002}
+ & &&& \multicolumn{2}{X|}{Statistics: Number of triggers accepted } \\
+ \hline
+ \addr{0xa003}
+ & &&& \multicolumn{2}{X|}{Current trigger status} \\
+ & \addr{15} & : & \addr{~0} & &{Trigger bitmask (before filtering)}\\
+ & \addr{19} & : & \addr{16} & &{Current trigger type}\\
+ & \multicolumn{3}{c|}{\addr{20}} & &{Trigger asserted }\\
+ \hline
+ \addr{0xa004}
+ & &&& \multicolumn{2}{X|}{Buffered trigger status} \\
+ & \addr{15} & : & \addr{~0} & &{Trigger bitmask (before filtering)}\\
+ & \addr{19} & : & \addr{16} & &{Trigger type }\\
+ \hline
+ \addr{0xa005}
+ & &&& \multicolumn{2}{X|}{TD FSM State (Trigger Distribution). One-Hot-Encoding:} \\
+ & \multicolumn{3}{c|}{\addr{0}} & &{TD\_FSM\_IDLE}\\
+ & \multicolumn{3}{c|}{\addr{1}} & &{TD\_FSM\_SEND\_TRIGGER}\\
+ & \multicolumn{3}{c|}{\addr{2}} & &{TD\_FSM\_WAIT\_FEE\_RECV\_TRIGGER}\\
+ & \multicolumn{3}{c|}{\addr{3}} & &{TD\_FSM\_FEE\_ENQUEUE\_INPUT\_COUNTER }\\
+ & \multicolumn{3}{c|}{...} & &\\
+ & \multicolumn{3}{c|}{\addr{12}} & &{TD\_FSM\_WAIT\_TRIGGER\_BECOME\_IDLE}\\
+ & \multicolumn{3}{c|}{\addr{13}} & &{TD\_FSM\_DEBUG\_LIMIT\_REACHED }\\
+ \hline
+ \addr{0xa006}
+ & &&& \multicolumn{2}{X|}{RO FSM State (Readout Handling). One-Hot-Encoding:} \\
+ & \multicolumn{3}{c|}{\addr{0}} & &{RO\_FSM\_IDLE}\\
+ & \multicolumn{3}{c|}{\addr{1}} & &{RO\_FSM\_SEND\_REQUEST}\\
+ & \multicolumn{3}{c|}{\addr{2}} & &{RO\_FSM\_WAIT\_BECOME\_BUSY}\\
+ & \multicolumn{3}{c|}{\addr{3}} & &{RO\_FSM\_WAIT\_BECOME\_IDLE}\\
+ & \multicolumn{3}{c|}{\addr{4}} & &{RO\_FSM\_DEBUG\_LIMIT\_REACHED }\\
+ \hline
+ \addr{0xa007}
+ & &&& \multicolumn{2}{X|}{Readout Queue} \\
+ & \addr{15} & : & \addr{~0} & &{Words enqueued}\\
+ & \multicolumn{3}{c|}{\addr{30}} & &{Empty}\\
+ & \multicolumn{3}{c|}{\addr{31}} & &{Full }\\
+ \hline
+ \addr{0xa008}
+ & &&& \multicolumn{2}{X|}{Debug FSM limits} \\
+ & \addr{15} & : & \addr{~0} & &{Number of Triggers (0xFFFF means no limit)}\\
+ & \addr{31} & : & \addr{16} & &{Number of Read-Outs (0xFFFF means no limit) }\\
+ \hline
+ \addr{0xa009}
+ & &&& \multicolumn{2}{X|}{Trigger information to be send in read-out (default: 0x00000000)} \\
+ & \multicolumn{3}{c|}{\addr{0}} & &{Input Counters}\\
+ & \multicolumn{3}{c|}{\addr{1}} & &{Channel Counters}\\
+ & \multicolumn{3}{c|}{\addr{2}} & &{Statistics: Idle- and Dead-Time counter}\\
+ & \multicolumn{3}{c|}{\addr{3}} & &{Statistics: Trigger asserted, -edges, -accepted}\\
+ & \multicolumn{3}{c|}{\addr{4}} & &{Timestamp }\\
+ \hline
+ \addr{0xa00a}
+ & &&& \multicolumn{2}{X|}{Statistics: Dead time of last trigger} \\
+ \hline
+ \addr{0xa00b}
+ & &&& \multicolumn{2}{X|}{Statistics: Time between last two accepted triggers } \\
+ \hline
+ \addr{0xa00c}
+ & &&& \multicolumn{2}{X|}{Event throttle} \\
+ & \addr{~9} & : & \addr{~0} & &{Maximal number of events accepted per millisecond}\\
+ & \multicolumn{3}{c|}{\addr{10}} & &{Throttle enabled}\\
+ & \multicolumn{3}{c|}{\addr{31}} & &{Stop Trigger}\\ \hline
+ \end{tabularx}
+ \end{spacing}
+ \caption[CTS Register with fixed address]{Registers with fixed addresses, i.e. controlled by the network logic domain}
+ \label{tab:cts_register_block}
+ \end{center}
+ \end{table}
+
+
+
\begin{information}
The following list states block types currently used and roughly describes their structure. If you require detailed
information about single bits, look into the source file of the corresponding driver module placed under
jspc29 / daqdocu.git / commitdiff
