All crashes (3 sofar) of trbnet have been solved with 'trbcmd reset'.
Changes to soda:
- The source now has a tx-fifo (fixed delay) but NO rx-fifo.
- Both sides have a watchdog implemented. It checks 'got_link_ready'. If this is absent the watchdog fires and resets the rx-control fsm.
- Calibration works with: 'trbcmd w 0xf355 0xbe00 0x40000000;trbcmd w 0xf355 0xbe00 0x00000000; trbcmd r 0xf355 0xbe02'
- The client still has an rx-fifo ; this will be next to go.
<Option name="HDL type" value="VHDL"/>
</Options>
<Implementation title="soda_client" dir="soda_client" description="soda_client" default_strategy="Strategy1">
- <Options def_top="trb3_periph_sodaclient" top="trb3_periph_sodaclient"/>
+ <Options top="trb3_periph_sodaclient"/>
<Source name="source/version.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="soda_client_probe.rvl" type="Reveal" type_short="Reveal">
<Options/>
</Source>
- <Source name="source/soda_source_syn_translated.fdc" type="Synplify Design Constraints File" type_short="SDC">
+ <Source name="source/soda_client_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC">
<Options/>
</Source>
<Source name="trb3_soda_client.xcf" type="Programming Project File" type_short="Programming">
-rvl_alias "clk_raw_internal" "clk_raw_internal";
+rvl_alias "reveal_ist_380" "the_sync_link/clk_rx_full";
RVL_ALIAS "reveal_ist_260" "the_sync_link/the_serdes/rx_full_clk_ch0";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
-rvl_alias "clk_raw_internal" "clk_raw_internal";
+rvl_alias "rx_clock_full" "rx_clock_full";
RVL_ALIAS "clk_raw_internal" "clk_raw_internal";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
signal sci_state : sci_ctrl;
signal sci_timer : unsigned(12 downto 0) := (others => '0');
signal start_timer : unsigned(18 downto 0) := (others => '0');
+signal watchdog_timer : unsigned(20 downto 0) := (others => '0');
+signal watchdog_trigger : std_logic :='0';
begin
SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
---rst_n <= not CLEAR; PL!
-rst_n <= not (CLEAR or sd_los_i or internal_make_link_reset_out);
-rst <= (CLEAR or sd_los_i or internal_make_link_reset_out);
+--rst_n <= not CLEAR; PL!\r
+rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
+rst <= (CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
hdinn_ch0 => SD_RXD_N_IN,
hdoutp_ch0 => SD_TXD_P_OUT,
hdoutn_ch0 => SD_TXD_N_OUT,
- rxiclk_ch0 => clk_200_i,
+-- rxiclk_ch0 => clk_200_i, -- read fifo is no longer present! PL!
txiclk_ch0 => clk_200_i,
rx_full_clk_ch0 => clk_rx_full,
rx_half_clk_ch0 => clk_rx_half,
tx_allow_q <= tx_allow when rising_edge(SYSCLK);
-PROC_START_TIMER : process begin
- wait until rising_edge(clk_200_i);
- if got_link_ready_i = '1' then
- if start_timer(start_timer'left) = '0' then
- start_timer <= start_timer + 1;
- end if;
- else
- start_timer <= (others => '0');
- end if;
-end process;
-
+--PROC_START_TIMER : process begin
+ --wait until rising_edge(clk_200_i);
+ --if got_link_ready_i = '1' then
+ --if start_timer(start_timer'left) = '0' then
+ --start_timer <= start_timer + 1;
+ --end if;
+ --else
+ --start_timer <= (others => '0');
+ --end if;
+--end process;
+PROC_START_TIMER : process(clk_200_i)
+begin
+ if rising_edge(clk_200_i) then
+ if got_link_ready_i = '1' then
+ watchdog_timer <= (others => '0');
+ if start_timer(start_timer'left) = '0' then
+ start_timer <= start_timer + 1;
+ end if;
+ else
+ start_timer <= (others => '0');
+ if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 1) = '1')) then
+ watchdog_trigger <= '1';
+ else
+ watchdog_trigger <= '0';
+ end if;
+ if watchdog_trigger = '0' then
+ watchdog_timer <= watchdog_timer + 1;
+ else
+ watchdog_timer <= (others => '0');
+ end if;
+ end if;
+ end if;
+end process;
-------------------------------------------------
-- TX Data
-------------------------------------------------
signal sci_state : sci_ctrl;
signal sci_timer : unsigned(12 downto 0) := (others => '0');
signal start_timer : unsigned(18 downto 0) := (others => '0');
+signal watchdog_timer : unsigned(20 downto 0) := (others => '0');
+signal watchdog_trigger : std_logic :='0';
begin
--rst_n <= not CLEAR; PL!
-rst_n <= not (CLEAR or sd_los_i or internal_make_link_reset_out);
-rst <= (CLEAR or sd_los_i or internal_make_link_reset_out);
+rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
+rst <= (CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
tx_allow_q <= tx_allow when rising_edge(SYSCLK);
-PROC_START_TIMER : process begin
- wait until rising_edge(clk_200_i);
- if got_link_ready_i = '1' then
- if start_timer(start_timer'left) = '0' then
- start_timer <= start_timer + 1;
- end if;
- else
- start_timer <= (others => '0');
- end if;
+PROC_START_TIMER : process(clk_200_i)\r
+begin\r
+ if rising_edge(clk_200_i) then
+ if got_link_ready_i = '1' then\r
+ watchdog_timer <= (others => '0');
+ if start_timer(start_timer'left) = '0' then
+ start_timer <= start_timer + 1;
+ end if;
+ else
+ start_timer <= (others => '0');\r
+ if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 2) = '1')) then\r
+ watchdog_trigger <= '1';\r
+ else
+ watchdog_trigger <= '0';\r
+ end if;
+ if watchdog_trigger = '0' then\r
+ watchdog_timer <= watchdog_timer + 1;\r
+ else \r
+ watchdog_timer <= (others => '0');
+ end if;\r
+ end if;\r
+ end if;
end process;
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_downstream" module="serdes_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 12 23 10:40:50.024" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_downstream" module="serdes_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 01 16 15:03:46.952" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_sync_downstream.lpc" type="lpc" modified="2013 12 23 10:40:48.000"/>
- <File name="serdes_sync_downstream.pp" type="pp" modified="2013 12 23 10:40:48.000"/>
- <File name="serdes_sync_downstream.sym" type="sym" modified="2013 12 23 10:40:48.000"/>
- <File name="serdes_sync_downstream.tft" type="tft" modified="2013 12 23 10:40:48.000"/>
- <File name="serdes_sync_downstream.txt" type="pcs_module" modified="2013 12 23 10:40:48.000"/>
- <File name="serdes_sync_downstream.vhd" type="top_level_vhdl" modified="2013 12 23 10:40:48.000"/>
+ <File name="serdes_sync_downstream.lpc" type="lpc" modified="2014 01 16 15:03:44.000"/>
+ <File name="serdes_sync_downstream.pp" type="pp" modified="2014 01 16 15:03:44.000"/>
+ <File name="serdes_sync_downstream.sym" type="sym" modified="2014 01 16 15:03:44.000"/>
+ <File name="serdes_sync_downstream.tft" type="tft" modified="2014 01 16 15:02:59.000"/>
+ <File name="serdes_sync_downstream.txt" type="pcs_module" modified="2014 01 16 15:03:44.000"/>
+ <File name="serdes_sync_downstream.vhd" type="top_level_vhdl" modified="2014 01 16 15:02:59.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_sync_downstream
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=12/23/2013
-Time=10:40:48
+Date=01/16/2014
+Time=15:03:44
[Parameters]
Verilog=0
_rx_data_width1=8
_rx_data_width2=8
_rx_data_width3=8
-_rx_fifo0=ENABLED
+_rx_fifo0=DISABLED
_rx_fifo1=ENABLED
_rx_fifo2=ENABLED
_rx_fifo3=ENABLED
CH0_TX_DATA_WIDTH "8"
CH0_RX_DATA_WIDTH "8"
CH0_TX_FIFO "ENABLED"
-CH0_RX_FIFO "ENABLED"
+CH0_RX_FIFO "DISABLED"
CH0_TDRV "0"
#CH0_TX_FICLK_RATE 200
#CH0_RXREFCLK_RATE "200"
hdinp_ch0, hdinn_ch0 : in std_logic;
hdoutp_ch0, hdoutn_ch0 : out std_logic;
sci_sel_ch0 : in std_logic;
- rxiclk_ch0 : in std_logic;
txiclk_ch0 : in std_logic;
rx_full_clk_ch0 : out std_logic;
rx_half_clk_ch0 : out std_logic;
PCIE_PHYSTATUS_0 => open,
SCISELCH0 => sci_sel_ch0,
SCIENCH0 => fpsc_vhi,
- FF_RXI_CLK_0 => rxiclk_ch0,
+ FF_RXI_CLK_0 => fpsc_vlo,
FF_TXI_CLK_0 => txiclk_ch0,
FF_EBRD_CLK_0 => fpsc_vlo,
FF_RX_F_CLK_0 => rx_full_clk_ch0,
RX_DLM_IN : in std_logic;
TX_DLM_OUT : out std_logic;
TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ TX_DLM_PREVIEW_OUT : out std_logic := '0'; --PL!
+ LINK_PHASE_IN : in std_logic := '0'; --PL!
SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0');
CLEAR => '0',
CLK_EN => CLK_EN,
--Internal Connection
+ LINK_PHASE_IN => LINK_PHASE_IN,\r
START_OF_SUPERBURST => start_of_superburst_S,
SUPER_BURST_NR_IN => super_burst_nr_S,
SODA_CMD_STROBE_IN => soda_cmd_valid_S,
SODA_CMD_WORD_IN => soda_cmd_word_S,
+ TX_DLM_PREVIEW_OUT => TX_DLM_PREVIEW_OUT,
TX_DLM_OUT => tx_dlm_out_S, --TX_DLM_OUT,
TX_DLM_WORD_OUT => TX_DLM_WORD_OUT
);
RX_DLM_IN : in std_logic;
TX_DLM_OUT : out std_logic;
TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ TX_DLM_PREVIEW_OUT : out std_logic := '0'; --PL!
+ LINK_PHASE_IN : in std_logic := '0'; --PL!
SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0');
SODACLK : in std_logic; -- fabric clock\r
RESET : in std_logic; -- synchronous reset\r
CLEAR : in std_logic; -- asynchronous reset\r
- CLK_EN : in std_logic; \r
+ CLK_EN : in std_logic;\r
--Internal Connection\r
+ LINK_PHASE_IN : in std_logic := '0'; --_vector(1 downto 0) := (others => '0');
START_OF_SUPERBURST : in std_logic := '0';\r
SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0');\r
SODA_CMD_STROBE_IN : in std_logic := '0'; -- \r
SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit\r
+ TX_DLM_PREVIEW_OUT : out std_logic := '0';
TX_DLM_OUT : out std_logic := '0'; --
TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0')\r
);\r
signal packet_state_S : packet_state_type := c_IDLE;\r
\r
signal soda_dlm_preview_S : std_logic;
- signal soda_cmd_reg_full_S : std_logic;
- signal soda_cmd_reg_S : std_logic_vector(31 downto 0) := (others => '0'); -- from super-burst-nr-generator
+-- signal soda_cmd_reg_full_S : std_logic;
+-- signal soda_cmd_reg_S : std_logic_vector(31 downto 0) := (others => '0'); -- from super-burst-nr-generator
\r
begin\r
\r
packet_state_S <= c_CMD2;\r
soda_dlm_preview_S <= '1';
soda_pkt_valid_S <= '0';
+ TIME_CAL_OUT <= soda_cmd_word_S(30);
when c_CMD2 =>\r
packet_state_S <= c_CMD3;\r
soda_pkt_valid_S <= '1';
soda_pkt_word_S <= soda_cmd_word_S(23 downto 16);
+ TIME_CAL_OUT <= '0';
when c_CMD3 =>\r
packet_state_S <= c_CMD4;\r
soda_pkt_valid_S <= '0';
\r
entity soda_reply_pkt_builder is\r
port(\r
- SODACLK : in std_logic; -- fabric clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset\r
- CLK_EN : in std_logic; \r
+ SODACLK : in std_logic; -- fabric clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset\r
+ CLK_EN : in std_logic; \r
--Internal Connection\r
- START_OF_SUPERBURST : in std_logic := '0';\r
- SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0');\r
- SODA_CMD_STROBE_IN : in std_logic := '0'; -- \r
- SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit\r
- TX_DLM_OUT : out std_logic := '0'; --
- TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0')\r
+ LINK_PHASE_IN : in std_logic := '0'; --_vector(1 downto 0) := (others => '0');
+ START_OF_SUPERBURST : in std_logic := '0';\r
+ SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0');\r
+ SODA_CMD_STROBE_IN : in std_logic := '0'; -- \r
+ SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit\r
+ TX_DLM_PREVIEW_OUT : out std_logic := '0'; --
+ TX_DLM_OUT : out std_logic := '0'; --
+ TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0')\r
);\r
end soda_reply_pkt_builder;\r
\r
architecture Behavioral of soda_reply_pkt_builder is\r
- type packet_state_type is ( c_IDLE, c_PKT1, c_PKT2 );\r
+ type packet_state_type is ( c_IDLE, c_ERROR,
+ c_WAIT4BST1, c_BST1, c_BST2, c_BST3, c_BST4, c_BST5, c_BST6, c_BST7, c_BST8,
+ c_WAIT4CMD1, c_CMD1, c_CMD2, c_CMD3, c_CMD4, c_CMD5, c_CMD6, c_CMD7, c_CMD8
+ );
signal packet_state_S : packet_state_type := c_IDLE;\r
\r
+signal soda_dlm_preview_S : std_logic;
+\r
begin\r
- reply_fsm_proc : process(SODACLK)
+ TX_DLM_PREVIEW_OUT <= '1' when (((LINK_PHASE_IN='1') and ((soda_dlm_preview_S='1') or (START_OF_SUPERBURST='1') or (SODA_CMD_STROBE_IN='1'))) or
+ ((LINK_PHASE_IN='0') and (soda_dlm_preview_S='1')))
+ else '0';
+\r
+reply_fsm_proc : process(SODACLK)
begin
- if rising_edge(SODACLK) then\r
+ if rising_edge(SODACLK) then
if (RESET='1') then
- packet_state_S <= c_IDLE;
+ packet_state_S <= c_IDLE;
+ soda_dlm_preview_S <= '0';
+ TX_DLM_OUT <= '0';
+ TX_DLM_WORD_OUT <= (others=>'0');
else
- case packet_state_S is\r
- when c_IDLE =>\r
- if (START_OF_SUPERBURST='1') or (SODA_CMD_STROBE_IN='1') then\r
- packet_state_S <= c_PKT1;\r
+ case packet_state_S is
+ when c_IDLE =>
+ if (START_OF_SUPERBURST='1') then
+ soda_dlm_preview_S <= '1';
+ if (LINK_PHASE_IN = c_PHASE_H) then
+ packet_state_S <= c_BST1;
+ TX_DLM_OUT <= '1';
+ TX_DLM_WORD_OUT <= SUPER_BURST_NR_IN(7 downto 0);
+ else
+ packet_state_S <= c_WAIT4BST1;
+ TX_DLM_OUT <= '0';
+ end if;
+ elsif (SODA_CMD_STROBE_IN='1') then
+ soda_dlm_preview_S <= '1';
+ if (LINK_PHASE_IN = c_PHASE_H) then
+ packet_state_S <= c_CMD1;
+ TX_DLM_OUT <= '1';
+ TX_DLM_WORD_OUT <= SODA_CMD_WORD_IN(7 downto 0);
+ else
+ packet_state_S <= c_WAIT4CMD1;
+ TX_DLM_OUT <= '0';\r
+ end if;
end if;
- when c_PKT1 =>
- packet_state_S <= c_PKT2;\r
- when c_PKT2 =>
- packet_state_S <= c_IDLE;\r
+ when c_WAIT4BST1 =>
+ packet_state_S <= c_BST1;
+ soda_dlm_preview_S <= '1';
+ TX_DLM_OUT <= '1';
+ TX_DLM_WORD_OUT <= '1' & SUPER_BURST_NR_IN(30 downto 24);
+ when c_BST1 =>
+ packet_state_S <= c_BST2;
+ TX_DLM_OUT <= '0';
+ soda_dlm_preview_S <= '0';
+ when c_BST2 =>
+ packet_state_S <= c_IDLE;
+ when c_WAIT4CMD1 =>
+ packet_state_S <= c_CMD1;
+ soda_dlm_preview_S <= '1';
+ TX_DLM_OUT <= '1';
+ TX_DLM_WORD_OUT <= '1' & SODA_CMD_WORD_IN(30 downto 24);
+ when c_CMD1 =>
+ packet_state_S <= c_CMD2;
+ TX_DLM_OUT <= '0';
+ soda_dlm_preview_S <= '0';
+ when c_CMD2 =>
+ packet_state_S <= c_IDLE;
when others =>
- packet_state_S <= c_IDLE;
+ packet_state_S <= c_IDLE;
+ TX_DLM_OUT <= '0';
+ soda_dlm_preview_S <= '0';
end case;
- end if;\r
+ end if;
end if;
end process;
+\r
+--reply_fsm_proc : process(SODACLK)
+-- begin
+-- if rising_edge(SODACLK) then\r
+-- if (RESET='1') then
+-- packet_state_S <= c_IDLE;
+-- else
+-- case packet_state_S is\r
+-- when c_IDLE =>\r
+-- if (START_OF_SUPERBURST='1') or (SODA_CMD_STROBE_IN='1') then\r
+-- packet_state_S <= c_PKT1;\r
+-- end if;
+-- when c_PKT1 =>
+-- packet_state_S <= c_PKT2;\r
+-- when c_PKT2 =>
+-- packet_state_S <= c_IDLE;\r
+-- when others =>
+-- packet_state_S <= c_IDLE;
+-- end case;
+-- end if;\r
+-- end if;
+-- end process;
- collect_reply_proc : process(SODACLK)
- begin
- if rising_edge(SODACLK) then\r
- if (RESET='1') then
- TX_DLM_OUT <= '0';\r
- TX_DLM_WORD_OUT <= (others=>'0');
- elsif (START_OF_SUPERBURST='1') then\r
- TX_DLM_OUT <= '1';\r
- TX_DLM_WORD_OUT <= SUPER_BURST_NR_IN(7 downto 0);\r
- elsif (SODA_CMD_STROBE_IN='1') then\r
- TX_DLM_OUT <= '1';\r
- TX_DLM_WORD_OUT <= SODA_CMD_WORD_IN(7 downto 0);
- elsif (packet_state_S=c_PKT1) then
- TX_DLM_OUT <= '0';\r
- elsif (packet_state_S=c_PKT2) then
- TX_DLM_WORD_OUT <= (others=>'0');
- end if;\r
- end if;
- end process;
+-- collect_reply_proc : process(SODACLK)
+-- begin
+-- if rising_edge(SODACLK) then\r
+-- if (RESET='1') then
+-- TX_DLM_OUT <= '0';\r
+-- TX_DLM_WORD_OUT <= (others=>'0');
+-- elsif (START_OF_SUPERBURST='1') then\r
+-- TX_DLM_OUT <= '1';\r
+-- TX_DLM_WORD_OUT <= SUPER_BURST_NR_IN(7 downto 0);\r
+-- elsif (SODA_CMD_STROBE_IN='1') then\r
+-- TX_DLM_OUT <= '1';\r
+-- TX_DLM_WORD_OUT <= SODA_CMD_WORD_IN(7 downto 0);
+-- elsif (packet_state_S=c_PKT1) then
+-- TX_DLM_OUT <= '0';\r
+-- elsif (packet_state_S=c_PKT2) then
+-- TX_DLM_WORD_OUT <= (others=>'0');
+-- end if;\r
+-- end if;
+-- end process;
\r
\r
end architecture;
\ No newline at end of file
signal tx_dlm_word : std_logic_vector(7 downto 0);
signal rx_dlm_word : std_logic_vector(7 downto 0);
signal make_reset : std_logic;
+ signal tx_dlm_preview_S : std_logic; --PL!
+ signal link_phase_S : std_logic; --PL!
-- SODA slow controll
signal soda_ack : std_logic;
---------------------------------------------------------------------------
THE_SYNC_LINK : med_ecp3_sfp_sync_up
- generic map(
- SERDES_NUM => 0, --number of serdes in quad
- IS_SYNC_SLAVE => c_YES
- )
- port map(
- CLK => clk_raw_internal, --clk_200_i,
- SYSCLK => clk_sys_internal, --clk_sys_i,
- RESET => reset_i,
- CLEAR => clear_i,
- --Internal Connection for TrbNet data -> not used a.t.m.
- MED_DATA_IN => med_data_out(15 downto 0),
- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
- MED_DATAREADY_IN => med_dataready_out(0),
- MED_READ_OUT => med_read_in(0),
- MED_DATA_OUT => med_data_in(15 downto 0),
- MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
- MED_DATAREADY_OUT => med_dataready_in(0),
- MED_READ_IN => med_read_out(0),
- CLK_RX_HALF_OUT => soda_rx_clock_half,
- CLK_RX_FULL_OUT => soda_rx_clock_full,
-
- RX_DLM => rx_dlm_i,
- RX_DLM_WORD => rx_dlm_word,
- TX_DLM => tx_dlm_i,
- TX_DLM_WORD => tx_dlm_word,
- --SFP Connection
- SD_RXD_P_IN => SERDES_ADDON_RX(0),
- SD_RXD_N_IN => SERDES_ADDON_RX(1),
- SD_TXD_P_OUT => SERDES_ADDON_TX(0),
- SD_TXD_N_OUT => SERDES_ADDON_TX(1),
- SD_REFCLK_P_IN => '0',
- SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => SFP_MOD0(1),
- SD_LOS_IN => SFP_LOS(1),
- SD_TXDIS_OUT => SFP_TXDIS(1),
-
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
- SCI_NACK => sci1_nack,
- -- Status and control port
- STAT_OP => med_stat_op(15 downto 0),
- CTRL_OP => med_ctrl_op(15 downto 0),
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
- );
+ generic map(
+ SERDES_NUM => 0, --number of serdes in quad
+ IS_SYNC_SLAVE => c_YES
+ )
+ port map(
+ CLK => clk_raw_internal, --clk_200_i,
+ SYSCLK => clk_sys_internal, --clk_sys_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ --Internal Connection for TrbNet data -> not used a.t.m.
+ MED_DATA_IN => med_data_out(15 downto 0),
+ MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
+ MED_DATAREADY_IN => med_dataready_out(0),
+ MED_READ_OUT => med_read_in(0),
+ MED_DATA_OUT => med_data_in(15 downto 0),
+ MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
+ MED_DATAREADY_OUT => med_dataready_in(0),
+ MED_READ_IN => med_read_out(0),
+ CLK_RX_HALF_OUT => soda_rx_clock_half,
+ CLK_RX_FULL_OUT => soda_rx_clock_full,
+
+ RX_DLM => rx_dlm_i,
+ RX_DLM_WORD => rx_dlm_word,
+ TX_DLM => tx_dlm_i,
+ TX_DLM_WORD => tx_dlm_word,
+ TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL!
+ LINK_PHASE_OUT => link_phase_S, --PL!
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_ADDON_RX(0),
+ SD_RXD_N_IN => SERDES_ADDON_RX(1),
+ SD_TXD_P_OUT => SERDES_ADDON_TX(0),
+ SD_TXD_N_OUT => SERDES_ADDON_TX(1),
+ SD_REFCLK_P_IN => '0',
+ SD_REFCLK_N_IN => '0',
+ SD_PRSNT_N_IN => SFP_MOD0(1),
+ SD_LOS_IN => SFP_LOS(1),
+ SD_TXDIS_OUT => SFP_TXDIS(1),
+
+ SCI_DATA_IN => sci1_data_in,
+ SCI_DATA_OUT => sci1_data_out,
+ SCI_ADDR => sci1_addr,
+ SCI_READ => sci1_read,
+ SCI_WRITE => sci1_write,
+ SCI_ACK => sci1_ack,
+ SCI_NACK => sci1_nack,
+ -- Status and control port
+ STAT_OP => med_stat_op(15 downto 0),
+ CTRL_OP => med_ctrl_op(15 downto 0),
+ STAT_DEBUG => open,
+ CTRL_DEBUG => (others => '0')
+ );
---------------------------------------------------------------------------
RX_DLM_IN => rx_dlm_i,
TX_DLM_OUT => tx_dlm_i,
TX_DLM_WORD_OUT => tx_dlm_word,
-\r
+ TX_DLM_PREVIEW_OUT => tx_dlm_preview_S,
+ LINK_PHASE_IN => link_phase_S,
SODA_DATA_IN => soda_data_in,
SODA_DATA_OUT => soda_data_out,
SODA_ADDR_IN => soda_addr,
jspc29 / soda.git / commitdiff