updating files

diff --git a/.gitignore b/.gitignore
index 3e097d771d80e88f6a25763cb1c9acb2d691c012..c04e6af2d6176bd3d8d283d7ea3c62dd66fb5114 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -6,3 +6,4 @@ __Previews
 History
 old
 *htm
+*zip

diff --git a/Lib/CB2013.PcbLib b/Lib/CB2013.PcbLib
index 7e0223bda71652447d92d434a7ce4818ee953fc3..a639d9e83dbe05d72b97e00001035615a34f3f1a 100755 (executable)
Binary files a/Lib/CB2013.PcbLib and b/Lib/CB2013.PcbLib differ

diff --git a/Lib/CB2013.SCHLIB b/Lib/CB2013.SCHLIB
index 807bc629d972ae6110afb6974ffaf283d748d71a..4a24feabed0dad8616ec1f3382025b5007327427 100755 (executable)
Binary files a/Lib/CB2013.SCHLIB and b/Lib/CB2013.SCHLIB differ

diff --git a/Pulser/FPGA.SchDoc b/Pulser/FPGA.SchDoc
index 93dcf73b26e4a233b7b5d91fea0a7f53d4b4f0d6..98aa0cdc87551b222dce353f286b27a7e9bfb566 100755 (executable)
Binary files a/Pulser/FPGA.SchDoc and b/Pulser/FPGA.SchDoc differ

diff --git a/Pulser/FPGA2.SchDoc b/Pulser/FPGA2.SchDoc
index 6fe534c6ba6fb3ca3db7c58d266719c27e21fe72..c4234057eece2e657092bebe3f73af2d2d22a230 100755 (executable)
Binary files a/Pulser/FPGA2.SchDoc and b/Pulser/FPGA2.SchDoc differ

diff --git a/Pulser/Main.SchDoc b/Pulser/Main.SchDoc
index 4658b9a68f1cf4342745c9ef2c87b01f1e9ee550..21f40d911f4e86fe2a008826b5834340b73218e6 100755 (executable)
Binary files a/Pulser/Main.SchDoc and b/Pulser/Main.SchDoc differ

diff --git a/Pulser/Power.SchDoc b/Pulser/Power.SchDoc
index 84b05333bf024565db5ed59fca5a46390d042f3a..c5cf3e0c8039433e44fb093095f7c42b4d11e52d 100755 (executable)
Binary files a/Pulser/Power.SchDoc and b/Pulser/Power.SchDoc differ

diff --git a/Pulser/Pulser.PrjPcb b/Pulser/Pulser.PrjPcb
index 5ede6854d3c468be0cecf376383038cf440c9a9f..df3d057bb7cb127af1c87ed164440063356260f7 100755 (executable)
--- a/Pulser/Pulser.PrjPcb
+++ b/Pulser/Pulser.PrjPcb
@@ -54,7 +54,7 @@ AnnotateStartValue=1
 AnnotationIndexControlEnabled=0\r
 AnnotateSuffix=\r
 AnnotateScope=All\r
-AnnotateOrder=-1\r
+AnnotateOrder=5\r
 DoLibraryUpdate=1\r
 DoDatabaseUpdate=1\r
 ClassGenCCAutoEnabled=1\r
@@ -70,7 +70,7 @@ AnnotateStartValue=1
 AnnotationIndexControlEnabled=0\r
 AnnotateSuffix=\r
 AnnotateScope=All\r
-AnnotateOrder=-1\r
+AnnotateOrder=3\r
 DoLibraryUpdate=1\r
 DoDatabaseUpdate=1\r
 ClassGenCCAutoEnabled=1\r
@@ -102,7 +102,7 @@ AnnotateStartValue=1
 AnnotationIndexControlEnabled=0\r
 AnnotateSuffix=\r
 AnnotateScope=All\r
-AnnotateOrder=-1\r
+AnnotateOrder=1\r
 DoLibraryUpdate=1\r
 DoDatabaseUpdate=1\r
 ClassGenCCAutoEnabled=1\r
@@ -118,7 +118,7 @@ AnnotateStartValue=1
 AnnotationIndexControlEnabled=0\r
 AnnotateSuffix=\r
 AnnotateScope=All\r
-AnnotateOrder=-1\r
+AnnotateOrder=0\r
 DoLibraryUpdate=1\r
 DoDatabaseUpdate=1\r
 ClassGenCCAutoEnabled=1\r
@@ -134,6 +134,38 @@ AnnotateStartValue=1
 AnnotationIndexControlEnabled=0\r
 AnnotateSuffix=\r
 AnnotateScope=All\r
+AnnotateOrder=4\r
+DoLibraryUpdate=1\r
+DoDatabaseUpdate=1\r
+ClassGenCCAutoEnabled=1\r
+ClassGenCCAutoRoomEnabled=1\r
+ClassGenNCAutoScope=None\r
+DItemRevisionGUID=\r
+GenerateClassCluster=0\r
+\r
+[Document8]\r
+DocumentPath=FPGA_HS.SchDoc\r
+AnnotationEnabled=1\r
+AnnotateStartValue=1\r
+AnnotationIndexControlEnabled=0\r
+AnnotateSuffix=\r
+AnnotateScope=All\r
+AnnotateOrder=2\r
+DoLibraryUpdate=1\r
+DoDatabaseUpdate=1\r
+ClassGenCCAutoEnabled=1\r
+ClassGenCCAutoRoomEnabled=1\r
+ClassGenNCAutoScope=None\r
+DItemRevisionGUID=\r
+GenerateClassCluster=0\r
+\r
+[Document9]\r
+DocumentPath=Pulser.Annotation\r
+AnnotationEnabled=1\r
+AnnotateStartValue=1\r
+AnnotationIndexControlEnabled=0\r
+AnnotateSuffix=\r
+AnnotateScope=All\r
 AnnotateOrder=-1\r
 DoLibraryUpdate=1\r
 DoDatabaseUpdate=1\r
@@ -998,8 +1030,8 @@ Type100=2
 \r
 [ERC Connection Matrix]\r
 L1=NNNNNNNNNNNWNNNWW\r
-L2=NNWNNNNWWWNWNWNWN\r
-L3=NWEENEEEENEWNEEWN\r
+L2=NNNNNNNWWWNWNWNWN\r
+L3=NNEENEEEENEWNEEWN\r
 L4=NNENNNWEENNWNENWN\r
 L5=NNNNNNNNNNNNNNNNN\r
 L6=NNENNNNEENNWNENWN\r
@@ -1025,6 +1057,54 @@ MatchStrictly2=1
 PhysicalNamingFormat=$Component_$RoomName\r
 GlobalIndexSortOrder=3\r
 GlobalIndexSortLocation=0\r
+UniqueIDPath0=\r
+DocumentName0=FPGA2.SchDoc\r
+IsEnabled0=1\r
+SelectionScope0=All\r
+Order0=1\r
+IndexEnabled0=0\r
+IndexStartValue0=1\r
+Suffix0=\r
+UniqueIDPath1=\r
+DocumentName1=FPGA.SchDoc\r
+IsEnabled1=1\r
+SelectionScope1=All\r
+Order1=2\r
+IndexEnabled1=0\r
+IndexStartValue1=1\r
+Suffix1=\r
+UniqueIDPath2=\r
+DocumentName2=FPGA_HS.SchDoc\r
+IsEnabled2=1\r
+SelectionScope2=All\r
+Order2=3\r
+IndexEnabled2=0\r
+IndexStartValue2=1\r
+Suffix2=\r
+UniqueIDPath3=\r
+DocumentName3=Main.SchDoc\r
+IsEnabled3=1\r
+SelectionScope3=All\r
+Order3=4\r
+IndexEnabled3=0\r
+IndexStartValue3=1\r
+Suffix3=\r
+UniqueIDPath4=\r
+DocumentName4=Power.SchDoc\r
+IsEnabled4=1\r
+SelectionScope4=All\r
+Order4=5\r
+IndexEnabled4=0\r
+IndexStartValue4=1\r
+Suffix4=\r
+UniqueIDPath5=\r
+DocumentName5=USB2.SchDoc\r
+IsEnabled5=1\r
+SelectionScope5=All\r
+Order5=6\r
+IndexEnabled5=0\r
+IndexStartValue5=1\r
+Suffix5=\r
 \r
 [PrjClassGen]\r
 CompClassManualEnabled=0\r