add external slow control bus (flashsettings, debuguart) to streaming hub

diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd
index 67b0438475e21f8164a74b7d46d8fe52fc048157..e93ea4a4a0f592c722d7798d61ee7bd7fbdfbfcc 100644 (file)
--- a/trb_net16_hub_base.vhd
+++ b/trb_net16_hub_base.vhd
@@ -1153,6 +1153,7 @@ end generate;
   BUS_MASTER_IN.ack     <= DAT_DATAREADY_IN or DAT_WRITE_ACK_IN;
   BUS_MASTER_IN.nack    <= DAT_NO_MORE_DATA_IN;
   BUS_MASTER_IN.unknown <= DAT_UNKNOWN_ADDR_IN;
+  BUS_MASTER_IN.data    <= DAT_DATA_IN;
   
   
 --Fucking Modelsim wants it like this...

diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd
index fe8ffd57eced3c11be2980e97a72a1174c19e015..4c533b42167434717aa51a2d15bf76347474318f 100644 (file)
--- a/trb_net16_hub_func.vhd
+++ b/trb_net16_hub_func.vhd
@@ -626,6 +626,10 @@ component trb_net16_hub_streaming_port_sctrl_cts is
     ONEWIRE_MONITOR_OUT            : out std_logic;
     MY_ADDRESS_OUT                 : out std_logic_vector (15 downto 0);
     UNIQUE_ID_OUT                  : out std_logic_vector (63 downto 0);
+    --Data port - external master (e.g. Flash or Debug)
+    BUS_MASTER_IN                  : out CTRLBUS_TX;
+    BUS_MASTER_OUT                 : in  CTRLBUS_RX := (data => (others => '0'), addr => (others => '0'), write => '0', read => '0', timeout => '0');
+    BUS_MASTER_ACTIVE              : in  std_logic := '0';
     --REGIO INTERFACE  (0x8000 - 0xFFFF)
     REGIO_ADDR_OUT                 : out std_logic_vector (16-1 downto 0);
     REGIO_READ_ENABLE_OUT          : out std_logic;

diff --git a/trb_net16_hub_streaming_port_sctrl_cts.vhd b/trb_net16_hub_streaming_port_sctrl_cts.vhd
index cee3c83e146f450461bdaf2d2520d8deb8157f6c..4a6a64138607deb843f1573aab4b4761401530d2 100644 (file)
--- a/trb_net16_hub_streaming_port_sctrl_cts.vhd
+++ b/trb_net16_hub_streaming_port_sctrl_cts.vhd
@@ -173,6 +173,10 @@ entity trb_net16_hub_streaming_port_sctrl_cts is
     ONEWIRE_MONITOR_OUT            : out std_logic;
     MY_ADDRESS_OUT                 : out std_logic_vector (15 downto 0);
     UNIQUE_ID_OUT                  : out std_logic_vector (63 downto 0);
+    --Data port - external master (e.g. Flash or Debug)
+    BUS_MASTER_IN                  : out CTRLBUS_TX;
+    BUS_MASTER_OUT                 : in  CTRLBUS_RX := (data => (others => '0'), addr => (others => '0'), write => '0', read => '0', timeout => '0');
+    BUS_MASTER_ACTIVE              : in  std_logic := '0';
     --REGIO INTERFACE  (0x8000 - 0xFFFF)
     REGIO_ADDR_OUT                 : out std_logic_vector (16-1 downto 0);
     REGIO_READ_ENABLE_OUT          : out std_logic;
@@ -517,6 +521,9 @@ info_tx_ack_or_info_tx_wack <= info_tx.ack or info_tx.wack;
       ONEWIRE_MONITOR_OUT=> ONEWIRE_MONITOR_OUT,
       MY_ADDRESS_OUT     => my_address,
       UNIQUE_ID_OUT      => UNIQUE_ID_OUT,
+      BUS_MASTER_IN             => BUS_MASTER_IN,
+      BUS_MASTER_OUT            => BUS_MASTER_OUT,
+      BUS_MASTER_ACTIVE         => BUS_MASTER_ACTIVE,      
       COMMON_CTRL_REGS   => common_ctrl,
       COMMON_STAT_REGS   => common_stat,
       COMMON_CTRL_REG_STROBE => common_ctrl_strobe,