-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-\r
-library machxo3lf;\r
-use machxo3lf.all;\r
-\r
-library work;\r
-use work.all;--trb_net_std.all;\r
-\r
-entity logicbox is\r
- port(\r
- CLK : in std_logic;\r
- \r
- INPUT : in std_logic_vector(3 downto 0);\r
- OUTPUT : out std_logic_vector(3 downto 0);\r
- \r
- LED : inout std_logic_vector(3 downto 0);\r
- \r
- STATUSI : in std_logic;\r
- STATUSO : in std_logic;\r
- CONTROLI : out std_logic;\r
- CONTROLO : out std_logic;\r
- \r
- RX_OUT : out std_logic;\r
- TX_IN : in std_logic;\r
- CBUS : in std_logic\r
- );\r
-end entity;\r
-\r
-architecture arch of logicbox is\r
- signal clk_i, clk_osc, clk_33,clk_266 : std_logic;\r
- signal led_i : std_logic_vector(3 downto 0);\r
- signal timer_i : unsigned(31 downto 0) := (others => '0');\r
- signal config : std_logic_vector(3 downto 0);\r
- signal led_highz : std_logic;\r
- \r
- type led_timer_t is array(0 to 3) of unsigned(24 downto 0);\r
- signal led_timer : led_timer_t;\r
- signal led_state : std_logic_vector(3 downto 0);\r
- \r
- --UART\r
- -------------------------------------\r
- signal uart_data_out : std_logic_vector(31 downto 0);\r
- signal uart_data_in : std_logic_vector(31 downto 0);\r
- signal uart_addr_out : std_logic_vector(7 downto 0);\r
- signal uart_read_out : std_logic := '0';\r
- signal uart_write_out : std_logic := '0';\r
- signal uart_ready_in : std_logic;\r
- signal uart_busy_out : std_logic;\r
- \r
- signal uart_rx_data : std_logic_vector(31 downto 0);\r
- signal uart_tx_data : std_logic_vector(31 downto 0);\r
- signal uart_addr : std_logic_vector(7 downto 0);\r
- signal bus_read : std_logic := '0';\r
- signal bus_write : std_logic := '0';\r
- signal bus_ready : std_logic; \r
- signal bus_busy : std_logic;\r
- \r
- signal input_i : std_logic_vector(3 downto 0);\r
- signal input_selected : std_logic_vector(3 downto 0); \r
- signal input_stretched, input_hold : std_logic_vector(3 downto 0);\r
- signal input_reg_0, input_reg_1, input_reg_2 : std_logic_vector(3 downto 0);\r
- \r
- signal edge_rising, edge_falling : std_logic_vector(3 downto 0);\r
- signal reg : std_logic_vector(31 downto 0);\r
- signal last_config : std_logic_vector(3 downto 0);\r
- \r
- signal sed_error : std_logic;\r
- signal sed_debug : std_logic_vector(31 downto 0);\r
- signal controlsed_i : std_logic_vector(3 downto 0);\r
- signal testreg1, testreg2 : std_logic_vector(31 downto 0);\r
- \r
- \r
- --PULSER\r
- ------------------------------------- \r
- signal pulser : std_logic;\r
- signal pulser_counter : unsigned(27 downto 0) := (others => '0');\r
- signal pulser_periodlength : unsigned(27 downto 0) := x"0000002";\r
- signal pulser_pulslength : unsigned(27 downto 0) := x"0000001";\r
- signal pulser_periodlength_buffer : unsigned(27 downto 0);\r
- signal pulser_pulslength_buffer : unsigned(27 downto 0);\r
-\r
- --UFM\r
- -------------------------------------\r
- --signal ufm_cmd : std_logic := '0'; --CMD=0 => Read; CMD=1 => Write\r
- --signal ufm_go : std_logic := '1'; --load default values to registers from UFM at startup \r
- --signal ufm_data_in : std_logic_vector(7 downto 0); --directly connected to flashram DataInA\r
- --signal ufm_data_out : std_logic_vector(7 downto 0); --directly connected to flashram QB\r
- --signal ufm_databyte_counter : unsigned(14 downto 0);\r
- --signal ufm_bus_ready_out : std_logic;\r
- --signal ufm_bus_ready_in : std_logic;\r
- --signal ufm_busy : std_logic;\r
-\r
- \r
- component OSCH\r
- generic (NOM_FREQ: string := "133.00");\r
- port (\r
- STDBY :IN std_logic;\r
- OSC :OUT std_logic;\r
- SEDSTDBY :OUT std_logic\r
- );\r
- end component; \r
- \r
- \r
-begin\r
-\r
----------------------------------------------------------------------------\r
--- I/O Logic\r
----------------------------------------------------------------------------\r
--- 0 1:1,\r
--- 1 1:4 fan-out,\r
--- 2 1:1, O1 is or of inputs\r
-\r
--- 3 1:1, invert\r
--- 4 1:4 fan-out, invert\r
--- 5 1:1, O1 is or of inputs, invert\r
-\r
--- 6 1:1, rising_edge to 14-21 ns\r
--- 7 1:1, falling_edge to 14-21 ns\r
-\r
--- 8 1:1, stretching by +14-21ns\r
--- 9 1:4 fan-out, stretching\r
--- a 1:1, O1 is or of inputs, stretching\r
-\r
--- e pulser, default 8.1 kHz, 60ns \r
--- f pulser, default 8.1 kHz, 60ns, negative\r
-\r
-input_i <= INPUT when STATUSI = '0' else INPUT(2) & INPUT(3) & INPUT(0) & INPUT(1);\r
-input_selected <= not input_i when config = x"3" or config = x"4" or config = x"5" else input_i;\r
-\r
-input_stretched <= input_hold or input_reg_0 or input_reg_1;\r
-\r
---Stretcher needs to work with negative signals as well\r
-input_hold <= input_selected or (input_hold and not input_reg_0);\r
-\r
-input_reg_0 <= input_selected or input_hold when rising_edge(clk_i);\r
-input_reg_1 <= input_reg_0 when rising_edge(clk_i);\r
-input_reg_2 <= input_reg_1 when rising_edge(clk_i);\r
-\r
-edge_rising <= input_stretched and not input_reg_2;\r
-edge_falling <= not input_stretched and input_reg_2;\r
-\r
-process(INPUT,config, STATUSI)\r
- begin\r
- case config is \r
- when x"0" => \r
- OUTPUT <= input_selected;\r
- when x"1" => \r
- OUTPUT <= (others => input_selected(0));\r
- when x"2" =>\r
- OUTPUT <= (input_selected(0) and input_selected(2)) & input_selected(2) & (input_selected(0) or input_selected(2)) & input_selected(0);\r
- when x"3" => \r
- OUTPUT <= input_selected;\r
- when x"4" => \r
- OUTPUT <= (others => input_selected(0));\r
- when x"5" =>\r
- OUTPUT <= (input_selected(0) and input_selected(2)) & input_selected(2) & \r
- (input_selected(0) or input_selected(2)) & input_selected(0);\r
- when x"6" =>\r
- OUTPUT <= edge_rising;\r
- when x"7" => \r
- OUTPUT <= edge_falling;\r
- when x"8" => \r
- OUTPUT <= input_stretched;\r
- when x"9" => \r
- OUTPUT <= (others => input_stretched(0));\r
- when x"a" =>\r
- OUTPUT <= (input_stretched(0) and input_stretched(2)) & input_stretched(2) & (input_stretched(0) or input_stretched(2)) & input_stretched(0);\r
- when x"e" =>\r
- OUTPUT <= (others => pulser);\r
- when x"f" =>\r
- OUTPUT <= (others => not pulser);\r
- when others => \r
- OUTPUT <= input_selected;\r
- end case;\r
- end process;\r
-\r
----------------------------------------------------------------------------\r
--- Pulser\r
----------------------------------------------------------------------------\r
- PROC_PULSER : process begin\r
- wait until rising_edge(clk_i);\r
- pulser_counter <= pulser_counter + 1;\r
- \r
- if pulser_counter = x"0000000" then\r
- pulser <= '1';\r
- pulser_pulslength_buffer <= pulser_pulslength;\r
- pulser_periodlength_buffer <= pulser_periodlength;\r
- end if;\r
- \r
- if pulser_counter = pulser_pulslength_buffer then\r
- pulser <= '0';\r
- end if;\r
- \r
- if pulser_counter = pulser_periodlength_buffer then\r
- pulser_counter <= (others => '0');\r
- end if;\r
- end process; \r
-\r
----------------------------------------------------------------------------\r
--- LED\r
----------------------------------------------------------------------------\r
- PROC_LED : process begin\r
- wait until rising_edge(clk_i);\r
- if not (config = last_config) and timer_i(27) = '0' then\r
- led_i <= config; \r
- elsif STATUSI = '0' then\r
- led_i <= led_state;\r
- else\r
- led_i <= led_state(2) & led_state(3) & led_state(0) & led_state(1);\r
- end if; \r
- end process;\r
-\r
- PROC_LED_STATE : process begin\r
- wait until rising_edge(clk_i);\r
- for i in 0 to 3 loop\r
- if (input_reg_2(i) xor input_reg_1(i)) = '1' and (led_timer(i)(23 downto 21) > 0) then\r
- led_state(i) <= not led_state(i);\r
- led_timer(i) <= 0;\r
- elsif led_timer(i)(23) = '1' then\r
- led_state(i) <= input_reg_1(i);\r
- else\r
- led_timer(i) <= led_timer(i) + 1;\r
- end if;\r
- end loop;\r
- end process; \r
- \r
----------------------------------------------------------------------------\r
--- Clock\r
----------------------------------------------------------------------------\r
-clk_source: OSCH\r
- generic map ( NOM_FREQ => "133" )\r
- port map (\r
- STDBY => '0',\r
- OSC => clk_osc,\r
- SEDSTDBY => open\r
- );\r
- \r
-THE_PLL : entity work.pll_in133_out33_133_266 \r
- port map (\r
- CLKI => clk_osc,\r
- CLKOP => clk_i, --133\r
- CLKOS => clk_33, --33 \r
- CLKOS2=> clk_266 --266\r
- );\r
-\r
-timer_i <= timer_i + 1 when rising_edge(clk_i);\r
-\r
----------------------------------------------------------------------------\r
--- Read configuration switch\r
----------------------------------------------------------------------------\r
-process begin\r
- wait until rising_edge(clk_i);\r
- if timer_i(27 downto 10) = 0 then\r
- led_highz <= '1';\r
- last_config <= config;\r
- if timer_i(9 downto 0) = "11"&x"ff" then\r
- config <= not LED;\r
- end if;\r
- else\r
- led_highz <= '0';\r
- end if;\r
-end process; \r
-\r
-LED <= led_i when led_highz = '0' else "ZZZZ";\r
--- LED <= sed_debug(3 downto 0);\r
-\r
----------------------------------------------------------------------------\r
--- UART\r
----------------------------------------------------------------------------\r
-THE_UART : entity work.uart_sctrl\r
- generic map(\r
- CLOCK_SPEED => 33250000\r
- )\r
- port map(\r
- CLK => clk_33,\r
- RESET => '0',\r
- UART_RX => TX_IN,\r
- UART_TX => RX_OUT,\r
- \r
- DATA_OUT => uart_data_out,\r
- DATA_IN => uart_data_in,\r
- ADDR_OUT => uart_addr_out, \r
- WRITE_OUT => uart_write_out,\r
- READ_OUT => uart_read_out,\r
- READY_IN => uart_ready_in,\r
- BUSY_OUT => uart_busy_out,\r
- \r
- DEBUG => open\r
- );\r
-\r
---uart_rx_data <= uart_data_out;\r
---uart_data_in <= uart_tx_data;\r
---uart_addr <= uart_addr_out;\r
---bus_write <= uart_write_out;\r
---bus_read <= uart_read_out;\r
---uart_ready_in <= bus_ready;\r
---bus_busy <= uart_busy_out;\r
-\r
-THE_FLASH_CONTROLLER : entity generic_flash_ctrl\r
- generic map(\r
- DATA_BUS_WIDTH => 32\r
- )\r
- port map(\r
-\r
- CLK_l => clk_33,\r
- CLK_f => clk_33,\r
- RESET => '0',\r
-\r
- SPI_DATA_IN => uart_data_out,\r
- SPI_DATA_OUT => uart_data_in,\r
- SPI_ADDR_IN => uart_addr_out,\r
- SPI_WRITE_IN => uart_write_out,\r
- SPI_READ_IN => uart_read_out,\r
- SPI_READY_OUT => uart_ready_in,\r
- SPI_BUSY_IN => uart_busy_out,\r
-\r
- LOC_DATA_OUT => uart_rx_data,\r
- LOC_DATA_IN => uart_tx_data,\r
- LOC_ADDR_OUT => uart_addr,\r
- LOC_WRITE_OUT => bus_write,\r
- LOC_READ_OUT => bus_read,\r
- LOC_READY_IN => bus_ready,\r
- LOC_BUSY_OUT => bus_busy\r
-\r
- );\r
-\r
-\r
----------------------------------------------------------------------------\r
--- Read/WRITE REGISTERS VIA UART/FLASH\r
----------------------------------------------------------------------------\r
-PROC_REGS : process begin\r
- wait until rising_edge(clk_33);\r
- \r
- --register <=> UART datatransfer\r
- -------------------------------------------------------------------\r
- bus_ready <= '0';\r
--- ufm_go <= '0'; --for operating UFM_control\r
- \r
- if bus_read = '1' then\r
- --send out data from registers over RS232\r
- bus_ready <= '1';\r
- case uart_addr is\r
- when x"00" => uart_tx_data <= x"0000000" & config;\r
- when x"10" => uart_tx_data <= reg;\r
- when x"ee" => uart_tx_data <= sed_debug;\r
- \r
- when x"20" => uart_tx_data <= x"0" & std_logic_vector(pulser_periodlength);\r
- when x"21" => uart_tx_data <= x"0" & std_logic_vector(pulser_pulslength);\r
-\r
- when x"ff" => uart_tx_data <= testreg1; \r
- when x"fe" => uart_tx_data <= testreg2; \r
- \r
- when others => uart_tx_data <= x"00000000";\r
- end case;\r
- \r
- elsif bus_write = '1' then\r
- --write registers with data from received from RS232\r
- case uart_addr is\r
--- when x"02" => if uart_rx_data = x"00000000" and ufm_busy = '0' then \r
- --initiate load from UFM\r
--- ufm_cmd <= '0';\r
--- ufm_go <= '1';-\r
--- elsif uart_rx_data = x"FFFFFFFF" and ufm_busy = '0' then\r
--- --initiate write to UFM\r
--- ufm_cmd <= '1';\r
--- ufm_go <= '1';\r
--- end if; \r
- \r
- when x"10" => reg <= uart_rx_data;\r
-\r
- when x"20" => if uart_rx_data = x"00000000" or uart_rx_data = x"00000001" then\r
- pulser_periodlength <= x"0000001";\r
- else\r
- pulser_periodlength <= unsigned(uart_rx_data(27 downto 0)) - 1;\r
- end if;\r
- \r
- when x"21" => pulser_pulslength <= uart_rx_data(27 downto 0);\r
- \r
- when x"ee" => controlsed_i <= uart_rx_data(3 downto 0);\r
-\r
- when x"ff" => testreg1 <= uart_rx_data(31 downto 0);\r
- when x"fe" => testreg2 <= uart_rx_data(31 downto 0);\r
- \r
- when others => null;\r
- end case;\r
- end if;\r
- \r
- --register <=> UFM datatransfer\r
- -------------------------------------------------------------------\r
--- ufm_bus_ready_in <= '0'; \r
-\r
--- if ufm_cmd = '0' and ufm_bus_ready_out = '1' then\r
- --copy data from UFM to registers\r
--- ufm_bus_ready_in <= '1';\r
--- case to_integer(ufm_databyte_counter) is\r
--- when 0 => reg(7 downto 0) <= ufm_data_out;\r
--- when 1 => reg(15 downto 8) <= ufm_data_out;\r
--- when 2 => reg(23 downto 16) <= ufm_data_out;\r
--- when 3 => reg(31 downto 24) <= ufm_data_out;\r
- \r
--- when 4 => pulser_periodlength(7 downto 0) <= ufm_data_out;\r
--- when 5 => pulser_periodlength(15 downto 8) <= ufm_data_out;\r
--- when 6 => pulser_periodlength(23 downto 16) <= ufm_data_out;\r
--- when 7 => pulser_periodlength(27 downto 24) <= ufm_data_out(3 downto 0);\r
- \r
--- when 8 => pulser_pulslength(7 downto 0) <= ufm_data_out;\r
--- when 9 => pulser_pulslength(15 downto 8) <= ufm_data_out;\r
--- when 10 => pulser_pulslength(23 downto 16) <= ufm_data_out;\r
--- when 11 => pulser_pulslength(27 downto 24) <= ufm_data_out(3 downto 0);\r
- \r
--- when others =>null;\r
--- end case;\r
- \r
--- elsif ufm_cmd = '1' and ufm_bus_ready_out = '1' then\r
- --save data from registers to UFM\r
--- ufm_bus_ready_in <= '1';\r
--- case to_integer(ufm_databyte_counter) is\r
--- when 0 => ufm_data_in <= reg(7 downto 0);\r
--- when 1 => ufm_data_in <= reg(15 downto 8);\r
--- when 2 => ufm_data_in <= reg(23 downto 16);\r
--- when 3 => ufm_data_in <= reg(31 downto 24);\r
-\r
--- when 4 => ufm_data_in <= pulser_periodlength(7 downto 0);\r
--- when 5 => ufm_data_in <= pulser_periodlength(15 downto 8);\r
--- when 6 => ufm_data_in <= pulser_periodlength(23 downto 16);\r
--- when 7 => ufm_data_in <= x"0" & std_logic_vector(pulser_periodlength(27 downto 24));\r
- \r
--- when 8 => ufm_data_in <= pulser_pulslength(7 downto 0);\r
--- when 9 => ufm_data_in <= pulser_pulslength(15 downto 8);\r
--- when 10 => ufm_data_in <= pulser_pulslength(23 downto 16);\r
--- when 11 => ufm_data_in <= x"0" & std_logic_vector(pulser_pulslength(27 downto 24));\r
- \r
--- when others =>null;\r
--- end case;\r
- \r
--- end if;\r
-end process;\r
-\r
-\r
- THE_SED : entity work.sedcheck\r
- port map(\r
- CLK => clk_i,\r
- ERROR_OUT => sed_error,\r
- \r
- CONTROL_IN => controlsed_i,\r
- DEBUG => sed_debug\r
- );\r
-\r
--- process begin\r
--- wait until rising_edge(clk_i);\r
--- if counter = x"40" then\r
--- counter <= 0;\r
--- pwm <= '1';\r
--- else \r
--- counter <= counter + 1;\r
--- pwm <= '0';\r
--- end if; \r
--- end process;\r
--- \r
--- \r
--- OUTPUT <= '0' & pwm & '0' & pwm;\r
--- CONTROLO <= pwm;\r
- \r
-end architecture;\r
-\r
- \r
- \r
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library machxo3lf;
+use machxo3lf.all;
+
+library work;
+use work.all;--trb_net_std.all;
+
+entity logicbox is
+ port(
+ CLK : in std_logic;
+
+ INPUT : in std_logic_vector(3 downto 0);
+ OUTPUT : out std_logic_vector(3 downto 0);
+
+ LED : inout std_logic_vector(3 downto 0);
+
+ STATUSI : in std_logic;
+ STATUSO : in std_logic;
+ CONTROLI : out std_logic;
+ CONTROLO : out std_logic;
+
+ RX_OUT : out std_logic;
+ TX_IN : in std_logic;
+ CBUS : in std_logic
+ );
+end entity;
+
+architecture arch of logicbox is
+ signal clk_i, clk_osc, clk_33,clk_266 : std_logic;
+ signal led_i : std_logic_vector(3 downto 0);
+ signal timer_i : unsigned(31 downto 0) := (others => '0');
+ signal config : std_logic_vector(3 downto 0);
+ signal led_highz : std_logic;
+
+ type led_timer_t is array(0 to 3) of unsigned(24 downto 0);
+ signal led_timer : led_timer_t;
+ signal led_state : std_logic_vector(3 downto 0);
+
+ --UART
+ -------------------------------------
+ signal uart_data_out : std_logic_vector(31 downto 0);
+ signal uart_data_in : std_logic_vector(31 downto 0);
+ signal uart_addr_out : std_logic_vector(7 downto 0);
+ signal uart_read_out : std_logic := '0';
+ signal uart_write_out : std_logic := '0';
+ signal uart_ready_in : std_logic;
+ signal uart_busy_out : std_logic;
+
+ signal uart_rx_data : std_logic_vector(31 downto 0);
+ signal uart_tx_data : std_logic_vector(31 downto 0);
+ signal uart_addr : std_logic_vector(7 downto 0);
+ signal bus_read : std_logic := '0';
+ signal bus_write : std_logic := '0';
+ signal bus_ready : std_logic;
+ signal bus_busy : std_logic;
+
+ signal input_i : std_logic_vector(3 downto 0);
+ signal input_selected : std_logic_vector(3 downto 0);
+ signal input_stretched, input_hold : std_logic_vector(3 downto 0);
+ signal input_reg_0, input_reg_1, input_reg_2 : std_logic_vector(3 downto 0);
+
+ signal edge_rising, edge_falling : std_logic_vector(3 downto 0);
+ signal reg : std_logic_vector(31 downto 0);
+ signal last_config : std_logic_vector(3 downto 0);
+
+ signal sed_error : std_logic;
+ signal sed_debug : std_logic_vector(31 downto 0);
+ signal controlsed_i : std_logic_vector(3 downto 0);
+ signal testreg1, testreg2 : std_logic_vector(31 downto 0);
+
+
+ --PULSER
+ -------------------------------------
+ signal pulser : std_logic;
+ signal pulser_counter : unsigned(27 downto 0) := (others => '0');
+ signal pulser_periodlength : unsigned(27 downto 0) := x"0000002";
+ signal pulser_pulslength : unsigned(27 downto 0) := x"0000001";
+ signal pulser_periodlength_buffer : unsigned(27 downto 0);
+ signal pulser_pulslength_buffer : unsigned(27 downto 0);
+
+ --UFM
+ -------------------------------------
+ --signal ufm_cmd : std_logic := '0'; --CMD=0 => Read; CMD=1 => Write
+ --signal ufm_go : std_logic := '1'; --load default values to registers from UFM at startup
+ --signal ufm_data_in : std_logic_vector(7 downto 0); --directly connected to flashram DataInA
+ --signal ufm_data_out : std_logic_vector(7 downto 0); --directly connected to flashram QB
+ --signal ufm_databyte_counter : unsigned(14 downto 0);
+ --signal ufm_bus_ready_out : std_logic;
+ --signal ufm_bus_ready_in : std_logic;
+ --signal ufm_busy : std_logic;
+
+
+ component OSCH
+ generic (NOM_FREQ: string := "133.00");
+ port (
+ STDBY :IN std_logic;
+ OSC :OUT std_logic;
+ SEDSTDBY :OUT std_logic
+ );
+ end component;
+
+
+begin
+
+---------------------------------------------------------------------------
+-- I/O Logic
+---------------------------------------------------------------------------
+-- 0 1:1,
+-- 1 1:4 fan-out,
+-- 2 1:1, O1 is or of inputs
+
+-- 3 1:1, invert
+-- 4 1:4 fan-out, invert
+-- 5 1:1, O1 is or of inputs, invert
+
+-- 6 1:1, rising_edge to 14-21 ns
+-- 7 1:1, falling_edge to 14-21 ns
+
+-- 8 1:1, stretching by +14-21ns
+-- 9 1:4 fan-out, stretching
+-- a 1:1, O1 is or of inputs, stretching
+
+-- e pulser, default 8.1 kHz, 60ns
+-- f pulser, default 8.1 kHz, 60ns, negative
+
+input_i <= INPUT when STATUSI = '0' else INPUT(2) & INPUT(3) & INPUT(0) & INPUT(1);
+input_selected <= not input_i when config = x"3" or config = x"4" or config = x"5" else input_i;
+
+input_stretched <= input_hold or input_reg_0 or input_reg_1;
+
+--Stretcher needs to work with negative signals as well
+input_hold <= input_selected or (input_hold and not input_reg_0);
+
+input_reg_0 <= input_selected or input_hold when rising_edge(clk_i);
+input_reg_1 <= input_reg_0 when rising_edge(clk_i);
+input_reg_2 <= input_reg_1 when rising_edge(clk_i);
+
+edge_rising <= input_stretched and not input_reg_2;
+edge_falling <= not input_stretched and input_reg_2;
+
+process(INPUT,config, STATUSI)
+ begin
+ case config is
+ when x"0" =>
+ OUTPUT <= input_selected;
+ when x"1" =>
+ OUTPUT <= (others => input_selected(0));
+ when x"2" =>
+ OUTPUT <= (input_selected(0) and input_selected(2)) & input_selected(2) & (input_selected(0) or input_selected(2)) & input_selected(0);
+ when x"3" =>
+ OUTPUT <= input_selected;
+ when x"4" =>
+ OUTPUT <= (others => input_selected(0));
+ when x"5" =>
+ OUTPUT <= (input_selected(0) and input_selected(2)) & input_selected(2) &
+ (input_selected(0) or input_selected(2)) & input_selected(0);
+ when x"6" =>
+ OUTPUT <= edge_rising;
+ when x"7" =>
+ OUTPUT <= edge_falling;
+ when x"8" =>
+ OUTPUT <= input_stretched;
+ when x"9" =>
+ OUTPUT <= (others => input_stretched(0));
+ when x"a" =>
+ OUTPUT <= (input_stretched(0) and input_stretched(2)) & input_stretched(2) & (input_stretched(0) or input_stretched(2)) & input_stretched(0);
+ when x"e" =>
+ OUTPUT <= (others => pulser);
+ when x"f" =>
+ OUTPUT <= (others => not pulser);
+ when others =>
+ OUTPUT <= input_selected;
+ end case;
+ end process;
+
+---------------------------------------------------------------------------
+-- Pulser
+---------------------------------------------------------------------------
+ PROC_PULSER : process begin
+ wait until rising_edge(clk_i);
+ pulser_counter <= pulser_counter + 1;
+
+ if pulser_counter = x"0000000" then
+ pulser <= '1';
+ pulser_pulslength_buffer <= pulser_pulslength;
+ pulser_periodlength_buffer <= pulser_periodlength;
+ end if;
+
+ if pulser_counter = pulser_pulslength_buffer then
+ pulser <= '0';
+ end if;
+
+ if pulser_counter = pulser_periodlength_buffer then
+ pulser_counter <= (others => '0');
+ end if;
+ end process;
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ PROC_LED : process begin
+ wait until rising_edge(clk_i);
+ if not (config = last_config) and timer_i(27) = '0' then
+ led_i <= config;
+ elsif STATUSI = '0' then
+ led_i <= led_state;
+ else
+ led_i <= led_state(2) & led_state(3) & led_state(0) & led_state(1);
+ end if;
+ end process;
+
+ PROC_LED_STATE : process begin
+ wait until rising_edge(clk_i);
+ for i in 0 to 3 loop
+ if (input_reg_2(i) xor input_reg_1(i)) = '1' and (led_timer(i)(23 downto 21) > 0) then
+ led_state(i) <= not led_state(i);
+ led_timer(i) <= 0;
+ elsif led_timer(i)(23) = '1' then
+ led_state(i) <= input_reg_1(i);
+ else
+ led_timer(i) <= led_timer(i) + 1;
+ end if;
+ end loop;
+ end process;
+
+---------------------------------------------------------------------------
+-- Clock
+---------------------------------------------------------------------------
+clk_source: OSCH
+ generic map ( NOM_FREQ => "133" )
+ port map (
+ STDBY => '0',
+ OSC => clk_osc,
+ SEDSTDBY => open
+ );
+
+THE_PLL : entity work.pll_in133_out33_133_266
+ port map (
+ CLKI => clk_osc,
+ CLKOP => clk_i, --133
+ CLKOS => clk_33, --33
+ CLKOS2=> clk_266 --266
+ );
+
+timer_i <= timer_i + 1 when rising_edge(clk_i);
+
+---------------------------------------------------------------------------
+-- Read configuration switch
+---------------------------------------------------------------------------
+process begin
+ wait until rising_edge(clk_i);
+ if timer_i(27 downto 10) = 0 then
+ led_highz <= '1';
+ last_config <= config;
+ if timer_i(9 downto 0) = "11"&x"ff" then
+ config <= not LED;
+ end if;
+ else
+ led_highz <= '0';
+ end if;
+end process;
+
+LED <= led_i when led_highz = '0' else "ZZZZ";
+-- LED <= sed_debug(3 downto 0);
+
+---------------------------------------------------------------------------
+-- UART
+---------------------------------------------------------------------------
+THE_UART : entity work.uart_sctrl
+ generic map(
+ CLOCK_SPEED => 33250000
+ )
+ port map(
+ CLK => clk_33,
+ RESET => '0',
+ UART_RX => TX_IN,
+ UART_TX => RX_OUT,
+
+ DATA_OUT => uart_data_out,
+ DATA_IN => uart_data_in,
+ ADDR_OUT => uart_addr_out,
+ WRITE_OUT => uart_write_out,
+ READ_OUT => uart_read_out,
+ READY_IN => uart_ready_in,
+ BUSY_OUT => uart_busy_out,
+
+ DEBUG => open
+ );
+
+--uart_rx_data <= uart_data_out;
+--uart_data_in <= uart_tx_data;
+--uart_addr <= uart_addr_out;
+--bus_write <= uart_write_out;
+--bus_read <= uart_read_out;
+--uart_ready_in <= bus_ready;
+--bus_busy <= uart_busy_out;
+
+THE_FLASH_CONTROLLER : entity generic_flash_ctrl
+ generic map(
+ DATA_BUS_WIDTH => 32
+ )
+ port map(
+
+ CLK_l => clk_33,
+ CLK_f => clk_33,
+ RESET => '0',
+
+ SPI_DATA_IN => uart_data_out,
+ SPI_DATA_OUT => uart_data_in,
+ SPI_ADDR_IN => uart_addr_out,
+ SPI_WRITE_IN => uart_write_out,
+ SPI_READ_IN => uart_read_out,
+ SPI_READY_OUT => uart_ready_in,
+ SPI_BUSY_IN => uart_busy_out,
+
+ LOC_DATA_OUT => uart_rx_data,
+ LOC_DATA_IN => uart_tx_data,
+ LOC_ADDR_OUT => uart_addr,
+ LOC_WRITE_OUT => bus_write,
+ LOC_READ_OUT => bus_read,
+ LOC_READY_IN => bus_ready,
+ LOC_BUSY_OUT => bus_busy
+
+ );
+
+
+---------------------------------------------------------------------------
+-- Read/WRITE REGISTERS VIA UART/FLASH
+---------------------------------------------------------------------------
+PROC_REGS : process begin
+ wait until rising_edge(clk_33);
+
+ --register <=> UART datatransfer
+ -------------------------------------------------------------------
+ bus_ready <= '0';
+-- ufm_go <= '0'; --for operating UFM_control
+
+ if bus_read = '1' then
+ --send out data from registers over RS232
+ bus_ready <= '1';
+ case uart_addr is
+ when x"00" => uart_tx_data <= x"0000000" & config;
+ when x"10" => uart_tx_data <= reg;
+ when x"ee" => uart_tx_data <= sed_debug;
+
+ when x"20" => uart_tx_data <= x"0" & std_logic_vector(pulser_periodlength);
+ when x"21" => uart_tx_data <= x"0" & std_logic_vector(pulser_pulslength);
+
+ when x"ff" => uart_tx_data <= testreg1;
+ when x"fe" => uart_tx_data <= testreg2;
+
+ when others => uart_tx_data <= x"00000000";
+ end case;
+
+ elsif bus_write = '1' then
+ --write registers with data from received from RS232
+ case uart_addr is
+-- when x"02" => if uart_rx_data = x"00000000" and ufm_busy = '0' then
+ --initiate load from UFM
+-- ufm_cmd <= '0';
+-- ufm_go <= '1';-
+-- elsif uart_rx_data = x"FFFFFFFF" and ufm_busy = '0' then
+-- --initiate write to UFM
+-- ufm_cmd <= '1';
+-- ufm_go <= '1';
+-- end if;
+
+ when x"10" => reg <= uart_rx_data;
+
+ when x"20" => if uart_rx_data = x"00000000" or uart_rx_data = x"00000001" then
+ pulser_periodlength <= x"0000001";
+ else
+ pulser_periodlength <= unsigned(uart_rx_data(27 downto 0)) - 1;
+ end if;
+
+ when x"21" => pulser_pulslength <= uart_rx_data(27 downto 0);
+
+ when x"ee" => controlsed_i <= uart_rx_data(3 downto 0);
+
+ when x"ff" => testreg1 <= uart_rx_data(31 downto 0);
+ when x"fe" => testreg2 <= uart_rx_data(31 downto 0);
+
+ when others => null;
+ end case;
+ end if;
+
+ --register <=> UFM datatransfer
+ -------------------------------------------------------------------
+-- ufm_bus_ready_in <= '0';
+
+-- if ufm_cmd = '0' and ufm_bus_ready_out = '1' then
+ --copy data from UFM to registers
+-- ufm_bus_ready_in <= '1';
+-- case to_integer(ufm_databyte_counter) is
+-- when 0 => reg(7 downto 0) <= ufm_data_out;
+-- when 1 => reg(15 downto 8) <= ufm_data_out;
+-- when 2 => reg(23 downto 16) <= ufm_data_out;
+-- when 3 => reg(31 downto 24) <= ufm_data_out;
+
+-- when 4 => pulser_periodlength(7 downto 0) <= ufm_data_out;
+-- when 5 => pulser_periodlength(15 downto 8) <= ufm_data_out;
+-- when 6 => pulser_periodlength(23 downto 16) <= ufm_data_out;
+-- when 7 => pulser_periodlength(27 downto 24) <= ufm_data_out(3 downto 0);
+
+-- when 8 => pulser_pulslength(7 downto 0) <= ufm_data_out;
+-- when 9 => pulser_pulslength(15 downto 8) <= ufm_data_out;
+-- when 10 => pulser_pulslength(23 downto 16) <= ufm_data_out;
+-- when 11 => pulser_pulslength(27 downto 24) <= ufm_data_out(3 downto 0);
+
+-- when others =>null;
+-- end case;
+
+-- elsif ufm_cmd = '1' and ufm_bus_ready_out = '1' then
+ --save data from registers to UFM
+-- ufm_bus_ready_in <= '1';
+-- case to_integer(ufm_databyte_counter) is
+-- when 0 => ufm_data_in <= reg(7 downto 0);
+-- when 1 => ufm_data_in <= reg(15 downto 8);
+-- when 2 => ufm_data_in <= reg(23 downto 16);
+-- when 3 => ufm_data_in <= reg(31 downto 24);
+
+-- when 4 => ufm_data_in <= pulser_periodlength(7 downto 0);
+-- when 5 => ufm_data_in <= pulser_periodlength(15 downto 8);
+-- when 6 => ufm_data_in <= pulser_periodlength(23 downto 16);
+-- when 7 => ufm_data_in <= x"0" & std_logic_vector(pulser_periodlength(27 downto 24));
+
+-- when 8 => ufm_data_in <= pulser_pulslength(7 downto 0);
+-- when 9 => ufm_data_in <= pulser_pulslength(15 downto 8);
+-- when 10 => ufm_data_in <= pulser_pulslength(23 downto 16);
+-- when 11 => ufm_data_in <= x"0" & std_logic_vector(pulser_pulslength(27 downto 24));
+
+-- when others =>null;
+-- end case;
+
+-- end if;
+end process;
+
+
+ THE_SED : entity work.sedcheck
+ port map(
+ CLK => clk_i,
+ ERROR_OUT => sed_error,
+
+ CONTROL_IN => controlsed_i,
+ DEBUG => sed_debug
+ );
+
+-- process begin
+-- wait until rising_edge(clk_i);
+-- if counter = x"40" then
+-- counter <= 0;
+-- pwm <= '1';
+-- else
+-- counter <= counter + 1;
+-- pwm <= '0';
+-- end if;
+-- end process;
+--
+--
+-- OUTPUT <= '0' & pwm & '0' & pwm;
+-- CONTROLO <= pwm;
+
+end architecture;
+
+
+
jspc29 / logicbox.git / commitdiff