USE_REPLY_CHANNEL : integer range 0 to 1 := std_USE_REPLY_CHANNEL;
FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES;
SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES
);
component trb_net16_fifo is
generic (
- DEPTH : integer := 3 -- Depth of the FIFO, 2^(n+1) 64Bit packets
+ DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1) 64Bit packets
+ USE_VENDOR_CORES : integer := c_YES
);
port (
CLK : in std_logic;
CHECK_BUFFER3: if FIFO_TO_INT_DEPTH >0 generate
FIFO_TO_INT: trb_net16_fifo
generic map (
- DEPTH => FIFO_TO_INT_DEPTH)
+ DEPTH => FIFO_TO_INT_DEPTH,
+ USE_VENDOR_CORES => USE_VENDOR_CORES)
port map (
CLK => CLK,
RESET => RESET,
CHECK_BUFFER5: if FIFO_TO_APL_DEPTH >0 generate
FIFO_TO_APL: trb_net16_fifo
generic map (
- DEPTH => FIFO_TO_APL_DEPTH)
+ DEPTH => FIFO_TO_APL_DEPTH,
+ USE_VENDOR_CORES => USE_VENDOR_CORES)
port map (
CLK => CLK,
RESET => RESET,
next_send_trm_wrong_addr <= '0';
next_wait_for_answer <= '0';
get_slave_running <= '0';
+ throw_away <= '0';
if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = "11" and (sbuf_to_apl_free = '1' or state_to_apl = WRONG_ADDR) then
next_state_to_apl <= IDLE;
HUB_CTRL_REG_ADDR_WIDTH : integer range 1 to 7 := 4;
HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES);
IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
+ HUB_ADDRESS : std_logic_vector(15 downto 0) := x"F003";
--media interfaces
MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12;
MII_INIT_DEPTH : hub_iobuf_config_t := std_HUB_INIT_DEPTH;
signal HUB_CTRL_CHANNEL : std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
signal HUB_CTRL_activepoints : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0);
signal HUB_CTRL_GEN : std_logic_vector (31 downto 0);
- signal HUB_ADDRESS : std_logic_vector (15 downto 0);
signal IOBUF_STAT_GEN : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
signal IOBUF_STAT_LOCKED : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
component trb_net16_iobuf is
generic (
- INIT_DEPTH : integer := 1;
- REPLY_DEPTH : integer := 1;
- IBUF_SECURE_MODE : integer := 1
+ INIT_DEPTH : integer range 0 to 6 := 6;
+ REPLY_DEPTH : integer range 0 to 6 := 6;
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
+ OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
+ USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
+ USE_REPLY_CHANNEL : integer range 0 to 1 := c_YES; -- not used yet
+ INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
+ REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
);
port(
-- Misc
component trb_net16_api_base is
generic (
- API_TYPE : integer := 1;
- FIFO_TO_INT_DEPTH : integer := 1;
- FIFO_TO_APL_DEPTH : integer := 1;
- SBUF_VERSION : integer := 0
+ API_TYPE : integer range 0 to 1 := c_API_ACTIVE;
+ FIFO_TO_INT_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
+ FIFO_TO_APL_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
+ USE_REPLY_CHANNEL : integer range 0 to 1 := std_USE_REPLY_CHANNEL;
+ FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
+ SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES;
+ SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES
);
port(
-- Misc
generic map (
INIT_DEPTH => calc_depth(i,MII_INIT_DEPTH, API_FIFO_TO_APL_DEPTH, MII_NUMBER, API_NUMBER, c_MUX_WIDTH, HUB_CTRL_DEPTH),
REPLY_DEPTH => calc_depth(i,MII_REPLY_DEPTH, API_FIFO_TO_INT_DEPTH, MII_NUMBER, API_NUMBER, c_MUX_WIDTH, HUB_CTRL_DEPTH),
- IBUF_SECURE_MODE => IBUF_SECURE_MODE
+ IBUF_SECURE_MODE => IBUF_SECURE_MODE
)
port map (
-- Misc
process(fifo_data_out, fifo_packet_num_out, is_locked, sbuf_free, fifo_empty, last_fifo_read, current_fifo_packet_type,
- release_locked)
+ release_locked, fifo_read_before, INT_READ_IN)
begin
tmp_INT_DATA_OUT <= fifo_data_out;
tmp_INT_PACKET_NUM_OUT <= fifo_packet_num_out;
);
end component;
- signal MUX_SBUF_data_out : std_logic_vector(c_DATA_WIDTH+1 downto 0);
signal demux_next_READ, current_demux_READ : STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0);
signal next_demux_dr, next_demux_dr_tmp, demux_dr_tmp: STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0);
signal current_MED_READ_OUT, next_MED_READ_OUT: STD_LOGIC;
- signal tmp_INT_READ_OUT, final_INT_READ_OUT: STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0);
+ signal final_INT_READ_OUT: STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0);
--signal tmp_tmp_INT_READ_OUT: STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0);
signal mux_read, mux_enable, mux_next_READ: STD_LOGIC;
signal current_mux_buffer: STD_LOGIC_VECTOR (c_DATA_WIDTH+2-1 downto 0);
signal endpoint_locked, next_endpoint_locked: std_logic;
- signal demux_sbuf_data_in : std_logic_vector((c_DATA_WIDTH+2)-1 downto 0);
- signal demux_sbuf_data_out: std_logic_vector((c_DATA_WIDTH+2)*(2**c_MUX_WIDTH)-1 downto 0);
signal current_INT_READ_OUT : STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0);
signal current_mux_packet_number : std_logic_vector (1 downto 0);
signal last_mux_enable : std_logic;
end if;
end process;
- process(tmp_INT_READ_OUT, endpoint_locked, final_INT_READ_OUT, last_mux_enable)
+ process(final_INT_READ_OUT, last_mux_enable)
begin
current_INT_READ_OUT <= final_INT_READ_OUT;
if last_mux_enable = '0' then
DEPTH : integer range 0 to 7 := std_FIFO_DEPTH;
USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- SECURE_MODE : integer range 0 to 1 := std_IBUF_SECURE_MODE
+ SECURE_MODE : integer range 0 to 1 := std_IBUF_SECURE_MODE;
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES
);
port(
-- Misc
if rising_edge(TLK_CLK_neg) then
if internal_reset = '1' then
reg_TXD <= (others => '0');
- reg_TX_EN <= '0';
+ --reg_TX_EN <= '0';
+ last_fifo_rd_en_m <= '0';
else
reg_TXD <= fifo_dout_m(15 downto 0);
reg_TX_EN <= last_fifo_rd_en_m;
- end if;
- end if;
- end process;
-
- process(TLK_CLK_neg)
- begin
- if rising_edge(TLK_CLK_neg) then
- if internal_reset = '1' then
- last_fifo_rd_en_m <= '0';
- else
last_fifo_rd_en_m <= fifo_rd_en_m;
end if;
end if;
constant c_DATA_WIDTH : integer := 16;
constant c_NUM_WIDTH : integer := 2;
- constant c_MUX_WIDTH : integer := 3;
+ constant c_MUX_WIDTH : integer := 1; --!!!
--assigning channel names
constant c_TRG_LVL2_CHANNEL : integer := 1;
constant c_DATA_CHANNEL : integer := 2;
constant c_SLOW_CTRL_CHANNEL : integer := 3;
-
--api_type generic
constant c_API_ACTIVE : integer := 1;