]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commitdiff
*** empty log message ***
authorhadeshyp <hadeshyp>
Tue, 12 Feb 2013 14:18:27 +0000 (14:18 +0000)
committerhadeshyp <hadeshyp>
Tue, 12 Feb 2013 14:18:27 +0000 (14:18 +0000)
soda_source/trb3_periph_sodasource.lpf [new file with mode: 0644]
soda_source/trb3_periph_sodasource.vhd [new file with mode: 0644]
soda_source/version.vhd [new file with mode: 0644]

diff --git a/soda_source/trb3_periph_sodasource.lpf b/soda_source/trb3_periph_sodasource.lpf
new file mode 100644 (file)
index 0000000..177c22b
--- /dev/null
@@ -0,0 +1,213 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+#   SYSCONFIG MCCLK_FREQ = 2.5;
+
+  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+  FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
+  FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
+
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP  "CLK_PCLK_RIGHT"       SITE "U20";
+LOCATE COMP  "CLK_PCLK_LEFT"        SITE "M4";
+LOCATE COMP  "CLK_SERDES_INT_RIGHT" SITE "AC18";
+LOCATE COMP  "CLK_SERDES_INT_LEFT"  SITE "AC10";
+LOCATE COMP  "CLK_GPLL_RIGHT"       SITE "W1";
+LOCATE COMP  "CLK_GPLL_LEFT"        SITE "U25";
+
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP  "CLK_group" IO_TYPE=LVDS25;
+
+
+#################################################################
+# Trigger I/O
+#################################################################
+
+#Trigger from fan-out
+LOCATE COMP  "TRIGGER_LEFT"   SITE "V3";
+LOCATE COMP  "TRIGGER_RIGHT"   SITE "N24";
+IOBUF  PORT  "TRIGGER_RIGHT" IO_TYPE=LVDS25 ; 
+IOBUF  PORT  "TRIGGER_LEFT"  IO_TYPE=LVDS25 ;
+
+
+
+
+#################################################################
+# To central FPGA
+#################################################################
+
+LOCATE COMP  "FPGA5_COMM_0"   SITE "AD4";
+LOCATE COMP  "FPGA5_COMM_1"   SITE "AE3";
+LOCATE COMP  "FPGA5_COMM_2"   SITE "AA7";
+LOCATE COMP  "FPGA5_COMM_3"   SITE "AB7";
+LOCATE COMP  "FPGA5_COMM_4"   SITE "AD3";
+LOCATE COMP  "FPGA5_COMM_5"   SITE "AC4";
+LOCATE COMP  "FPGA5_COMM_6"   SITE "AE2";
+LOCATE COMP  "FPGA5_COMM_7"   SITE "AF3";
+LOCATE COMP  "FPGA5_COMM_8"   SITE "AE4";
+LOCATE COMP  "FPGA5_COMM_9"   SITE "AF4";
+LOCATE COMP  "FPGA5_COMM_10"  SITE "V10";
+LOCATE COMP  "FPGA5_COMM_11"  SITE "W10";
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+LOCATE COMP  "TEST_LINE_0"   SITE "A5";
+LOCATE COMP  "TEST_LINE_1"   SITE "A6";
+LOCATE COMP  "TEST_LINE_2"   SITE "G8";
+LOCATE COMP  "TEST_LINE_3"   SITE "F9";
+LOCATE COMP  "TEST_LINE_4"   SITE "D9";
+LOCATE COMP  "TEST_LINE_5"   SITE "D10";
+LOCATE COMP  "TEST_LINE_6"   SITE "F10";
+LOCATE COMP  "TEST_LINE_7"   SITE "E10";
+LOCATE COMP  "TEST_LINE_8"   SITE "A8";
+LOCATE COMP  "TEST_LINE_9"   SITE "B8";
+LOCATE COMP  "TEST_LINE_10"  SITE "G10";
+LOCATE COMP  "TEST_LINE_11"  SITE "G9";
+LOCATE COMP  "TEST_LINE_12"  SITE "C9";
+LOCATE COMP  "TEST_LINE_13"  SITE "C10";
+LOCATE COMP  "TEST_LINE_14"  SITE "H10";
+LOCATE COMP  "TEST_LINE_15"  SITE "H11";
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12;
+
+#################################################################
+# Connection to AddOn
+#################################################################
+
+LOCATE COMP  "LED_LINKOK_1"  SITE "P1";     #DQLL0_0   #1
+LOCATE COMP  "LED_RX_1"      SITE "P2";     #DQLL0_1   #3
+LOCATE COMP  "LED_TX_1"      SITE "T2";     #DQLL0_2   #5
+LOCATE COMP  "SFP_MOD0_1"    SITE "U3";     #DQLL0_3   #7
+LOCATE COMP  "SFP_MOD1_1"    SITE "R1";     #DQLL0_4   #9
+LOCATE COMP  "SFP_MOD2_1"    SITE "R2";     #DQLL0_5   #11
+LOCATE COMP  "SFP_RATESEL_1" SITE "N3";     #DQSLL0_T  #13
+LOCATE COMP  "SFP_TXDIS_1"   SITE "P3";     #DQSLL0_C  #15
+LOCATE COMP  "SFP_LOS_1"     SITE "P5";     #DQLL0_6   #17
+LOCATE COMP  "SFP_TXFAULT_1" SITE "P6";     #DQLL0_7   #19
+
+LOCATE COMP  "LED_LINKOK_2"  SITE "N5";     #DQLL0_8   #21
+LOCATE COMP  "LED_RX_2"      SITE "N6";     #DQLL0_9   #23
+LOCATE COMP  "LED_TX_2"      SITE "AC2";    #DQLL2_0   #25
+LOCATE COMP  "SFP_MOD0_2"    SITE "AC3";    #DQLL2_1   #27
+LOCATE COMP  "SFP_MOD1_2"    SITE "AB1";    #DQLL2_2   #29
+LOCATE COMP  "SFP_MOD2_2"    SITE "AC1";    #DQLL2_3   #31
+LOCATE COMP  "SFP_RATESEL_2" SITE "AA1";    #DQLL2_4   #33
+LOCATE COMP  "SFP_TXDIS_2"   SITE "AA2";    #DQLL2_5   #35
+LOCATE COMP  "SFP_LOS_2"     SITE "W7";     #DQLL2_T   #37  #should be DQSLL2
+LOCATE COMP  "SFP_TXFAULT_2" SITE "W6";     #DQLL2_C   #39  #should be DQSLL2
+
+LOCATE COMP  "LED_LINKOK_3"    SITE "AD1";    #DQLL3_0   #2
+LOCATE COMP  "LED_RX_3"        SITE "AD2";    #DQLL3_1   #4
+LOCATE COMP  "LED_TX_3"        SITE "AB5";    #DQLL3_2   #6
+LOCATE COMP  "SFP_MOD0_3"      SITE "AB6";    #DQLL3_3   #8
+LOCATE COMP  "SFP_MOD1_3"      SITE "AB3";    #DQLL3_4   #10
+LOCATE COMP  "SFP_MOD2_3"      SITE "AB4";    #DQLL3_5   #12
+LOCATE COMP  "SFP_RATESEL_3"   SITE "Y6";     #DQLL3_T   #14  #should be DQSLL3
+LOCATE COMP  "SFP_TXDIS_3"     SITE "Y7";     #DQLL3_C   #16  #should be DQSLL3
+LOCATE COMP  "SFP_LOS_3"       SITE "AA3";    #DQLL3_6   #18
+LOCATE COMP  "SFP_TXFAULT_3"   SITE "AA4";    #DQLL3_7   #20
+
+LOCATE COMP  "LED_LINKOK_4"    SITE "W8";     #DQLL3_8   #22
+LOCATE COMP  "LED_RX_4"        SITE "W9";     #DQLL3_9   #24
+LOCATE COMP  "LED_TX_4"        SITE "V1";     #DQLL1_0   #26
+LOCATE COMP  "SFP_MOD0_4"      SITE "U2";     #DQLL1_1   #28
+LOCATE COMP  "SFP_MOD1_4"      SITE "T1";     #DQLL1_2   #30
+LOCATE COMP  "SFP_MOD2_4"      SITE "U1";     #DQLL1_3   #32
+LOCATE COMP  "SFP_RATESEL_4"   SITE "P4";     #DQLL1_4   #34
+LOCATE COMP  "SFP_TXDIS_4"     SITE "R3";     #DQLL1_5   #36
+LOCATE COMP  "SFP_LOS_4"       SITE "T3";     #DQSLL1_T  #38
+LOCATE COMP  "SFP_TXFAULT_4"   SITE "R4";     #DQSLL1_C  #40
+
+
+
+LOCATE COMP  "LED_LINKOK_5"   SITE "W23";    #DQLR1_0   #169
+LOCATE COMP  "LED_RX_5"       SITE "W22";    #DQLR1_1   #171
+LOCATE COMP  "LED_TX_5"       SITE "AA25";   #DQLR1_2   #173
+LOCATE COMP  "SFP_MOD0_5"     SITE "Y24";    #DQLR1_3   #175
+LOCATE COMP  "SFP_MOD1_5"     SITE "AA26";   #DQLR1_4   #177
+LOCATE COMP  "SFP_MOD2_5"     SITE "AB26";   #DQLR1_5   #179
+LOCATE COMP  "SFP_RATESEL_5"  SITE "W21";    #DQSLR1_T  #181
+LOCATE COMP  "SFP_TXDIS_5"    SITE "W20";    #DQSLR1_C  #183
+LOCATE COMP  "SFP_LOS_5"      SITE "AA24";   #DQLR1_6   #185
+LOCATE COMP  "SFP_TXFAULT_5"  SITE "AA23";   #DQLR1_7   #187
+
+LOCATE COMP  "LED_LINKOK_6"   SITE "R25";    #DQLR2_0   #170
+LOCATE COMP  "LED_RX_6"       SITE "R26";    #DQLR2_1   #172
+LOCATE COMP  "LED_TX_6"       SITE "T25";    #DQLR2_2   #174
+LOCATE COMP  "SFP_MOD0_6"     SITE "T24";    #DQLR2_3   #176
+LOCATE COMP  "SFP_MOD1_6"     SITE "T26";    #DQLR2_4   #178
+LOCATE COMP  "SFP_MOD2_6"     SITE "U26";    #DQLR2_5   #180
+LOCATE COMP  "SFP_RATESEL_6"  SITE "V21";    #DQSLR2_T  #182
+LOCATE COMP  "SFP_TXDIS_6"    SITE "V22";    #DQSLR2_C  #184
+LOCATE COMP  "SFP_LOS_6"      SITE "U24";    #DQLR2_6   #186
+LOCATE COMP  "SFP_TXFAULT_6"  SITE "V24";    #DQLR2_7   #188
+
+
+DEFINE PORT GROUP "SFP_group" "SFP*" ;
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP;
+
+
+#################################################################
+# Additional Lines to AddOn
+#################################################################
+
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
+#all lines are input only
+#line 4/5 go to PLL input
+LOCATE COMP  "SPARE_LINE_0"    SITE "M25"; #194
+LOCATE COMP  "SPARE_LINE_1"    SITE "M26"; #196
+LOCATE COMP  "SPARE_LINE_2"    SITE "W4";  #198
+LOCATE COMP  "SPARE_LINE_3"    SITE "W5";  #200
+LOCATE COMP  "SPARE_LINE_4"    SITE "M3";  #DQUL3_8_OUTOFLANE_FPGA__3 #69
+LOCATE COMP  "SPARE_LINE_5"    SITE "M2";  #DQUL3_9_OUTOFLANE_FPGA__3 #71  
+
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+
+LOCATE COMP  "FLASH_CLK"    SITE "B12";
+LOCATE COMP  "FLASH_CS"   SITE "E11";
+LOCATE COMP  "FLASH_DIN"   SITE "E12";
+LOCATE COMP  "FLASH_DOUT"    SITE "A12";
+
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+
+LOCATE COMP  "PROGRAMN"   SITE "B11";
+IOBUF  PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8  ;
+
+
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP  "TEMPSENS"    SITE "A13";
+IOBUF  PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8  ;
+
+#coding of FPGA number
+LOCATE COMP "CODE_LINE_1"    SITE "AA20";
+LOCATE COMP "CODE_LINE_0"    SITE "Y21";
+IOBUF  PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP  ;
+IOBUF  PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP  ;
+
+#terminated differential pair to pads
+LOCATE COMP  "SUPPL"   SITE "C14";
+IOBUF  PORT "SUPPL" IO_TYPE=LVDS25   ;
+
+
+#################################################################
+# LED
+#################################################################
+LOCATE COMP  "LED_GREEN"    SITE "F12";
+LOCATE COMP  "LED_ORANGE"   SITE "G13";
+LOCATE COMP  "LED_RED"      SITE "A15";
+LOCATE COMP  "LED_YELLOW"   SITE "A16";
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12;
diff --git a/soda_source/trb3_periph_sodasource.vhd b/soda_source/trb3_periph_sodasource.vhd
new file mode 100644 (file)
index 0000000..6587ec3
--- /dev/null
@@ -0,0 +1,814 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.version.all;
+
+
+entity trb3_periph_padiwa is
+  generic(
+    SYNC_MODE : integer range 0 to 1 := c_NO   --use the RX clock for internal logic and transmission.
+    );
+  port(
+    --Clocks
+    CLK_GPLL_LEFT  : in std_logic;      --Clock Manager 6
+    CLK_GPLL_RIGHT : in std_logic;  --Clock Manager 4  <-- MAIN CLOCK for FPGA
+    CLK_PCLK_LEFT  : in std_logic;      --Clock Manager 3
+    CLK_PCLK_RIGHT : in std_logic;      --Clock Manager 1
+    --CLK_PCLK_RIGHT is the only clock with external termination !?
+    CLK_EXTERNAL   : in std_logic;      --Clock Manager 9
+
+
+--     --Trigger
+    TRIGGER_LEFT : in std_logic;        --left side trigger input from fan-out
+--     TRIGGER_RIGHT : in std_logic;       --right side trigger input from fan-out
+
+    --Serdes
+    CLK_SERDES_INT_RIGHT : in  std_logic;  --Clock Manager 0, not used
+    SERDES_TX            : out std_logic_vector(3 downto 2);
+    SERDES_RX            : in  std_logic_vector(3 downto 2);
+
+    FPGA5_COMM : inout std_logic_vector(11 downto 0);
+                                        --Bit 0/1 input, serial link RX active
+                                        --Bit 2/3 output, serial link TX active
+
+
+    --Connections
+    SPARE_LINE : inout std_logic_vector(3 downto 0);
+    INP        : in    std_logic_vector(63 downto 0);
+
+    --Flash ROM & Reboot
+    FLASH_CLK  : out std_logic;
+    FLASH_CS   : out std_logic;
+    FLASH_DIN  : out std_logic;
+    FLASH_DOUT : in  std_logic;
+    PROGRAMN   : out std_logic;         --reboot FPGA
+
+    --DAC
+    OUT_SDO    : out   std_logic_vector(4 downto 1);
+    IN_SDI     : in    std_logic_vector(4 downto 1);
+    OUT_SCK    : out   std_logic_vector(4 downto 1);
+    OUT_CS     : out   std_logic_vector(4 downto 1);
+    --Misc
+    TEMPSENS   : inout std_logic;       --Temperature Sensor
+    CODE_LINE  : in    std_logic_vector(1 downto 0);
+    LED_GREEN  : out   std_logic;
+    LED_ORANGE : out   std_logic;
+    LED_RED    : out   std_logic;
+    LED_YELLOW : out   std_logic;
+
+    --Test Connectors
+    TEST_LINE : out std_logic_vector(15 downto 0)
+    );
+
+
+  attribute syn_useioff               : boolean;
+  --no IO-FF for LEDs relaxes timing constraints
+  attribute syn_useioff of LED_GREEN  : signal is false;
+  attribute syn_useioff of LED_ORANGE : signal is false;
+  attribute syn_useioff of LED_RED    : signal is false;
+  attribute syn_useioff of LED_YELLOW : signal is false;
+  attribute syn_useioff of TEMPSENS   : signal is false;
+  attribute syn_useioff of PROGRAMN   : signal is false;
+
+  --important signals _with_ IO-FF
+  attribute syn_useioff of OUT_SCK    : signal is true;
+  attribute syn_useioff of OUT_CS     : signal is true;
+  attribute syn_useioff of OUT_SDO    : signal is true;
+  attribute syn_useioff of FLASH_CLK  : signal is true;
+  attribute syn_useioff of FLASH_CS   : signal is true;
+  attribute syn_useioff of FLASH_DIN  : signal is true;
+  attribute syn_useioff of FLASH_DOUT : signal is true;
+  attribute syn_useioff of TEST_LINE  : signal is true;
+  attribute syn_useioff of SPARE_LINE : signal is true;
+
+
+end entity;
+
+architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is
+  --Constants
+  constant REGIO_NUM_STAT_REGS : integer := 0;
+  constant REGIO_NUM_CTRL_REGS : integer := 2;
+
+  attribute syn_keep     : boolean;
+  attribute syn_preserve : boolean;
+
+  --Clock / Reset
+  signal clk_100_i                : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+  signal clk_200_i                : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+  signal pll_lock                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
+  signal clear_i                  : std_logic;
+  signal reset_i                  : std_logic;
+  signal GSR_N                    : std_logic;
+  attribute syn_keep of GSR_N     : signal is true;
+  attribute syn_preserve of GSR_N : signal is true;
+  signal clk_100_internal         : std_logic;
+  signal clk_200_internal         : std_logic;
+  signal rx_clock_100             : std_logic;
+  signal rx_clock_200             : std_logic;
+  signal clk_tdc                  : std_logic;
+  signal time_counter, time_counter2 : unsigned(31 downto 0);
+  --Media Interface
+  signal med_stat_op        : std_logic_vector (1*16-1 downto 0);
+  signal med_ctrl_op        : std_logic_vector (1*16-1 downto 0);
+  signal med_stat_debug     : std_logic_vector (1*64-1 downto 0);
+  signal med_ctrl_debug     : std_logic_vector (1*64-1 downto 0);
+  signal med_data_out       : std_logic_vector (1*16-1 downto 0);
+  signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
+  signal med_dataready_out  : std_logic;
+  signal med_read_out       : std_logic;
+  signal med_data_in        : std_logic_vector (1*16-1 downto 0);
+  signal med_packet_num_in  : std_logic_vector (1*3-1 downto 0);
+  signal med_dataready_in   : std_logic;
+  signal med_read_in        : std_logic;
+
+  --LVL1 channel
+  signal timing_trg_received_i  : std_logic;
+  signal trg_data_valid_i       : std_logic;
+  signal trg_timing_valid_i     : std_logic;
+  signal trg_notiming_valid_i   : std_logic;
+  signal trg_invalid_i          : std_logic;
+  signal trg_type_i             : std_logic_vector(3 downto 0);
+  signal trg_number_i           : std_logic_vector(15 downto 0);
+  signal trg_code_i             : std_logic_vector(7 downto 0);
+  signal trg_information_i      : std_logic_vector(23 downto 0);
+  signal trg_int_number_i       : std_logic_vector(15 downto 0);
+  signal trg_multiple_trg_i     : std_logic;
+  signal trg_timeout_detected_i : std_logic;
+  signal trg_spurious_trg_i     : std_logic;
+  signal trg_missing_tmg_trg_i  : std_logic;
+  signal trg_spike_detected_i   : std_logic;
+
+  --Data channel
+  signal fee_trg_release_i    : std_logic;
+  signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
+  signal fee_data_i           : std_logic_vector(31 downto 0);
+  signal fee_data_write_i     : std_logic;
+  signal fee_data_finished_i  : std_logic;
+  signal fee_almost_full_i    : std_logic;
+
+  --Slow Control channel
+  signal common_stat_reg        : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+  signal common_ctrl_reg        : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+  signal stat_reg               : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+  signal ctrl_reg               : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+  signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+  signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+  signal stat_reg_strobe        : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+  signal ctrl_reg_strobe        : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+  --RegIO
+  signal my_address             : std_logic_vector (15 downto 0);
+  signal regio_addr_out         : std_logic_vector (15 downto 0);
+  signal regio_read_enable_out  : std_logic;
+  signal regio_write_enable_out : std_logic;
+  signal regio_data_out         : std_logic_vector (31 downto 0);
+  signal regio_data_in          : std_logic_vector (31 downto 0);
+  signal regio_dataready_in     : std_logic;
+  signal regio_no_more_data_in  : std_logic;
+  signal regio_write_ack_in     : std_logic;
+  signal regio_unknown_addr_in  : std_logic;
+  signal regio_timeout_out      : std_logic;
+
+  --Timer
+  signal global_time         : std_logic_vector(31 downto 0);
+  signal local_time          : std_logic_vector(7 downto 0);
+  signal time_since_last_trg : std_logic_vector(31 downto 0);
+  signal timer_ticks         : std_logic_vector(1 downto 0);
+
+  --Flash
+  signal spictrl_read_en  : std_logic;
+  signal spictrl_write_en : std_logic;
+  signal spictrl_data_in  : std_logic_vector(31 downto 0);
+  signal spictrl_addr     : std_logic;
+  signal spictrl_data_out : std_logic_vector(31 downto 0);
+  signal spictrl_ack      : std_logic;
+  signal spictrl_busy     : std_logic;
+  signal spimem_read_en   : std_logic;
+  signal spimem_write_en  : std_logic;
+  signal spimem_data_in   : std_logic_vector(31 downto 0);
+  signal spimem_addr      : std_logic_vector(5 downto 0);
+  signal spimem_data_out  : std_logic_vector(31 downto 0);
+  signal spimem_ack       : std_logic;
+
+  signal dac_read_en  : std_logic;
+  signal dac_write_en : std_logic;
+  signal dac_data_in  : std_logic_vector(31 downto 0);
+  signal dac_addr     : std_logic_vector(4 downto 0);
+  signal dac_data_out : std_logic_vector(31 downto 0);
+  signal dac_ack      : std_logic;
+  signal dac_busy     : std_logic;
+
+  signal hitreg_read_en    : std_logic;
+  signal hitreg_write_en   : std_logic;
+  signal hitreg_data_in    : std_logic_vector(31 downto 0);
+  signal hitreg_addr       : std_logic_vector(6 downto 0);
+  signal hitreg_data_out   : std_logic_vector(31 downto 0);
+  signal hitreg_data_ready : std_logic;
+  signal hitreg_invalid    : std_logic;
+
+  signal srb_read_en    : std_logic;
+  signal srb_write_en   : std_logic;
+  signal srb_data_in    : std_logic_vector(31 downto 0);
+  signal srb_addr       : std_logic_vector(6 downto 0);
+  signal srb_data_out   : std_logic_vector(31 downto 0);
+  signal srb_data_ready : std_logic;
+  signal srb_invalid    : std_logic;
+
+  signal lhb_read_en    : std_logic;
+  signal lhb_write_en   : std_logic;
+  signal lhb_data_in    : std_logic_vector(31 downto 0);
+  signal lhb_addr       : std_logic_vector(6 downto 0);
+  signal lhb_data_out   : std_logic_vector(31 downto 0);
+  signal lhb_data_ready : std_logic;
+  signal lhb_invalid    : std_logic;
+
+  signal esb_read_en    : std_logic;
+  signal esb_write_en   : std_logic;
+  signal esb_data_in    : std_logic_vector(31 downto 0);
+  signal esb_addr       : std_logic_vector(6 downto 0);
+  signal esb_data_out   : std_logic_vector(31 downto 0);
+  signal esb_data_ready : std_logic;
+  signal esb_invalid    : std_logic;
+
+  signal fwb_read_en    : std_logic;
+  signal fwb_write_en   : std_logic;
+  signal fwb_data_in    : std_logic_vector(31 downto 0);
+  signal fwb_addr       : std_logic_vector(6 downto 0);
+  signal fwb_data_out   : std_logic_vector(31 downto 0);
+  signal fwb_data_ready : std_logic;
+  signal fwb_invalid    : std_logic;
+
+  signal spi_bram_addr : std_logic_vector(7 downto 0);
+  signal spi_bram_wr_d : std_logic_vector(7 downto 0);
+  signal spi_bram_rd_d : std_logic_vector(7 downto 0);
+  signal spi_bram_we   : std_logic;
+
+  signal sci1_ack      : std_logic;
+  signal sci1_write    : std_logic;
+  signal sci1_read     : std_logic;
+  signal sci1_data_in  : std_logic_vector(7 downto 0);
+  signal sci1_data_out : std_logic_vector(7 downto 0);
+  signal sci1_addr     : std_logic_vector(8 downto 0);  
+  
+  signal padiwa_cs  : std_logic_vector(3 downto 0);
+  signal padiwa_sck : std_logic;
+  signal padiwa_sdi : std_logic;
+  signal padiwa_sdo : std_logic;
+
+  --TDC
+  signal hit_in_i : std_logic_vector(63 downto 0);
+
+begin
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+  GSR_N <= pll_lock;
+
+  THE_RESET_HANDLER : trb_net_reset_handler
+    generic map(
+      RESET_DELAY => x"FEEE"
+      )
+    port map(
+      CLEAR_IN      => '0',              -- reset input (high active, async)
+      CLEAR_N_IN    => '1',              -- reset input (low active, async)
+      CLK_IN        => clk_200_internal, -- raw master clock, NOT from PLL/DLL!
+      SYSCLK_IN     => clk_100_i,        -- PLL/DLL remastered clock
+      PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
+      RESET_IN      => '0',              -- general reset signal (SYSCLK)
+      TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
+      CLEAR_OUT     => clear_i,          -- async reset out, USE WITH CARE!
+      RESET_OUT     => reset_i,          -- synchronous reset out (SYSCLK)
+      DEBUG_OUT     => open
+      );  
+
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+
+  THE_MAIN_PLL : pll_in200_out100
+    port map(
+      CLK   => CLK_GPLL_RIGHT,
+      CLKOP => clk_100_internal,
+      CLKOK => clk_200_internal,
+      LOCK  => pll_lock
+      );
+
+  gen_sync_clocks : if SYNC_MODE = c_YES generate
+    clk_100_i <= rx_clock_100;
+    clk_200_i <= rx_clock_200;
+    clk_tdc   <= rx_clock_200;
+  end generate;
+
+  gen_local_clocks : if SYNC_MODE = c_NO generate
+    clk_100_i <= clk_100_internal;
+    clk_200_i <= clk_200_internal;
+    clk_tdc   <= CLK_PCLK_LEFT;
+  end generate;
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+  THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+    generic map(
+      SERDES_NUM  => 1,     --number of serdes in quad
+      EXT_CLOCK   => c_NO,  --use internal clock
+      USE_200_MHZ => c_YES, --run on 200 MHz clock
+      USE_CTC     => c_NO,
+      USE_SLAVE   => SYNC_MODE
+      )      
+    port map(
+      CLK                => clk_200_internal,
+      SYSCLK             => clk_100_i,
+      RESET              => reset_i,
+      CLEAR              => clear_i,
+      CLK_EN             => '1',
+      --Internal Connection
+      MED_DATA_IN        => med_data_out,
+      MED_PACKET_NUM_IN  => med_packet_num_out,
+      MED_DATAREADY_IN   => med_dataready_out,
+      MED_READ_OUT       => med_read_in,
+      MED_DATA_OUT       => med_data_in,
+      MED_PACKET_NUM_OUT => med_packet_num_in,
+      MED_DATAREADY_OUT  => med_dataready_in,
+      MED_READ_IN        => med_read_out,
+      REFCLK2CORE_OUT    => open,
+      CLK_RX_HALF_OUT    => rx_clock_100,
+      CLK_RX_FULL_OUT    => rx_clock_200,
+      
+      --SFP Connection
+      SD_RXD_P_IN        => SERDES_RX(2),
+      SD_RXD_N_IN        => SERDES_RX(3),
+      SD_TXD_P_OUT       => SERDES_TX(2),
+      SD_TXD_N_OUT       => SERDES_TX(3),
+      SD_REFCLK_P_IN     => open,
+      SD_REFCLK_N_IN     => open,
+      SD_PRSNT_N_IN      => FPGA5_COMM(0),
+      SD_LOS_IN          => FPGA5_COMM(0),
+      SD_TXDIS_OUT       => FPGA5_COMM(2),
+      
+      SCI_DATA_IN        => sci1_data_in,
+      SCI_DATA_OUT       => sci1_data_out,
+      SCI_ADDR           => sci1_addr,
+      SCI_READ           => sci1_read,
+      SCI_WRITE          => sci1_write,
+      SCI_ACK            => sci1_ack,        
+      -- Status and control port
+      STAT_OP            => med_stat_op,
+      CTRL_OP            => med_ctrl_op,
+      STAT_DEBUG         => med_stat_debug,
+      CTRL_DEBUG         => (others => '0')
+      );
+
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+  THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+    generic map(
+      REGIO_NUM_STAT_REGS       => REGIO_NUM_STAT_REGS,  --4,    --16 stat reg
+      REGIO_NUM_CTRL_REGS       => REGIO_NUM_CTRL_REGS,  --3,    --8 cotrol reg
+      ADDRESS_MASK              => x"FFFF",
+      BROADCAST_BITMASK         => x"FF",
+      BROADCAST_SPECIAL_ADDR    => x"48",
+      REGIO_COMPILE_TIME        => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+      REGIO_HARDWARE_VERSION    => x"91004120",
+      REGIO_INIT_ADDRESS        => x"f306",
+      REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+      CLOCK_FREQUENCY           => 100,
+      TIMING_TRIGGER_RAW        => c_YES,
+      --Configure data handler
+      DATA_INTERFACE_NUMBER     => 1,
+      DATA_BUFFER_DEPTH         => 13,  --13
+      DATA_BUFFER_WIDTH         => 32,
+      DATA_BUFFER_FULL_THRESH   => 2**13-800,
+      TRG_RELEASE_AFTER_DATA    => c_YES,
+      HEADER_BUFFER_DEPTH       => 9,
+      HEADER_BUFFER_FULL_THRESH => 2**9-16
+      )
+    port map(
+      CLK                => clk_100_i,
+      RESET              => reset_i,
+      CLK_EN             => '1',
+      MED_DATAREADY_OUT  => med_dataready_out,  -- open, --
+      MED_DATA_OUT       => med_data_out,  -- open, --
+      MED_PACKET_NUM_OUT => med_packet_num_out,  -- open, --
+      MED_READ_IN        => med_read_in,
+      MED_DATAREADY_IN   => med_dataready_in,
+      MED_DATA_IN        => med_data_in,
+      MED_PACKET_NUM_IN  => med_packet_num_in,
+      MED_READ_OUT       => med_read_out,  -- open, --
+      MED_STAT_OP_IN     => med_stat_op,
+      MED_CTRL_OP_OUT    => med_ctrl_op,
+
+      --Timing trigger in
+      TRG_TIMING_TRG_RECEIVED_IN  => timing_trg_received_i,
+      --LVL1 trigger to FEE
+      LVL1_TRG_DATA_VALID_OUT     => trg_data_valid_i,
+      LVL1_VALID_TIMING_TRG_OUT   => trg_timing_valid_i,
+      LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
+      LVL1_INVALID_TRG_OUT        => trg_invalid_i,
+
+      LVL1_TRG_TYPE_OUT        => trg_type_i,
+      LVL1_TRG_NUMBER_OUT      => trg_number_i,
+      LVL1_TRG_CODE_OUT        => trg_code_i,
+      LVL1_TRG_INFORMATION_OUT => trg_information_i,
+      LVL1_INT_TRG_NUMBER_OUT  => trg_int_number_i,
+
+      --Information about trigger handler errors
+      TRG_MULTIPLE_TRG_OUT     => trg_multiple_trg_i,
+      TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
+      TRG_SPURIOUS_TRG_OUT     => trg_spurious_trg_i,
+      TRG_MISSING_TMG_TRG_OUT  => trg_missing_tmg_trg_i,
+      TRG_SPIKE_DETECTED_OUT   => trg_spike_detected_i,
+
+      --Response from FEE
+      FEE_TRG_RELEASE_IN(0)       => fee_trg_release_i,
+      FEE_TRG_STATUSBITS_IN       => fee_trg_statusbits_i,
+      FEE_DATA_IN                 => fee_data_i,
+      FEE_DATA_WRITE_IN(0)        => fee_data_write_i,
+      FEE_DATA_FINISHED_IN(0)     => fee_data_finished_i,
+      FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,
+
+      -- Slow Control Data Port
+      REGIO_COMMON_STAT_REG_IN           => common_stat_reg,  --0x00
+      REGIO_COMMON_CTRL_REG_OUT          => common_ctrl_reg,  --0x20
+      REGIO_COMMON_STAT_STROBE_OUT       => common_stat_reg_strobe,
+      REGIO_COMMON_CTRL_STROBE_OUT       => common_ctrl_reg_strobe,
+      REGIO_STAT_REG_IN                  => stat_reg,         --start 0x80
+      REGIO_CTRL_REG_OUT                 => ctrl_reg,         --start 0xc0
+      REGIO_STAT_STROBE_OUT              => stat_reg_strobe,
+      REGIO_CTRL_STROBE_OUT              => ctrl_reg_strobe,
+      REGIO_VAR_ENDPOINT_ID(1 downto 0)  => CODE_LINE,
+      REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+      BUS_ADDR_OUT         => regio_addr_out,
+      BUS_READ_ENABLE_OUT  => regio_read_enable_out,
+      BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+      BUS_DATA_OUT         => regio_data_out,
+      BUS_DATA_IN          => regio_data_in,
+      BUS_DATAREADY_IN     => regio_dataready_in,
+      BUS_NO_MORE_DATA_IN  => regio_no_more_data_in,
+      BUS_WRITE_ACK_IN     => regio_write_ack_in,
+      BUS_UNKNOWN_ADDR_IN  => regio_unknown_addr_in,
+      BUS_TIMEOUT_OUT      => regio_timeout_out,
+      ONEWIRE_INOUT        => TEMPSENS,
+      ONEWIRE_MONITOR_OUT  => open,
+
+      TIME_GLOBAL_OUT         => global_time,
+      TIME_LOCAL_OUT          => local_time,
+      TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+      TIME_TICKS_OUT          => timer_ticks,
+
+      STAT_DEBUG_IPU              => open,
+      STAT_DEBUG_1                => open,
+      STAT_DEBUG_2                => open,
+      STAT_DEBUG_DATA_HANDLER_OUT => open,
+      STAT_DEBUG_IPU_HANDLER_OUT  => open,
+      STAT_TRIGGER_OUT            => open,
+      CTRL_MPLEX                  => (others => '0'),
+      IOBUF_CTRL_GEN              => (others => '0'),
+      STAT_ONEWIRE                => open,
+      STAT_ADDR_DEBUG             => open,
+      DEBUG_LVL1_HANDLER_OUT      => open
+      );
+
+---------------------------------------------------------------------------
+-- I/O
+---------------------------------------------------------------------------
+  timing_trg_received_i <= TRIGGER_LEFT;
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+  THE_BUS_HANDLER : trb_net16_regio_bus_handler
+    generic map(
+      PORT_NUMBER    => 8,
+      PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"b000", others => x"0000"),
+      PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 9, others => 0)
+      )
+    port map(
+      CLK   => clk_100_i,
+      RESET => reset_i,
+
+      DAT_ADDR_IN          => regio_addr_out,
+      DAT_DATA_IN          => regio_data_out,
+      DAT_DATA_OUT         => regio_data_in,
+      DAT_READ_ENABLE_IN   => regio_read_enable_out,
+      DAT_WRITE_ENABLE_IN  => regio_write_enable_out,
+      DAT_TIMEOUT_IN       => regio_timeout_out,
+      DAT_DATAREADY_OUT    => regio_dataready_in,
+      DAT_WRITE_ACK_OUT    => regio_write_ack_in,
+      DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+      DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+      --Bus Handler (SPI CTRL)
+      BUS_READ_ENABLE_OUT(0)              => spictrl_read_en,
+      BUS_WRITE_ENABLE_OUT(0)             => spictrl_write_en,
+      BUS_DATA_OUT(0*32+31 downto 0*32)   => spictrl_data_in,
+      BUS_ADDR_OUT(0*16)                  => spictrl_addr,
+      BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
+      BUS_TIMEOUT_OUT(0)                  => open,
+      BUS_DATA_IN(0*32+31 downto 0*32)    => spictrl_data_out,
+      BUS_DATAREADY_IN(0)                 => spictrl_ack,
+      BUS_WRITE_ACK_IN(0)                 => spictrl_ack,
+      BUS_NO_MORE_DATA_IN(0)              => spictrl_busy,
+      BUS_UNKNOWN_ADDR_IN(0)              => '0',
+      --Bus Handler (SPI Memory)
+      BUS_READ_ENABLE_OUT(1)              => spimem_read_en,
+      BUS_WRITE_ENABLE_OUT(1)             => spimem_write_en,
+      BUS_DATA_OUT(1*32+31 downto 1*32)   => spimem_data_in,
+      BUS_ADDR_OUT(1*16+5 downto 1*16)    => spimem_addr,
+      BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
+      BUS_TIMEOUT_OUT(1)                  => open,
+      BUS_DATA_IN(1*32+31 downto 1*32)    => spimem_data_out,
+      BUS_DATAREADY_IN(1)                 => spimem_ack,
+      BUS_WRITE_ACK_IN(1)                 => spimem_ack,
+      BUS_NO_MORE_DATA_IN(1)              => '0',
+      BUS_UNKNOWN_ADDR_IN(1)              => '0',
+      --DAC
+      BUS_READ_ENABLE_OUT(2)              => dac_read_en,
+      BUS_WRITE_ENABLE_OUT(2)             => dac_write_en,
+      BUS_DATA_OUT(2*32+31 downto 2*32)   => dac_data_in,
+      BUS_ADDR_OUT(2*16+4 downto 2*16)    => dac_addr,
+      BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open,
+      BUS_TIMEOUT_OUT(2)                  => open,
+      BUS_DATA_IN(2*32+31 downto 2*32)    => dac_data_out,
+      BUS_DATAREADY_IN(2)                 => dac_ack,
+      BUS_WRITE_ACK_IN(2)                 => dac_ack,
+      BUS_NO_MORE_DATA_IN(2)              => dac_busy,
+      BUS_UNKNOWN_ADDR_IN(2)              => '0',
+
+      --HitRegisters
+      BUS_READ_ENABLE_OUT(3)              => hitreg_read_en,
+      BUS_WRITE_ENABLE_OUT(3)             => hitreg_write_en,
+      BUS_DATA_OUT(3*32+31 downto 3*32)   => open,
+      BUS_ADDR_OUT(3*16+6 downto 3*16)    => hitreg_addr,
+      BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open,
+      BUS_TIMEOUT_OUT(3)                  => open,
+      BUS_DATA_IN(3*32+31 downto 3*32)    => hitreg_data_out,
+      BUS_DATAREADY_IN(3)                 => hitreg_data_ready,
+      BUS_WRITE_ACK_IN(3)                 => '0',
+      BUS_NO_MORE_DATA_IN(3)              => '0',
+      BUS_UNKNOWN_ADDR_IN(3)              => hitreg_invalid,
+      --Status Registers
+      BUS_READ_ENABLE_OUT(4)              => srb_read_en,
+      BUS_WRITE_ENABLE_OUT(4)             => srb_write_en,
+      BUS_DATA_OUT(4*32+31 downto 4*32)   => open,
+      BUS_ADDR_OUT(4*16+6 downto 4*16)    => srb_addr,
+      BUS_ADDR_OUT(4*16+15 downto 4*16+7) => open,
+      BUS_TIMEOUT_OUT(4)                  => open,
+      BUS_DATA_IN(4*32+31 downto 4*32)    => srb_data_out,
+      BUS_DATAREADY_IN(4)                 => srb_data_ready,
+      BUS_WRITE_ACK_IN(4)                 => '0',
+      BUS_NO_MORE_DATA_IN(4)              => '0',
+      BUS_UNKNOWN_ADDR_IN(4)              => srb_invalid,
+      --Encoder Start Registers
+      BUS_READ_ENABLE_OUT(5)              => esb_read_en,
+      BUS_WRITE_ENABLE_OUT(5)             => esb_write_en,
+      BUS_DATA_OUT(5*32+31 downto 5*32)   => open,
+      BUS_ADDR_OUT(5*16+6 downto 5*16)    => esb_addr,
+      BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open,
+      BUS_TIMEOUT_OUT(5)                  => open,
+      BUS_DATA_IN(5*32+31 downto 5*32)    => esb_data_out,
+      BUS_DATAREADY_IN(5)                 => esb_data_ready,
+      BUS_WRITE_ACK_IN(5)                 => '0',
+      BUS_NO_MORE_DATA_IN(5)              => '0',
+      BUS_UNKNOWN_ADDR_IN(5)              => esb_invalid,
+      --Fifo Write Registers
+      BUS_READ_ENABLE_OUT(6)              => fwb_read_en,
+      BUS_WRITE_ENABLE_OUT(6)             => fwb_write_en,
+      BUS_DATA_OUT(6*32+31 downto 6*32)   => open,
+      BUS_ADDR_OUT(6*16+6 downto 6*16)    => fwb_addr,
+      BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open,
+      BUS_TIMEOUT_OUT(6)                  => open,
+      BUS_DATA_IN(6*32+31 downto 6*32)    => fwb_data_out,
+      BUS_DATAREADY_IN(6)                 => fwb_data_ready,
+      BUS_WRITE_ACK_IN(6)                 => '0',
+      BUS_NO_MORE_DATA_IN(6)              => '0',
+      BUS_UNKNOWN_ADDR_IN(6)              => fwb_invalid,
+      --SCI first Media Interface
+      BUS_READ_ENABLE_OUT(7)              => sci1_read,
+      BUS_WRITE_ENABLE_OUT(7)             => sci1_write,
+      BUS_DATA_OUT(7*32+7 downto 7*32)    => sci1_data_in,
+      BUS_DATA_OUT(7*32+31 downto 7*32+8) => open,
+      BUS_ADDR_OUT(7*16+8 downto 7*16)    => sci1_addr,
+      BUS_ADDR_OUT(7*16+15 downto 7*16+9) => open,
+      BUS_TIMEOUT_OUT(7)                  => open,
+      BUS_DATA_IN(7*32+7 downto 7*32)     => sci1_data_out,
+      BUS_DATAREADY_IN(7)                 => sci1_ack,
+      BUS_WRITE_ACK_IN(7)                 => sci1_ack,
+      BUS_NO_MORE_DATA_IN(7)              => '0',
+      BUS_UNKNOWN_ADDR_IN(7)              => '0',
+      STAT_DEBUG => open
+      );
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+
+  THE_SPI_MASTER : spi_master
+    port map(
+      CLK_IN         => clk_100_i,
+      RESET_IN       => reset_i,
+      -- Slave bus
+      BUS_READ_IN    => spictrl_read_en,
+      BUS_WRITE_IN   => spictrl_write_en,
+      BUS_BUSY_OUT   => spictrl_busy,
+      BUS_ACK_OUT    => spictrl_ack,
+      BUS_ADDR_IN(0) => spictrl_addr,
+      BUS_DATA_IN    => spictrl_data_in,
+      BUS_DATA_OUT   => spictrl_data_out,
+      -- SPI connections
+      SPI_CS_OUT     => FLASH_CS,
+      SPI_SDI_IN     => FLASH_DOUT,
+      SPI_SDO_OUT    => FLASH_DIN,
+      SPI_SCK_OUT    => FLASH_CLK,
+      -- BRAM for read/write data
+      BRAM_A_OUT     => spi_bram_addr,
+      BRAM_WR_D_IN   => spi_bram_wr_d,
+      BRAM_RD_D_OUT  => spi_bram_rd_d,
+      BRAM_WE_OUT    => spi_bram_we,
+      -- Status lines
+      STAT           => open
+      );
+
+-- data memory for SPI accesses
+  THE_SPI_MEMORY : spi_databus_memory
+    port map(
+      CLK_IN        => clk_100_i,
+      RESET_IN      => reset_i,
+      -- Slave bus
+      BUS_ADDR_IN   => spimem_addr,
+      BUS_READ_IN   => spimem_read_en,
+      BUS_WRITE_IN  => spimem_write_en,
+      BUS_ACK_OUT   => spimem_ack,
+      BUS_DATA_IN   => spimem_data_in,
+      BUS_DATA_OUT  => spimem_data_out,
+      -- state machine connections
+      BRAM_ADDR_IN  => spi_bram_addr,
+      BRAM_WR_D_OUT => spi_bram_wr_d,
+      BRAM_RD_D_IN  => spi_bram_rd_d,
+      BRAM_WE_IN    => spi_bram_we,
+      -- Status lines
+      STAT          => open
+      );
+
+---------------------------------------------------------------------------
+-- DAC
+---------------------------------------------------------------------------      
+  THE_DAC_SPI : spi_ltc2600
+    port map(
+      CLK_IN                 => clk_100_i,
+      RESET_IN               => reset_i,
+      -- Slave bus
+      BUS_ADDR_IN            => dac_addr,
+      BUS_READ_IN            => dac_read_en,
+      BUS_WRITE_IN           => dac_write_en,
+      BUS_ACK_OUT            => dac_ack,
+      BUS_BUSY_OUT           => dac_busy,
+      BUS_DATA_IN            => dac_data_in,
+      BUS_DATA_OUT           => dac_data_out,
+      -- SPI connections
+      SPI_CS_OUT(3 downto 0) => padiwa_cs,
+      SPI_SDI_IN             => padiwa_sdi,
+      SPI_SDO_OUT            => padiwa_sdo,
+      SPI_SCK_OUT            => padiwa_sck
+      );
+
+
+  OUT_CS     <= padiwa_cs(3 downto 0);
+  OUT_SCK    <= padiwa_sck & padiwa_sck & padiwa_sck & padiwa_sck;
+  OUT_SDO    <= padiwa_sdo & padiwa_sdo & padiwa_sdo & padiwa_sdo;
+  padiwa_sdi <= or_all(IN_SDI and not padiwa_cs(3 downto 0));
+
+---------------------------------------------------------------------------
+-- Reboot FPGA
+---------------------------------------------------------------------------
+  THE_FPGA_REBOOT : fpga_reboot
+    port map(
+      CLK       => clk_100_i,
+      RESET     => reset_i,
+      DO_REBOOT => common_ctrl_reg(15),
+      PROGRAMN  => PROGRAMN
+      );
+
+
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+  LED_ORANGE <= not reset_i when rising_edge(clk_100_internal);
+  LED_YELLOW <= '1';
+  LED_GREEN  <= not med_stat_op(9);
+  LED_RED    <= not (med_stat_op(10) or med_stat_op(11));
+
+---------------------------------------------------------------------------
+-- Test Connector
+---------------------------------------------------------------------------    
+--  TEST_LINE(15 downto 0) <= (others => '0');
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+  process
+    begin
+      wait until rising_edge(clk_100_internal);
+      time_counter <= time_counter + 1;
+    end process;
+
+
+
+-------------------------------------------------------------------------------
+-- TDC
+-------------------------------------------------------------------------------
+  THE_TDC : TDC
+    generic map (
+      CHANNEL_NUMBER => 5,             -- Number of TDC channels
+      STATUS_REG_NR  => REGIO_NUM_STAT_REGS,
+      CONTROL_REG_NR => REGIO_NUM_CTRL_REGS)
+    port map (
+      RESET                 => reset_i,
+      CLK_TDC               => clk_tdc,  -- Clock used for the time measurement
+      CLK_READOUT           => clk_100_i,   -- Clock for the readout
+      REFERENCE_TIME        => timing_trg_received_i,  -- Reference time input
+      HIT_IN                => hit_in_i(3 downto 0),  -- Channel start signals
+      TRG_WIN_PRE           => ctrl_reg(42 downto 32),  -- Pre-Trigger window width
+      TRG_WIN_POST          => ctrl_reg(58 downto 48),  -- Post-Trigger window width
+      --
+      -- Trigger signals from handler
+      TRG_DATA_VALID_IN     => trg_data_valid_i,  -- trig data valid signal from trbnet
+      VALID_TIMING_TRG_IN   => trg_timing_valid_i,  -- valid timing trigger signal from trbnet
+      VALID_NOTIMING_TRG_IN => trg_notiming_valid_i,  -- valid notiming signal from trbnet
+      INVALID_TRG_IN        => trg_invalid_i,  -- invalid trigger signal from trbnet
+      TMGTRG_TIMEOUT_IN     => trg_timeout_detected_i,  -- timing trigger timeout signal from trbnet
+      SPIKE_DETECTED_IN     => trg_spike_detected_i,
+      MULTI_TMG_TRG_IN      => trg_multiple_trg_i,
+      SPURIOUS_TRG_IN       => trg_spurious_trg_i,
+      --
+      TRG_NUMBER_IN         => trg_number_i,  -- LVL1 trigger information package
+      TRG_CODE_IN           => trg_code_i,  --
+      TRG_INFORMATION_IN    => trg_information_i,   --
+      TRG_TYPE_IN           => trg_type_i,  -- LVL1 trigger information package
+      --
+      --Response to handler
+      TRG_RELEASE_OUT       => fee_trg_release_i,   -- trigger release signal
+      TRG_STATUSBIT_OUT     => fee_trg_statusbits_i,  -- status information of the tdc
+      DATA_OUT              => fee_data_i,  -- tdc data
+      DATA_WRITE_OUT        => fee_data_write_i,  -- data valid signal
+      DATA_FINISHED_OUT     => fee_data_finished_i,  -- readout finished signal
+      --
+      --Hit Counter Bus
+      HCB_READ_EN_IN        => hitreg_read_en,    -- bus read en strobe
+      HCB_WRITE_EN_IN       => hitreg_write_en,   -- bus write en strobe
+      HCB_ADDR_IN           => hitreg_addr,   -- bus address
+      HCB_DATA_OUT          => hitreg_data_out,   -- bus data
+      HCB_DATAREADY_OUT     => hitreg_data_ready,   -- bus data ready strobe
+      HCB_UNKNOWN_ADDR_OUT  => hitreg_invalid,    -- bus invalid addr
+      --Status Registers Bus
+      SRB_READ_EN_IN        => srb_read_en,   -- bus read en strobe
+      SRB_WRITE_EN_IN       => srb_write_en,  -- bus write en strobe
+      SRB_ADDR_IN           => srb_addr,    -- bus address
+      SRB_DATA_OUT          => srb_data_out,  -- bus data
+      SRB_DATAREADY_OUT     => srb_data_ready,    -- bus data ready strobe
+      SRB_UNKNOWN_ADDR_OUT  => srb_invalid,   -- bus invalid addr
+      --Encoder Start Registers Bus
+      ESB_READ_EN_IN        => esb_read_en,   -- bus read en strobe
+      ESB_WRITE_EN_IN       => esb_write_en,  -- bus write en strobe
+      ESB_ADDR_IN           => esb_addr,    -- bus address
+      ESB_DATA_OUT          => esb_data_out,  -- bus data
+      ESB_DATAREADY_OUT     => esb_data_ready,    -- bus data ready strobe
+      ESB_UNKNOWN_ADDR_OUT  => esb_invalid,   -- bus invalid addr
+      --Fifo Write Registers Bus
+      FWB_READ_EN_IN        => fwb_read_en,   -- bus read en strobe
+      FWB_WRITE_EN_IN       => fwb_write_en,  -- bus write en strobe
+      FWB_ADDR_IN           => fwb_addr,    -- bus address
+      FWB_DATA_OUT          => fwb_data_out,  -- bus data
+      FWB_DATAREADY_OUT     => fwb_data_ready,    -- bus data ready strobe
+      FWB_UNKNOWN_ADDR_OUT  => fwb_invalid,   -- bus invalid addr
+      --Lost Hit Registers Bus
+      LHB_READ_EN_IN        => '0', -- lhb_read_en,   -- bus read en strobe
+      LHB_WRITE_EN_IN       => '0', -- lhb_write_en,  -- bus write en strobe
+      LHB_ADDR_IN           => (others => '0'), -- lhb_addr,    -- bus address
+      LHB_DATA_OUT          => open, -- lhb_data_out,  -- bus data
+      LHB_DATAREADY_OUT     => open, -- lhb_data_ready,    -- bus data ready strobe
+      LHB_UNKNOWN_ADDR_OUT  => open, -- lhb_invalid,   -- bus invalid addr
+      --
+      LOGIC_ANALYSER_OUT    => TEST_LINE,
+      CONTROL_REG_IN        => ctrl_reg);
+
+
+  hit_in_i <= INP;
+
+  --Gen_Hit_In_Signals : for i in 0 to 31 generate
+  -- hit_in_i(i*2)     <= INP(i);
+  -- hit_in_i(i*2+1)   <= not INP(i);
+  --end generate Gen_Hit_In_Signals;
+
+
+end architecture;
diff --git a/soda_source/version.vhd b/soda_source/version.vhd
new file mode 100644 (file)
index 0000000..1bf4caf
--- /dev/null
@@ -0,0 +1,13 @@
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+    constant VERSION_NUMBER_TIME  : integer   := 1358442567;
+
+end package version;