*** empty log message ***

diff --git a/.cvsignore b/.cvsignore
new file mode 100644 (file)
index 0000000..8f9fbc7
--- /dev/null
+++ b/.cvsignore
@@ -0,0 +1,5 @@
+shower_fpga*
+*.log
+*.rpt
+version.vhd
+*.log

diff --git a/README b/README
index 8951213bb4dacb513591658d37291e95df1be20d..3276defeac59f221664ae0bb8ad62f8f627b4dae 100644 (file)
--- a/README
+++ b/README
@@ -1,23 +1,61 @@
 ====================
-== CVS Organization
+== 0. Content
 ====================
-base           Here the main files like entity templates and pin-out files are stored. 
-fpgatest       Designs used during hardware testing go here
-central_hub2   The central hub design for TRBnetv2 goes here
+
+== 1. CVS Organization / File list
+== 2. Design Files & FLASH ROMs
+== 3. Network addresses generic settings for TrbNet
+
 
 
 ====================
-== Design Files
+== 1. CVS Organization / File list
 ====================
+base                           Here the main files like entity templates and pin-out files are stored. 
+base/cores              All IP-cores specific to the TRB3 that will be used in more than one project, e.g. PLLs
+fpgatest                     Designs used during hardware testing
+central_hub2             The central hub design for TRBnetv2
+
+
+
+=== Files to copy & change for new projects (COPY, CHANGE & USE)
+
+base/trb3_central.vhd               Basic design for central FPGA
+base/trb3_periph.vhd                Basic design for central FPGA
+base/constraints_trb3_central.lpf   Constraints for each specific design of trb3_central
+base/constraints_trb3_periph.lpf    Constraints for each specific design of trb3_peripheral
+
+base/compile_central_frankfurt.pl   Generic compile script for central FPGA using paths for Frankfurt set-up
+base/compile_central_gsi.pl         Generic compile script for central FPGA using paths for GSI set-up
+base/compile_periph_frankfurt.pl    Generic compile script for peripheral FPGA using paths for Frankfurt set-up
+base/compile_periph_gsi.pl          Generic compile script for peripheral FPGA using paths for GSI set-up
+
+
+
+=== Files to change directly for all projects (NO COPY)
+
+base/trb3_components.vhd            All VHDL components special for TRB3 used in any design should 
+                                    be listed in here
+
+
+=== Files not to change at all (NO CHANGE)
+
+base/trb3_central.lpf               Pin-out for central FPGA
+
 
-In general, there should be two designs: One for the central FPGA, one for the peripheral FPGA. If necessary, designs for each of the peripheral FPGA can be defined. I.e. six different cases of design files are listed for each of the settings below.
 
 
 ====================
-== FLASH ROMs
+== 2. Design Files & FLASH ROMs
 ====================
 
-To run TRBnet and especially to operate the Flash ROMs to store the FPGA designs, several settings have to be present in each design:
+
+In general, there should be two designs: One for the central FPGA, one for the peripheral FPGA. 
+If necessary, designs for each of the peripheral FPGA can be defined. I.e. six different cases 
+of design files are listed for each of the settings below.
+
+To run TRBnet and especially to operate the Flash ROMs to store the FPGA designs, several settings 
+have to be present in each design:
 
 The filename must contain a substring according to the FPGA the design belongs to:
 - trb3_central or trb3_fpga5   : designs for the central FPGA
@@ -36,8 +74,12 @@ The upper 16 bit of the REGIO_HARDWARE_VERSION generic of the TrbNet endpoint ha
 - 0x9130  for FPGA 3 only
 - 0x9140  for FPGA 4 only
 
+
+
+
+
 ====================
-== Network addresses
+== 3. Network addresses generic settings for TrbNet
 ====================
 
 REGIO_INIT_ADDRESS gives the default network address

diff --git a/base/.cvsignore b/base/.cvsignore
new file mode 100644 (file)
index 0000000..8f9fbc7
--- /dev/null
+++ b/base/.cvsignore
@@ -0,0 +1,5 @@
+shower_fpga*
+*.log
+*.rpt
+version.vhd
+*.log

diff --git a/base/cores/.cvsignore b/base/cores/.cvsignore
new file mode 100644 (file)
index 0000000..8f9fbc7
--- /dev/null
+++ b/base/cores/.cvsignore
@@ -0,0 +1,5 @@
+shower_fpga*
+*.log
+*.rpt
+version.vhd
+*.log

diff --git a/base/trb3_central.lpf b/base/trb3_central.lpf
new file mode 100644 (file)
index 0000000..20e8334
--- /dev/null
+++ b/base/trb3_central.lpf
@@ -0,0 +1,548 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+
+#################################################################
+# Clock I/O
+#################################################################
+
+#Additional signals from Clock-RJ-45
+LOCATE COMP  "CLK_EXT_3"   SITE "U9";  #was SPARE_LINE_2
+LOCATE COMP  "CLK_EXT_4"   SITE "Y34"; #was SPARE_LINE_4
+LOCATE COMP  "CLK_SERDES_INT_RIGHT" SITE "AH22"; 
+LOCATE COMP  "CLK_SERDES_INT_LEFT"  SITE "AH12";
+LOCATE COMP  "CLK_GPLL_RIGHT"       SITE "Y28";
+LOCATE COMP  "CLK_GPLL_LEFT"        SITE "Y9";
+LOCATE COMP  "CLK_PCLK_LEFT"   SITE "V9";
+LOCATE COMP  "CLK_PCLK_RIGHT"   SITE "U28";
+
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP  "CLK_group" IO_TYPE=LVDS25;
+
+LOCATE COMP  "ENPIRION_CLOCK" SITE "G18";
+IOBUF PORT   "ENPIRION_CLOCK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4;
+
+#################################################################
+# Trigger I/O
+#################################################################
+
+#Trigger from fan-out
+LOCATE COMP  "TRIGGER_RIGHT" SITE "W30";
+IOBUF  PORT  "TRIGGER_RIGHT" IO_TYPE=LVDS25  
+LOCATE COMP  "TRIGGER_LEFT"  SITE "Y2";
+IOBUF  PORT  "TRIGGER_LEFT"  IO_TYPE=LVDS25  
+
+#To fan-out to all FPGA
+LOCATE COMP  "TRIGGER_OUT"   SITE "V7";
+IOBUF  PORT  "TRIGGER_OUT"   IO_TYPE=LVDS25  
+
+#Additional lines on Trigger-RJ-45
+LOCATE COMP  "TRIGGER_EXT_2"   SITE "W2";
+LOCATE COMP  "TRIGGER_EXT_3"   SITE "W8"; #was EXT_TRIG_2
+LOCATE COMP  "TRIGGER_EXT_4"   SITE "W4"; #was EXT_TRIG_4
+DEFINE PORT GROUP "TRIGGER_EXT_group" "TRIGGER_EXT*" ;
+IOBUF GROUP  "TRIGGER_EXT_group" IO_TYPE=LVDS25;
+
+
+#################################################################
+# Clock and Trigger Select
+#################################################################
+#Trigger select for fan-out. 0: external trigger. 1: TRIGGER_OUT
+LOCATE COMP  "TRIGGER_SELECT" SITE "AA31";
+IOBUF  PORT  "TRIGGER_SELECT" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4  ;
+
+LOCATE COMP  "CLK_MNGR1_USER_0"   SITE "AA28";
+LOCATE COMP  "CLK_MNGR1_USER_1"   SITE "AA27";
+LOCATE COMP  "CLK_MNGR1_USER_2"   SITE "AB32";
+LOCATE COMP  "CLK_MNGR1_USER_3"   SITE "AB31";
+LOCATE COMP  "CLK_MNGR2_USER_0"   SITE "AE34";
+LOCATE COMP  "CLK_MNGR2_USER_1"   SITE "AE33";
+LOCATE COMP  "CLK_MNGR2_USER_2"   SITE "AB26";
+LOCATE COMP  "CLK_MNGR2_USER_3"   SITE "AB25";
+DEFINE PORT GROUP "CLK_MNGR_group" "CLK_MNGR*" ;
+IOBUF GROUP "CLK_MNGR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8;
+
+LOCATE COMP  "CLOCK_SELECT"   SITE "AA30";
+IOBUF  PORT  "CLOCK_SELECT" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4  ;
+
+#################################################################
+# LED
+#################################################################
+LOCATE COMP  "LED_CLOCK_GREEN"    SITE "AL4";
+LOCATE COMP  "LED_CLOCK_RED"      SITE "AM4";
+LOCATE COMP  "LED_GREEN"          SITE "A17";
+LOCATE COMP  "LED_ORANGE"         SITE "B17";
+LOCATE COMP  "LED_RED"            SITE "E19";
+LOCATE COMP  "LED_TRIGGER_GREEN"  SITE "AP5";
+LOCATE COMP  "LED_TRIGGER_RED"    SITE "AP6";
+LOCATE COMP  "LED_YELLOW"         SITE "E20";
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8;
+
+
+#################################################################
+# Inter-FPGA Connection
+#################################################################
+LOCATE COMP  "FPGA1_COMM_0"   SITE "AC9";
+LOCATE COMP  "FPGA1_COMM_10"  SITE "AJ1";
+LOCATE COMP  "FPGA1_COMM_11"  SITE "AK1";
+LOCATE COMP  "FPGA1_COMM_1"   SITE "AC8";
+LOCATE COMP  "FPGA1_COMM_2"   SITE "AE2";
+LOCATE COMP  "FPGA1_COMM_3"   SITE "AE1";
+LOCATE COMP  "FPGA1_COMM_4"   SITE "AE4";
+LOCATE COMP  "FPGA1_COMM_5"   SITE "AE3";
+LOCATE COMP  "FPGA1_COMM_6"   SITE "AB10";
+LOCATE COMP  "FPGA1_COMM_7"   SITE "AC10";
+LOCATE COMP  "FPGA1_COMM_8"   SITE "AD4";
+LOCATE COMP  "FPGA1_COMM_9"   SITE "AD3";
+
+LOCATE COMP  "FPGA2_COMM_0"   SITE "P5";
+LOCATE COMP  "FPGA2_COMM_10"  SITE "M10";
+LOCATE COMP  "FPGA2_COMM_11"  SITE "N10";
+LOCATE COMP  "FPGA2_COMM_1"   SITE "P4";
+LOCATE COMP  "FPGA2_COMM_2"   SITE "N8";
+LOCATE COMP  "FPGA2_COMM_3"   SITE "P8";
+LOCATE COMP  "FPGA2_COMM_4"   SITE "M5";
+LOCATE COMP  "FPGA2_COMM_5"   SITE "N5";
+LOCATE COMP  "FPGA2_COMM_6"   SITE "R7";
+LOCATE COMP  "FPGA2_COMM_7"   SITE "R5";
+LOCATE COMP  "FPGA2_COMM_8"   SITE "N2";
+LOCATE COMP  "FPGA2_COMM_9"   SITE "N1";
+
+LOCATE COMP  "FPGA3_COMM_0"   SITE "AC28";
+LOCATE COMP  "FPGA3_COMM_10"  SITE "AF32";
+LOCATE COMP  "FPGA3_COMM_11"  SITE "AF31";
+LOCATE COMP  "FPGA3_COMM_1"   SITE "AB27";
+LOCATE COMP  "FPGA3_COMM_2"   SITE "AE32";
+LOCATE COMP  "FPGA3_COMM_3"   SITE "AE31";
+LOCATE COMP  "FPGA3_COMM_4"   SITE "AE30";
+LOCATE COMP  "FPGA3_COMM_5"   SITE "AE29";
+LOCATE COMP  "FPGA3_COMM_6"   SITE "AC25";
+LOCATE COMP  "FPGA3_COMM_7"   SITE "AC26";
+LOCATE COMP  "FPGA3_COMM_8"   SITE "AD26";
+LOCATE COMP  "FPGA3_COMM_9"   SITE "AD25";
+
+LOCATE COMP  "FPGA4_COMM_0"   SITE "AN32";
+LOCATE COMP  "FPGA4_COMM_10"  SITE "AM29";
+LOCATE COMP  "FPGA4_COMM_11"  SITE "AN29";
+LOCATE COMP  "FPGA4_COMM_1"   SITE "AM32";
+LOCATE COMP  "FPGA4_COMM_2"   SITE "AP29";
+LOCATE COMP  "FPGA4_COMM_3"   SITE "AP30";
+LOCATE COMP  "FPGA4_COMM_4"   SITE "AL30";
+LOCATE COMP  "FPGA4_COMM_5"   SITE "AM30";
+LOCATE COMP  "FPGA4_COMM_6"   SITE "AL31";
+LOCATE COMP  "FPGA4_COMM_7"   SITE "AM31";
+LOCATE COMP  "FPGA4_COMM_8"   SITE "AP31";
+LOCATE COMP  "FPGA4_COMM_9"   SITE "AN31";
+
+LOCATE COMP  "FPGA1_CONNECTOR_0"    SITE "AN1";
+LOCATE COMP  "FPGA1_CONNECTOR_1"    SITE "AN2";
+LOCATE COMP  "FPGA1_CONNECTOR_2"    SITE "AD9";
+LOCATE COMP  "FPGA1_CONNECTOR_3"    SITE "AD8";
+LOCATE COMP  "FPGA1_CONNECTOR_4"    SITE "AP2";
+LOCATE COMP  "FPGA1_CONNECTOR_5"    SITE "AP3";
+LOCATE COMP  "FPGA1_CONNECTOR_6"    SITE "AJ2";
+LOCATE COMP  "FPGA1_CONNECTOR_7"    SITE "AJ3";
+
+LOCATE COMP  "FPGA2_CONNECTOR_0"    SITE "P9";
+LOCATE COMP  "FPGA2_CONNECTOR_1"    SITE "P10";
+LOCATE COMP  "FPGA2_CONNECTOR_2"    SITE "R2";
+LOCATE COMP  "FPGA2_CONNECTOR_3"    SITE "R1";
+LOCATE COMP  "FPGA2_CONNECTOR_4"    SITE "P7";
+LOCATE COMP  "FPGA2_CONNECTOR_5"    SITE "P6";
+LOCATE COMP  "FPGA2_CONNECTOR_6"    SITE "R4";
+LOCATE COMP  "FPGA2_CONNECTOR_7"    SITE "R3";
+
+LOCATE COMP  "FPGA3_CONNECTOR_0"    SITE "AN34";
+LOCATE COMP  "FPGA3_CONNECTOR_1"    SITE "AN33";
+LOCATE COMP  "FPGA3_CONNECTOR_2"    SITE "AH33";
+LOCATE COMP  "FPGA3_CONNECTOR_3"    SITE "AJ33";
+LOCATE COMP  "FPGA3_CONNECTOR_4"    SITE "AP33";
+LOCATE COMP  "FPGA3_CONNECTOR_5"    SITE "AP32";
+LOCATE COMP  "FPGA3_CONNECTOR_6"    SITE "AL34";
+LOCATE COMP  "FPGA3_CONNECTOR_7"    SITE "AL33";
+
+LOCATE COMP  "FPGA4_CONNECTOR_0"    SITE "AK27";
+LOCATE COMP  "FPGA4_CONNECTOR_1"    SITE "AJ27";
+LOCATE COMP  "FPGA4_CONNECTOR_2"    SITE "AK28";
+LOCATE COMP  "FPGA4_CONNECTOR_3"    SITE "AJ28";
+LOCATE COMP  "FPGA4_CONNECTOR_4"    SITE "AH27";
+LOCATE COMP  "FPGA4_CONNECTOR_5"    SITE "AH28";
+LOCATE COMP  "FPGA4_CONNECTOR_6"    SITE "AL29";
+LOCATE COMP  "FPGA4_CONNECTOR_7"    SITE "AK29";
+
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8;
+
+LOCATE COMP  "FPGA1_TTL_0"    SITE "J21";  #was F1_3V3_LINE etc.
+LOCATE COMP  "FPGA1_TTL_1"    SITE "H22";
+LOCATE COMP  "FPGA1_TTL_2"    SITE "A23";
+LOCATE COMP  "FPGA1_TTL_3"    SITE "B23";
+LOCATE COMP  "FPGA2_TTL_0"    SITE "E22";
+LOCATE COMP  "FPGA2_TTL_1"    SITE "E23";
+LOCATE COMP  "FPGA2_TTL_2"    SITE "C23";
+LOCATE COMP  "FPGA2_TTL_3"    SITE "D23";
+LOCATE COMP  "FPGA3_TTL_0"    SITE "K22";
+LOCATE COMP  "FPGA3_TTL_1"    SITE "K21";
+LOCATE COMP  "FPGA3_TTL_2"    SITE "A24";
+LOCATE COMP  "FPGA3_TTL_3"    SITE "B24";
+LOCATE COMP  "FPGA4_TTL_0"    SITE "G23";
+LOCATE COMP  "FPGA4_TTL_1"    SITE "H23";
+LOCATE COMP  "FPGA4_TTL_2"    SITE "D24";
+LOCATE COMP  "FPGA4_TTL_3"    SITE "E24";
+DEFINE PORT GROUP "FPGATTL_group" "*TTL*" ;
+IOBUF GROUP "TTL_group" IO_TYPE=LVTTL33 PULLMODE=DOWN DRIVE=8;
+
+#################################################################
+# SFP Control / Status
+#################################################################
+LOCATE COMP  "SFP_TX_FAULT_1"  SITE "K23";
+LOCATE COMP  "SFP_TX_FAULT_2"  SITE "D21";
+LOCATE COMP  "SFP_TX_FAULT_3"  SITE "H19";
+LOCATE COMP  "SFP_TX_FAULT_4"  SITE "A18";
+LOCATE COMP  "SFP_TX_FAULT_5"  SITE "D25";
+LOCATE COMP  "SFP_TX_FAULT_6"  SITE "D27";
+LOCATE COMP  "SFP_TX_FAULT_7"  SITE "D20";
+LOCATE COMP  "SFP_TX_FAULT_8"  SITE "J19";
+LOCATE COMP  "SFP_RATE_SEL_1"  SITE "C25";
+LOCATE COMP  "SFP_RATE_SEL_2"  SITE "J22";
+LOCATE COMP  "SFP_RATE_SEL_3"  SITE "D19";
+LOCATE COMP  "SFP_RATE_SEL_4"  SITE "G19";
+LOCATE COMP  "SFP_RATE_SEL_5"  SITE "C27";
+LOCATE COMP  "SFP_RATE_SEL_6"  SITE "A29";
+LOCATE COMP  "SFP_RATE_SEL_7"  SITE "E16";
+LOCATE COMP  "SFP_RATE_SEL_8"  SITE "C20";
+LOCATE COMP  "SFP_LOS_1"       SITE "K24";
+LOCATE COMP  "SFP_LOS_2"       SITE "E21";
+LOCATE COMP  "SFP_LOS_3"       SITE "A19";
+LOCATE COMP  "SFP_LOS_4"       SITE "B18";
+LOCATE COMP  "SFP_LOS_5"       SITE "G26";
+LOCATE COMP  "SFP_LOS_6"       SITE "E27";
+LOCATE COMP  "SFP_LOS_7"       SITE "F21";
+LOCATE COMP  "SFP_LOS_8"       SITE "K19";
+LOCATE COMP  "SFP_TXDIS_1"     SITE "A25";
+LOCATE COMP  "SFP_TXDIS_2"     SITE "H20";
+LOCATE COMP  "SFP_TXDIS_3"     SITE "B19";
+LOCATE COMP  "SFP_TXDIS_4"     SITE "J18";
+LOCATE COMP  "SFP_TXDIS_5"     SITE "G25";
+LOCATE COMP  "SFP_TXDIS_6"     SITE "B28";
+LOCATE COMP  "SFP_TXDIS_7"     SITE "F22";
+LOCATE COMP  "SFP_TXDIS_8"     SITE "A20";
+LOCATE COMP  "SFP_MOD0_1"      SITE "B25";
+LOCATE COMP  "SFP_MOD0_2"      SITE "J20";
+LOCATE COMP  "SFP_MOD0_3"      SITE "K20";
+LOCATE COMP  "SFP_MOD0_4"      SITE "H18";
+LOCATE COMP  "SFP_MOD0_5"      SITE "C26";
+LOCATE COMP  "SFP_MOD0_6"      SITE "A28";
+LOCATE COMP  "SFP_MOD0_7"      SITE "A21";
+LOCATE COMP  "SFP_MOD0_8"      SITE "B20";
+LOCATE COMP  "SFP_MOD1_1"      SITE "C28";
+LOCATE COMP  "SFP_MOD1_2"      SITE "A22";
+LOCATE COMP  "SFP_MOD1_3"      SITE "L19";
+LOCATE COMP  "SFP_MOD1_4"      SITE "D18";
+LOCATE COMP  "SFP_MOD1_5"      SITE "D26";
+LOCATE COMP  "SFP_MOD1_6"      SITE "A26";
+LOCATE COMP  "SFP_MOD1_7"      SITE "B21";
+LOCATE COMP  "SFP_MOD1_8"      SITE "G20";
+LOCATE COMP  "SFP_MOD2_1"      SITE "D28";
+LOCATE COMP  "SFP_MOD2_2"      SITE "B22";
+LOCATE COMP  "SFP_MOD2_3"      SITE "C19";
+LOCATE COMP  "SFP_MOD2_4"      SITE "E18";
+LOCATE COMP  "SFP_MOD2_5"      SITE "B27";
+LOCATE COMP  "SFP_MOD2_6"      SITE "A27";
+LOCATE COMP  "SFP_MOD2_7"      SITE "F16";
+LOCATE COMP  "SFP_MOD2_8"      SITE "G21";
+
+DEFINE PORT GROUP "SFP_group" "SFP*" ;
+IOBUF GROUP "SFP_group" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8;
+
+#################################################################
+# Main AddOn Connector 
+#################################################################
+
+LOCATE COMP  "ADDON_RESET"        SITE "J23";
+IOBUF  PORT "ADDON_RESET" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4  ;
+
+LOCATE COMP  "ADDON_TO_TRB_CLK"   SITE "J17";
+IOBUF  PORT "ADDON_TO_TRB_CLK" IO_TYPE=LVDS25  ;
+
+LOCATE COMP  "TRB_TO_ADDON_CLK"   SITE "K16";
+IOBUF  PORT "TRB_TO_ADDON_CLK" IO_TYPE=LVDS25  ;
+
+LOCATE COMP  "ADO_LV_0"   SITE "D5";
+LOCATE COMP  "ADO_LV_1"   SITE "C6";
+LOCATE COMP  "ADO_LV_2"   SITE "A4";
+LOCATE COMP  "ADO_LV_3"   SITE "A5";
+LOCATE COMP  "ADO_LV_4"   SITE "B4";
+LOCATE COMP  "ADO_LV_5"   SITE "A3";
+LOCATE COMP  "ADO_LV_6"   SITE "B3";
+LOCATE COMP  "ADO_LV_7"   SITE "A2";
+LOCATE COMP  "ADO_LV_8"   SITE "B1";
+LOCATE COMP  "ADO_LV_9"   SITE "B2";
+LOCATE COMP  "ADO_LV_10"  SITE "C3";
+LOCATE COMP  "ADO_LV_11"  SITE "C4";
+LOCATE COMP  "ADO_LV_12"  SITE "D3";
+LOCATE COMP  "ADO_LV_13"  SITE "C2";
+LOCATE COMP  "ADO_LV_14"  SITE "E4";
+LOCATE COMP  "ADO_LV_15"  SITE "D4";
+LOCATE COMP  "ADO_LV_16"  SITE "D6";
+LOCATE COMP  "ADO_LV_17"  SITE "C5";
+LOCATE COMP  "ADO_LV_18"  SITE "B6";
+LOCATE COMP  "ADO_LV_19"  SITE "A6";
+LOCATE COMP  "ADO_LV_20"  SITE "B7";
+LOCATE COMP  "ADO_LV_21"  SITE "A7";
+LOCATE COMP  "ADO_LV_22"  SITE "B8";
+LOCATE COMP  "ADO_LV_23"  SITE "C8";
+LOCATE COMP  "ADO_LV_24"  SITE "A8";
+LOCATE COMP  "ADO_LV_25"  SITE "A9";
+LOCATE COMP  "ADO_LV_26"  SITE "K11";
+LOCATE COMP  "ADO_LV_27"  SITE "J11";
+LOCATE COMP  "ADO_LV_28"  SITE "D12";
+LOCATE COMP  "ADO_LV_29"  SITE "E12";
+LOCATE COMP  "ADO_LV_30"  SITE "A12";
+LOCATE COMP  "ADO_LV_31"  SITE "B12";
+LOCATE COMP  "ADO_LV_32"  SITE "A11";
+LOCATE COMP  "ADO_LV_33"  SITE "B11";
+LOCATE COMP  "ADO_LV_34"  SITE "A10";
+LOCATE COMP  "ADO_LV_35"  SITE "B10";
+LOCATE COMP  "ADO_LV_36"  SITE "C11";
+LOCATE COMP  "ADO_LV_37"  SITE "D11";
+LOCATE COMP  "ADO_LV_38"  SITE "D9";
+LOCATE COMP  "ADO_LV_39"  SITE "C9";
+LOCATE COMP  "ADO_LV_40"  SITE "E11";
+LOCATE COMP  "ADO_LV_41"  SITE "F12";
+LOCATE COMP  "ADO_LV_42"  SITE "F10";
+LOCATE COMP  "ADO_LV_43"  SITE "E10";
+LOCATE COMP  "ADO_LV_44"  SITE "G11";
+LOCATE COMP  "ADO_LV_45"  SITE "G12";
+LOCATE COMP  "ADO_LV_46"  SITE "H11";
+LOCATE COMP  "ADO_LV_47"  SITE "H12";
+LOCATE COMP  "ADO_LV_48"  SITE "J14";
+LOCATE COMP  "ADO_LV_49"  SITE "H13";
+LOCATE COMP  "ADO_LV_50"  SITE "J12";
+LOCATE COMP  "ADO_LV_51"  SITE "K12";
+LOCATE COMP  "ADO_LV_52"  SITE "K13";
+LOCATE COMP  "ADO_LV_53"  SITE "J13";
+LOCATE COMP  "ADO_LV_54"  SITE "K14";
+LOCATE COMP  "ADO_LV_55"  SITE "K15";
+LOCATE COMP  "ADO_LV_56"  SITE "E13";
+LOCATE COMP  "ADO_LV_57"  SITE "F13";
+LOCATE COMP  "ADO_LV_58"  SITE "G13";
+LOCATE COMP  "ADO_LV_59"  SITE "H14";
+LOCATE COMP  "ADO_LV_60"  SITE "A13";
+LOCATE COMP  "ADO_LV_61"  SITE "B13";
+
+DEFINE PORT GROUP "ADO_LV_group" "ADO_LV*" ;
+IOBUF GROUP "ADO_LV_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8;
+
+
+LOCATE COMP  "ADO_TTL_0"    SITE "R26";
+LOCATE COMP  "ADO_TTL_1"    SITE "R25";
+LOCATE COMP  "ADO_TTL_2"    SITE "P26";
+LOCATE COMP  "ADO_TTL_3"    SITE "N26";
+LOCATE COMP  "ADO_TTL_4"    SITE "M25";
+LOCATE COMP  "ADO_TTL_5"    SITE "M26";
+LOCATE COMP  "ADO_TTL_6"    SITE "L26";
+LOCATE COMP  "ADO_TTL_7"    SITE "P28";
+LOCATE COMP  "ADO_TTL_8"    SITE "P27";
+LOCATE COMP  "ADO_TTL_9"    SITE "N27";
+LOCATE COMP  "ADO_TTL_10"   SITE "M27";
+LOCATE COMP  "ADO_TTL_11"   SITE "L28";
+LOCATE COMP  "ADO_TTL_12"   SITE "K29";
+LOCATE COMP  "ADO_TTL_13"   SITE "K30";
+LOCATE COMP  "ADO_TTL_14"   SITE "M28";
+LOCATE COMP  "ADO_TTL_15"   SITE "M29";
+LOCATE COMP  "ADO_TTL_16"   SITE "L33";
+LOCATE COMP  "ADO_TTL_17"   SITE "L32";
+LOCATE COMP  "ADO_TTL_18"   SITE "M30";
+LOCATE COMP  "ADO_TTL_19"   SITE "N32";
+LOCATE COMP  "ADO_TTL_20"   SITE "R27";
+LOCATE COMP  "ADO_TTL_21"   SITE "R28";
+LOCATE COMP  "ADO_TTL_22"   SITE "N28";
+LOCATE COMP  "ADO_TTL_23"   SITE "R29";
+LOCATE COMP  "ADO_TTL_24"   SITE "R30";
+LOCATE COMP  "ADO_TTL_25"   SITE "R31";
+LOCATE COMP  "ADO_TTL_26"   SITE "P32";
+LOCATE COMP  "ADO_TTL_27"   SITE "R34";
+LOCATE COMP  "ADO_TTL_28"   SITE "P33";
+LOCATE COMP  "ADO_TTL_29"   SITE "P34";
+LOCATE COMP  "ADO_TTL_30"   SITE "P30";
+LOCATE COMP  "ADO_TTL_31"   SITE "N34";
+LOCATE COMP  "ADO_TTL_32"   SITE "M34";
+LOCATE COMP  "ADO_TTL_33"   SITE "M31";
+LOCATE COMP  "ADO_TTL_34"   SITE "M33";
+LOCATE COMP  "ADO_TTL_35"   SITE "L34";
+LOCATE COMP  "ADO_TTL_36"   SITE "L31";
+LOCATE COMP  "ADO_TTL_37"   SITE "K34";
+LOCATE COMP  "ADO_TTL_38"   SITE "K33";
+LOCATE COMP  "ADO_TTL_39"   SITE "K32";
+LOCATE COMP  "ADO_TTL_40"   SITE "K31";
+LOCATE COMP  "ADO_TTL_41"   SITE "L30";
+LOCATE COMP  "ADO_TTL_42"   SITE "N33";
+LOCATE COMP  "ADO_TTL_43"   SITE "N30";
+LOCATE COMP  "ADO_TTL_44"   SITE "N29";
+LOCATE COMP  "ADO_TTL_45"   SITE "N31";
+LOCATE COMP  "ADO_TTL_46"   SITE "P31";
+
+DEFINE PORT GROUP "ADO_TTL_group" "ADO_TTL*" ;
+IOBUF GROUP "ADO_TTL_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8;
+
+LOCATE COMP  "FS_PE_0"    SITE "T26";
+LOCATE COMP  "FS_PE_1"    SITE "U26";
+LOCATE COMP  "FS_PE_2"    SITE "U27";
+LOCATE COMP  "FS_PE_3"    SITE "U31";
+LOCATE COMP  "FS_PE_4"    SITE "V33";
+LOCATE COMP  "FS_PE_5"    SITE "V34";
+LOCATE COMP  "FS_PE_6"    SITE "U32";
+LOCATE COMP  "FS_PE_7"    SITE "U34";
+LOCATE COMP  "FS_PE_8"    SITE "U33";
+LOCATE COMP  "FS_PE_9"    SITE "T34";
+LOCATE COMP  "FS_PE_10"   SITE "T33";
+LOCATE COMP  "FS_PE_11"   SITE "T32";
+LOCATE COMP  "FS_PE_12"   SITE "T31";
+LOCATE COMP  "FS_PE_13"   SITE "T30";
+LOCATE COMP  "FS_PE_14"   SITE "U30";
+LOCATE COMP  "FS_PE_15"   SITE "T29";
+LOCATE COMP  "FS_PE_16"   SITE "T28";
+LOCATE COMP  "FS_PE_17"   SITE "T27";
+
+DEFINE PORT GROUP "FS_PE_group" "FS_PE*" ;
+IOBUF GROUP "FS_PE_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8;
+
+
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+LOCATE COMP  "FLASH_CLK"   SITE "C30";
+LOCATE COMP  "FLASH_CS"    SITE "A31";
+LOCATE COMP  "FLASH_DIN"   SITE "B31";
+LOCATE COMP  "FLASH_DOUT"  SITE "C29";
+
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12;
+
+LOCATE COMP  "PROGRAMN"   SITE "H25";
+IOBUF  PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8  ;
+
+
+#################################################################
+# Test Connector
+#################################################################
+LOCATE COMP  "TEST_LINE_0"    SITE "G4";
+LOCATE COMP  "TEST_LINE_1"    SITE "G5";
+LOCATE COMP  "TEST_LINE_2"    SITE "H5";
+LOCATE COMP  "TEST_LINE_3"    SITE "H4";
+LOCATE COMP  "TEST_LINE_4"    SITE "F2";
+LOCATE COMP  "TEST_LINE_5"    SITE "F1";
+LOCATE COMP  "TEST_LINE_6"    SITE "F3";
+LOCATE COMP  "TEST_LINE_7"    SITE "E3";
+LOCATE COMP  "TEST_LINE_8"    SITE "G2";
+LOCATE COMP  "TEST_LINE_9"    SITE "G1";
+LOCATE COMP  "TEST_LINE_10"   SITE "G3";
+LOCATE COMP  "TEST_LINE_11"   SITE "H3";
+LOCATE COMP  "TEST_LINE_12"   SITE "H1";
+LOCATE COMP  "TEST_LINE_13"   SITE "J1";
+LOCATE COMP  "TEST_LINE_14"   SITE "J3";
+LOCATE COMP  "TEST_LINE_15"   SITE "H2";
+LOCATE COMP  "TEST_LINE_16"   SITE "K4";
+LOCATE COMP  "TEST_LINE_17"   SITE "K3";
+LOCATE COMP  "TEST_LINE_18"   SITE "K7";
+LOCATE COMP  "TEST_LINE_19"   SITE "J6";
+LOCATE COMP  "TEST_LINE_20"   SITE "K2";
+LOCATE COMP  "TEST_LINE_21"   SITE "K1";
+LOCATE COMP  "TEST_LINE_22"   SITE "L10";
+LOCATE COMP  "TEST_LINE_23"   SITE "L9";
+LOCATE COMP  "TEST_LINE_24"   SITE "L2";
+LOCATE COMP  "TEST_LINE_25"   SITE "L1";
+LOCATE COMP  "TEST_LINE_26"   SITE "M8";
+LOCATE COMP  "TEST_LINE_27"   SITE "L7";
+LOCATE COMP  "TEST_LINE_28"   SITE "L5";
+LOCATE COMP  "TEST_LINE_29"   SITE "L4";
+LOCATE COMP  "TEST_LINE_30"   SITE "K6";
+LOCATE COMP  "TEST_LINE_31"   SITE "K5";
+
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8;
+
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP  "TEMPSENS"    SITE "D22";
+IOBUF  PORT "TEMPSENS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8  ;
+
+
+#################################################################
+# Other Pins / Unused
+#################################################################
+# LOCATE COMP  "SDF4_RIGHT_INP_0"   SITE "AP10";
+# LOCATE COMP  "SDF4_RIGHT_INN_0"   SITE "AN10";
+# LOCATE COMP  "SDF3_RIGHT_OUTP_0"    SITE "AL11";
+# LOCATE COMP  "SDF4_RIGHT_OUTP_0"    SITE "AL10";
+# LOCATE COMP  "SDF4_RIGHT_OUTN_0"    SITE "AK10";
+# LOCATE COMP  "SDF2_RIGHT_OUTN_0"    SITE "AK12";
+# LOCATE COMP  "SDF1_RIGHT_INP_0"   SITE "AP13";
+# LOCATE COMP  "SDF2_RIGHT_INP_0"   SITE "AP12";
+# LOCATE COMP  "SDF1_RIGHT_INN_0"   SITE "AN13";
+# LOCATE COMP  "SDF3_RIGHT_INN_0"   SITE "AN11";
+# LOCATE COMP  "SDF2_RIGHT_INN_0"   SITE "AN12";
+# LOCATE COMP  "SDF1_RIGHT_OUTP_0"    SITE "AL13";
+# LOCATE COMP  "SDF3_RIGHT_OUTN_0"    SITE "AK11";
+# LOCATE COMP  "SDF2_RIGHT_OUTP_0"    SITE "AL12";
+# LOCATE COMP  "SDF3_RIGHT_INP_0"   SITE "AP11";
+# LOCATE COMP  "SDF1_RIGHT_OUTN_0"    SITE "AK13";
+# LOCATE COMP  "SDF4_RIGHT_OUTP_1"    SITE "AL22";
+# LOCATE COMP  "SDF3_RIGHT_INN_1"   SITE "AN23";
+# LOCATE COMP  "SDF3_RIGHT_OUTN_1"    SITE "AK23";
+# LOCATE COMP  "SDF2_RIGHT_OUTN_1"    SITE "AK24";
+# LOCATE COMP  "SDF2_RIGHT_INN_1"   SITE "AN24";
+# LOCATE COMP  "SDF3_RIGHT_OUTP_1"    SITE "AL23";
+# LOCATE COMP  "SDF4_RIGHT_INN_1"   SITE "AN22";
+# LOCATE COMP  "SDF1_RIGHT_OUTN_1"    SITE "AK25";
+# LOCATE COMP  "SDF2_RIGHT_OUTP_1"    SITE "AL24";
+# LOCATE COMP  "SDF1_RIGHT_OUTP_1"    SITE "AL25";
+# LOCATE COMP  "SDF1_RIGHT_INP_1"   SITE "AP25";
+# LOCATE COMP  "SDF3_RIGHT_INP_1"   SITE "AP23";
+# LOCATE COMP  "SDF1_RIGHT_INN_1"   SITE "AN25";
+# LOCATE COMP  "SDF2_RIGHT_INP_1"   SITE "AP24";
+# LOCATE COMP  "SDF4_RIGHT_OUTN_1"    SITE "AK22";
+# LOCATE COMP  "SDF4_RIGHT_INP_1"   SITE "AP22";
+# LOCATE COMP  "SFP5_RXN"   SITE "AK17";
+# LOCATE COMP  "SFP5_TXP"   SITE "AP17";
+# LOCATE COMP  "SFP8_RXP"   SITE "AL14";
+# LOCATE COMP  "SFP8_TXP"   SITE "AP14";
+# LOCATE COMP  "SFP1_TXN"   SITE "AN21";
+# LOCATE COMP  "SFP4_RXN"   SITE "AK18";
+# LOCATE COMP  "SFP6_TXP"   SITE "AP16";
+# LOCATE COMP  "SFP1_RXP"   SITE "AL21";
+# LOCATE COMP  "SFP5_RXP"   SITE "AL17";
+# LOCATE COMP  "SFP7_TXN"   SITE "AN15";
+# LOCATE COMP  "SFP6_RXN"   SITE "AK16";
+# LOCATE COMP  "SFP3_RXP"   SITE "AL19";
+# LOCATE COMP  "SFP2_RXP"   SITE "AL20";
+# LOCATE COMP  "SFP7_RXP"   SITE "AL15";
+# LOCATE COMP  "SFP2_TXN"   SITE "AN20";
+# LOCATE COMP  "SFP4_RXP"   SITE "AL18";
+# LOCATE COMP  "SFP3_TXP"   SITE "AP19";
+# LOCATE COMP  "SFP7_TXP"   SITE "AP15";
+# LOCATE COMP  "SFP8_RXN"   SITE "AK14";
+# LOCATE COMP  "SFP2_TXP"   SITE "AP20";
+# LOCATE COMP  "SFP1_RXN"   SITE "AK21";
+# LOCATE COMP  "SFP1_TXP"   SITE "AP21";
+# LOCATE COMP  "SFP3_RXN"   SITE "AK19";
+# LOCATE COMP  "SFP8_TXN"   SITE "AN14";
+# LOCATE COMP  "SFP4_TXP"   SITE "AP18";
+# LOCATE COMP  "SFP7_RXN"   SITE "AK15";
+# LOCATE COMP  "SFP5_TXN"   SITE "AN17";
+# LOCATE COMP  "SFP2_RXN"   SITE "AK20";
+# LOCATE COMP  "SFP4_TXN"   SITE "AN18";
+# LOCATE COMP  "SFP6_TXN"   SITE "AN16";
+# LOCATE COMP  "SFP6_RXP"   SITE "AL16";
+# LOCATE COMP  "SFP3_TXN"   SITE "AN19";
+# LOCATE COMP  "JTAG_F5TDO"   SITE "C1";
+# LOCATE COMP  "JTAG_TCK"   SITE "D1";
+# LOCATE COMP  "JTAG_TDO"   SITE "E1";
+# LOCATE COMP  "JTAG_TMS"   SITE "D2";
+
+
+

diff --git a/base/trb3_central.vhd b/base/trb3_central.vhd
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..5519a0597dc253aa945647fffa523aa55f323d86 100644 (file)
--- a/base/trb3_central.vhd
+++ b/base/trb3_central.vhd
@@ -0,0 +1,218 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.version.all;
+
+
+
+entity trb3_central is
+  port(
+    --Clocks
+    CLK_EXT                        : in  std_logic_vector(4 downto 3); --from RJ45
+    CLK_GPLL_LEFT                  : in  std_logic;  --Clock Manager 2/9, 200 MHz  <-- MAIN CLOCK
+    CLK_GPLL_RIGHT                 : in  std_logic;  --Clock Manager 1/9, 125 MHz  <-- for GbE
+    CLK_PCLK_LEFT                  : in  std_logic;  --Clock Fan-out, 200 MHz      <-- for Serdes if GPLL doesn't work. Same oscillator as GPLL left!
+    CLK_PCLK_RIGHT                 : in  std_logic;  --Clock Fan-out, 200 MHz      <-- use this clock for BASIC tests!
+
+    --Trigger
+    TRIGGER_LEFT                   : in  std_logic;  --left side trigger input from fan-out
+    TRIGGER_RIGHT                  : in  std_logic;  --right side trigger input from fan-out
+    TRIGGER_EXT                    : in  std_logic_vector(4 downto 2); --additional trigger from RJ45
+    TRIGGER_OUT                    : out std_logic;  --trigger to second input of fan-out
+    
+    --Serdes
+    CLK_SERDES_INT_LEFT            : in  std_logic;  --Clock Manager 2/0, 200 MHz, only in case of problems
+    CLK_SERDES_INT_RIGHT           : in  std_logic;  --Clock Manager 1/0, off, 125 MHz possible
+    
+    --SFP
+    SFP_TX_FAULT                   : in  std_logic_vector(7 downto 0); --TX broken
+    SFP_RATE_SEL                   : out std_logic_vector(7 downto 0); --not supported by our SFP
+    SFP_LOS                        : in  std_logic_vector(7 downto 0); --Loss of signal
+    SFP_MOD0                       : in  std_logic_vector(7 downto 0); --SFP present
+    SFP_MOD1                       : in  std_logic_vector(7 downto 0); --I2C interface
+    SFP_MOD2                       : in  std_logic_vector(7 downto 0); --I2C interface
+    SFP_TXDIS                      : out std_logic_vector(7 downto 0); --disable TX
+    
+    --Clock and Trigger Control
+    TRIGGER_SELECT                 : out std_logic;  --trigger select for fan-out. 0: external, 1: signal from FPGA5
+    CLOCK_SELECT                   : out std_logic;  --clock select for fan-out. 0: 200MHz, 1: external from RJ45
+    CLK_MNGR1_USER                 : inout std_logic_vector(3 downto 0); --I/O lines to clock manager 1
+    CLK_MNGR2_USER                 : inout std_logic_vector(3 downto 0); --I/O lines to clock manager 1
+    
+    --Inter-FPGA Communication
+    FPGA1_COMM                     : inout std_logic_vector(11 downto 0);
+    FPGA2_COMM                     : inout std_logic_vector(11 downto 0);
+    FPGA3_COMM                     : inout std_logic_vector(11 downto 0);
+    FPGA4_COMM                     : inout std_logic_vector(11 downto 0); 
+                                    -- on all FPGAn_COMM:  --Bit 0/1 output, serial link TX active
+                                                           --Bit 2/3 input, serial link RX active
+                                                           --others yet undefined
+    FPGA1_TTL                      : inout std_logic_vector(3 downto 0);
+    FPGA2_TTL                      : inout std_logic_vector(3 downto 0);
+    FPGA3_TTL                      : inout std_logic_vector(3 downto 0);
+    FPGA4_TTL                      : inout std_logic_vector(3 downto 0);
+                                    --only for not timing-sensitive signals
+
+    --Communication to small addons
+    FPGA1_CONNECTOR                : inout std_logic_vector(7 downto 0); --Bit 2-3: LED for SFP3/4
+    FPGA2_CONNECTOR                : inout std_logic_vector(7 downto 0); --Bit 2-3: LED for SFP7/8
+    FPGA3_CONNECTOR                : inout std_logic_vector(7 downto 0); --Bit 0-1: LED for SFP5/6 
+    FPGA4_CONNECTOR                : inout std_logic_vector(7 downto 0); --Bit 0-1: LED for SFP1/2
+                                                                         --Bit 0-3 connected to LED by default, two on each side
+                                                                         
+    --Big AddOn connector
+    ADDON_RESET                    : out std_logic; --reset signal to AddOn
+    ADDON_TO_TRB_CLK               : in  std_logic; --Clock from AddOn, connected to PCLK input
+    TRB_TO_ADDON_CLK               : out std_logic; --Clock sent to AddOn
+    ADO_LV                         : inout std_logic_vector(61 downto 0);
+    ADO_TTL                        : inout std_logic_vector(46 downto 0);
+    FS_PE                          : inout std_logic_vector(17 downto 0);
+    
+    --Flash ROM & Reboot
+    FLASH_CLK                      : out std_logic;
+    FLASH_CS                       : out std_logic;
+    FLASH_CIN                      : out std_logic;
+    FLASH_DOUT                     : in  std_logic;
+    PROGRAMN                       : out std_logic; --reboot FPGA
+    
+    --Misc
+    ENPIRION_CLOCK                 : out std_logic;  --Clock for power supply, not necessary, floating
+    TEMPSENS                       : inout std_logic; --Temperature Sensor
+    LED_CLOCK_GREEN                : out std_logic;
+    LED_CLOCK_GREEN                : out std_logic; 
+    LED_CLOCK_RED                  : out std_logic;
+    LED_GREEN                      : out std_logic;
+    LED_ORANGE                     : out std_logic; 
+    LED_RED                        : out std_logic;
+    LED_TRIGGER_GREEN              : out std_logic;
+    LED_TRIGGER_RED                : out std_logic; 
+    LED_YELLOW                     : out std_logic;
+
+    --Test Connectors
+    TEST_LINE                      : out std_logic_vector(31 downto 0)
+    );
+    
+    attribute syn_useioff : boolean;
+    --no IO-FF for LEDs relaxes timing constraints
+    attribute syn_useioff of LED_CLOCK_GREEN    : signal is false;
+    attribute syn_useioff of LED_CLOCK_GREEN    : signal is false;
+    attribute syn_useioff of LED_CLOCK_RED      : signal is false;
+    attribute syn_useioff of LED_GREEN          : signal is false;
+    attribute syn_useioff of LED_ORANGE         : signal is false;
+    attribute syn_useioff of LED_RED            : signal is false;
+    attribute syn_useioff of LED_TRIGGER_GREEN  : signal is false;
+    attribute syn_useioff of LED_TRIGGER_RED    : signal is false;
+    attribute syn_useioff of LED_YELLOW         : signal is false;
+    attribute syn_useioff of FPGA1_TTL          : signal is false;
+    attribute syn_useioff of FPGA2_TTL          : signal is false;
+    attribute syn_useioff of FPGA3_TTL          : signal is false;
+    attribute syn_useioff of FPGA4_TTL          : signal is false;
+    attribute syn_useioff of SFP_TXDIS          : signal is false;
+    
+    --important signals _with_ IO-FF
+    attribute syn_useioff of FLASH_CLK          : signal is true;
+    attribute syn_useioff of FLASH_CS           : signal is true;
+    attribute syn_useioff of FLASH_CIN          : signal is true;
+    attribute syn_useioff of FLASH_DOUT         : signal is true;
+    attribute syn_useioff of FPGA1_COMM         : signal is true;
+    attribute syn_useioff of FPGA2_COMM         : signal is true;
+    attribute syn_useioff of FPGA3_COMM         : signal is true;
+    attribute syn_useioff of FPGA4_COMM         : signal is true;
+
+
+end entity;
+
+architecture trb3_central_arch of trb3_central is
+
+  signal clk_100_i   : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+  signal clk_200_i   : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+  signal pll_lock    : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+
+begin
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+  THE_MAIN_PLL : pll_in200_out100
+    port map(
+      CLK    => CLK_GPLL_LEFT,
+      CLKOP  => clk_100_i,
+      CLKOK  => clk_200_i,
+      LOCK   => pll_lock
+      );
+
+
+---------------------------------------------------------------------------
+-- Clock and Trigger Configuration
+---------------------------------------------------------------------------
+  TRIGGER_SELECT <= '0'; --always external trigger source
+  CLOCK_SELECT   <= '0'; --use on-board oscillator
+  CLK_MNGR1_USER <= (others => 'Z');
+  CLK_MNGR2_USER <= (others => 'Z'); 
+
+  TRIGGER_OUT    <= '0';
+
+
+---------------------------------------------------------------------------
+-- FPGA communication
+---------------------------------------------------------------------------
+  FPGA1_COMM <= (others => 'Z');
+  FPGA2_COMM <= (others => 'Z');
+  FPGA3_COMM <= (others => 'Z');
+  FPGA4_COMM <= (others => 'Z');
+
+  FPGA1_TTL <= (others => 'Z');
+  FPGA2_TTL <= (others => 'Z');
+  FPGA3_TTL <= (others => 'Z');
+  FPGA4_TTL <= (others => 'Z');
+
+  FPGA1_CONNECTOR <= (others => '0');
+  FPGA2_CONNECTOR <= (others => '0');
+  FPGA3_CONNECTOR <= (others => '0');
+  FPGA4_CONNECTOR <= (others => '0');
+
+
+---------------------------------------------------------------------------
+-- Flash ROM
+---------------------------------------------------------------------------
+  FLASH_CLK <= '0';
+  FLASH_CS  <= '0';
+  FLASH_CIN <= '0';
+
+
+---------------------------------------------------------------------------
+-- Big AddOn Connector
+---------------------------------------------------------------------------
+  ADDON_RESET      <= '1';
+  TRB_TO_ADDON_CLK <= '0';
+  ADO_LV           <= (others => 'Z');
+  ADO_TTL          <= (others => 'Z');
+  FS_PE            <= (others => 'Z');
+
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+  LED_CLOCK_GREEN                <= '0';
+  LED_CLOCK_GREEN                <= '1';
+  LED_CLOCK_RED                  <= '1';
+  LED_GREEN                      <= '1';
+  LED_ORANGE                     <= '1'; 
+  LED_RED                        <= '1';
+  LED_TRIGGER_GREEN              <= '0';
+  LED_TRIGGER_RED                <= '1';
+  LED_YELLOW                     <= '1';
+
+
+---------------------------------------------------------------------------
+-- Test Connector
+---------------------------------------------------------------------------    
+  TEST_LINE                     <= (others => '0');
+
+
+end architecture;
\ No newline at end of file

diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd
new file mode 100644 (file)
index 0000000..8c1d102
--- /dev/null
+++ b/base/trb3_components.vhd
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.trb_net_std.all;
+
+package trb3_components is
+
+
+
+component pll_in200_out100
+  port (
+    CLK: in std_logic; 
+    CLKOP: out std_logic; --100 MHz
+    CLKOK: out std_logic; --200 MHz
+    LOCK: out std_logic
+    );
+  end component;
+  
+  
+end package;
\ No newline at end of file

diff --git a/central_hub2/.cvsignore b/central_hub2/.cvsignore
new file mode 100644 (file)
index 0000000..8f9fbc7
--- /dev/null
+++ b/central_hub2/.cvsignore
@@ -0,0 +1,5 @@
+shower_fpga*
+*.log
+*.rpt
+version.vhd
+*.log

diff --git a/fpgatest/.cvsignore b/fpgatest/.cvsignore
new file mode 100644 (file)
index 0000000..8f9fbc7
--- /dev/null
+++ b/fpgatest/.cvsignore
@@ -0,0 +1,5 @@
+shower_fpga*
+*.log
+*.rpt
+version.vhd
+*.log