RICH joined the party

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@@ -4,7 +4,134 @@ The schematics of the RICH ADCM 3 can be found in \cite{ADCM}.
 \subsection{IPU Data Format}
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
+The RICH data format used in the TRBnet readout differs significantly from the 
+previous VME based readout. Like the old format (sector, readout controller,
+port, module, channel) it is based on the physical readout structure of the 
+new system.
+
+One sector is read out by five ADCMs, each one connected to 15 APV frontend 
+cards (APV-FE). The sector and module number is set by DIP switches located
+on the backplanes.
+
+One data word is represented by a 32bit word, containing all necessary 
+information to identify a single channel within the RICH setup. A single 
+channel is identified by SECTOR (3bits), MODULE (3bits), APV (4bits) and
+CHANNEL (7bits). The ADC value itself is 14bit wide, while the intrinsic 
+resolution of the ADC is 12bit. This is necessary due to the data 
+preprocessing inside the FPGA (see table \ref{richnormaldataformat}).
+
+\begin{table}
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|X|}
+\hline
+\textbf{Bits} & \textbf{description} \\
+\hline
+\hline
+31       & 0: normal data, 1: debug / status information \\
+30 -- 28 & sector number, starting with zero \\
+27 -- 25 & ADCM module number \\
+24 -- 21 & APV number \\
+20 -- 14 & APV channel \\
+13 -- 0  & ADC value with offsets \textbf{(to be changed!)} \\
+\hline
+\end{tabularx}
+\caption{RICH normal data format}
+\label{richnormaldataformat}
+\end{center}
+\end{table}
+
+In general, all channels with even numbers (0,2,4,$\ldots$) represent physical 
+channels on the detector, all channels with odd numbers (1,3,5,$\ldots$) are
+auxiliary channels used for local baseline restauration.
+
+All normal RICH data words start with the most significant bit (MSB) set to 
+zero, while status and debug information has always set MSB to one. Unpackers
+should ignore RICH data words with the MSB set.
+
+RICH data can be preprocessed in several ways, depending on the LVL1 trigger
+information sent on TRBnet (see table~\ref{richpreprocessingoptions}). 
+
+\begin{table}
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|l|c|X|}
+\hline
+\textbf{Bits} & \textbf{OPCODE} & \textbf{channels} &
+  \textbf{result} \\
+\hline
+\hline
+000 & RAW128    & $128$      & raw \\
+001 & PED128    & $128$      & pedestal corrected \\
+010 & PED128THR & $\leq 128$ & pedestal corrected, threshold selected \\
+011 & reserved  & ---        & DO NOT USE \\
+100 & NC64PED64 & $128$      & baseline corrected + auxiliary channels \\
+101 & NC64      & $64$       & baseline corrected \\
+110 & NC64GOOD  & $\leq 64$  & overflow / underflows removed \\
+111 & NC64THR   & $\leq 64$  & normal mode \\
+\hline
+\end{tabularx}
+\caption{RICH preprocessing options}
+\label{richpreprocessingoptions}
+\end{center}
+\end{table}
+
+At the moment, there are two different debug and status words defined in RICH.
+This may change in the future.
+
+\begin{table}
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|C|C|}
+\hline
+\textbf{Bits} & \textbf{STAT0} & \textbf{STAT1} \\
+\hline
+\hline
+31       & 1              & 1               \\
+30 -- 28 & SECTOR         & SECTOR          \\
+27 -- 25 & MODULE         & MODULE          \\
+24 -- 21 & APV            & APV             \\
+20       & BUF\_BAD       & ERROR           \\
+19 -- 16 & error bits     & EDS\_FRAME\_CTR \\
+19       & BUF\_INVALID   & ---             \\
+18       & FRAME\_COUNTER & ---             \\
+17       & ROW\_MISMATCH  & ---             \\
+16       & APV\_ERROR     & ---             \\
+15 -- 12 & MAX\_FRAMES    & LOC\_FRAME\_CTR \\
+11 -- 8  & CURR\_FRAME    & FRAME\_CTR      \\
+7 -- 0   & APV\_ROW       & APV\_ROW        \\
+\hline
+\end{tabularx}
+\caption{RICH status format}
+\label{richdebugformat}
+\end{center}
+\end{table}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \subsection{Memory Map}
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\ No newline at end of file
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
+\begin{table}[hbtp]
+\begin{center}
+\begin{tabularx}{\textwidth}{l|l|X}
+\textbf{Address} & \textbf{Name} & \textbf{Description} \\
+0xA000 -- 0xA7FF & PEDESTALS     & pedestal memories \\
+0xA800 -- 0xAFFF & THRESHOLDS    & threshold memories \\
+0x8040           & I2C\_MASTER   & I2C master for APV slow control \\ 
+0xC000 -- 0xC03F & 1WIRE\_MASTER & 1Wire Master + memory \\
+0xD000           & SPI\_MASTER   & FlashROM controller \\
+0xD100 -- 0xD13F & SPI\_MEMORY   & SPI auxiliary memory \\
+0xD010           & ADC0\_SPI     & SPI master for ADC0 slow control \\
+0xD020           & ADC1\_SPI     & SPI master for ADC1 slow control \\
+0xB000 -- 0xB00F & APV\_CTRL     & APV control and status register \\
+0xB010           & ADC\_LEVEL    & ADC level settings \\    
+0xB020           & TRG\_CTRL     & trigger settings \\
+0xB030           & PLL\_CTRL     & PLL settings \\
+0xF000 -- 0xF3FF & ADC0\_SNOOP   & ADC0 digital scope \\
+0xF800 -- 0xFFFF & ADC1\_SNOOP   & ADC1 digital scope \\
+0x8000           & SCRATCH\_PAD  & test register \\
+\end{tabularx}
+\caption{Memory map for FPGA on ADCMv3}
+\label{RichAdcmMemoryMap}
+\end{center}
+\end{table}
+
+\subsubsection{Pedestals}
+