CTS in TDC included

diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
index f769ac6e7abbe81ee7fabfed60b863193553d08a..f372974b07f412dc2b0aa5656fb0edf342be1101 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
@@ -49,8 +49,6 @@ entity med_ecp3_sfp_sync_all_RS is
     LINK_TX_READY_IN   : in  std_logic; -- from TX reset generator
     DESTROY_LINK_IN    : in  std_logic_vector(3 downto 0); -- hard reset for links
     WAP_REQUESTED_IN   : in  std_logic_vector(3 downto 0); -- TESTTESTTEST
-    RX_INDEX_OUT       : out std_logic_vector(3 downto 0); -- TESTTESTTEST
-    DLM_RESULT_OUT     : out std_logic_vector(4*32-1 downto 0); -- TESTTESTTEST
     --SFP Connection
     SD_PRSNT_N_IN      : in  std_logic_vector(3 downto 0);  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
     SD_LOS_IN          : in  std_logic_vector(3 downto 0);  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
@@ -144,10 +142,7 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is
   signal word_sync_sel      : std_logic;
 
   signal link_active_i      : std_logic_vector(3 downto 0);
-  
-  signal rx_index_i         : std_logic_vector(3 downto 0);
-  signal dlm_result_i       : std_logic_vector(4*32-1 downto 0);
-  
+
   signal quad_mode : integer range 0 to 100;
 
 begin
@@ -284,10 +279,6 @@ begin
   wap_requested_i(2*4+3 downto 2*4) <= WAP_REQUESTED_IN when (IS_MODE(2) = c_IS_MASTER) else x"0";
   wap_requested_i(3*4+3 downto 3*4) <= WAP_REQUESTED_IN when (IS_MODE(3) = c_IS_MASTER) else x"0";
 
--------------------------------------------------      
--------------------------------------------------      
-  RX_INDEX_OUT <= rx_index_i;
-
 -------------------------------------------------      
 -- Serdes
 -------------------------------------------------      
@@ -484,7 +475,6 @@ gen_control : for i in 0 to 3 generate
         LINK_TX_READY_IN   => LINK_TX_READY_IN,
         LINK_RX_READY_OUT  => link_rx_ready_i(i),
         LINK_ACTIVE_OUT    => link_active_i(i),
-        RX_INDEX_OUT       => rx_index_i(i),
         -- komma operation
         TX_DLM_IN          => TX_DLM_IN,
         TX_DLM_WORD_IN     => TX_DLM_WORD_IN,
@@ -511,48 +501,17 @@ gen_control : for i in 0 to 3 generate
     powerup_ch(i)              <= '0'; -- keep in power down
     rx_serdes_rst(i)           <= '1'; -- keep in reset
     rx_pcs_rst(i)              <= '1'; -- keep in reset
-    rx_index_i(i)              <= '0';
     wap_req_i(i)               <= '0';
     MEDIA_MED2INT(i).dataready <= '0';
     MEDIA_MED2INT(i).tx_read   <= '1';
     MEDIA_MED2INT(i).stat_op   <= x"0007";
   end generate;
-
-  gen_phaser : if (IS_MODE(i) = c_IS_MASTER) generate
-    THE_PHASER : entity work.phaser
-      port map( 
-        SAMPLE_CLK    => SAMPLE_CLK,
-        RESET         => RESET,
-        START_IN      => TX_DLM_IN, -- TX DLM
-        STOP_IN       => rx_dlm_i(i), -- RX DLM
-        PING_IN       => word_sync_sel, -- TX K
-        CLK_PING      => MASTER_CLK_IN, -- TX CLK
-        PONG_IN       => rx_index_i(i), -- RX K
-        CLK_PONG      => clk_rx_full(i), -- RX CLK
-        RESULT_OUT    => dlm_result_i(i*32+31 downto i*32),
-        UPDATE_OUT    => open
-     );
-     
-     --- BUG BUG BUG word_sync_sel works not always
-  end generate;
   
 end generate;
 
-  RX_DLM_OUT     <= rx_dlm_i;
-  DLM_RESULT_OUT <= dlm_result_i;
-
   wap_req_all <= wap_req_i(0) or wap_req_i(1) or wap_req_i(2) or wap_req_i(3);
 
---  SYNC_REQ_0: entity work.signal_sync 
---  generic map( WIDTH => 1 )
---  port map(
---    RESET    => RESET,
---    CLK0     => CLK_REF_FULL, 
---    CLK1     => SYSCLK,
---    D_IN(0)  => wap_req_all,
---    D_OUT(0) => wap_req_all_q
---  );
-  
+  -- SIGNAL_SYNC fails. TAKE CARE!
   wap_req_all_q(2 downto 0) <= wap_req_all_q(1 downto 0) & wap_req_all when rising_edge(SYSCLK);
   
   THE_SCI_READER : entity work.sci_reader_RS

diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd
index 9ea5a1fa29d94dfbb91a32b58f69b6c5c25aca58..35965171c68ced8cf05bba259b9e9ea3831c7ef9 100644 (file)
--- a/media_interfaces/sync/med_sync_control_RS.vhd
+++ b/media_interfaces/sync/med_sync_control_RS.vhd
@@ -48,7 +48,6 @@ entity med_sync_control_RS is
     LINK_TX_READY_IN   : in  std_logic; --
     LINK_RX_READY_OUT  : out std_logic; --
     LINK_ACTIVE_OUT    : out std_logic; --
-    RX_INDEX_OUT       : out std_logic; -- 
     -- komma handling
     TX_DLM_IN          : in  std_logic; -- transmit one DLM komma
     TX_DLM_WORD_IN     : in  std_logic_vector(7 downto 0);
@@ -197,8 +196,6 @@ begin
     );   
 
   DEBUG_RX_CONTROL <= debug_rx_control_i;
-
-  RX_INDEX_OUT <= word_sync_rx_i;
   
 -- clocks for media interface
   media_med2int_i.clk_half <= CLK_RXHALF; -- goes to clock and reset handler 

diff --git a/media_interfaces/sync/sci_reader_RS.vhd b/media_interfaces/sync/sci_reader_RS.vhd
index 0898aaf2653c46268011e32fc9c7edd63f4f056d..d67f99d200e5586c080a0d33fa573e4828ef003a 100644 (file)
--- a/media_interfaces/sync/sci_reader_RS.vhd
+++ b/media_interfaces/sync/sci_reader_RS.vhd
@@ -45,6 +45,10 @@ signal sci_reg_i         : std_logic;
 signal wa_position       : std_logic_vector(15 downto 0);
 signal next_sci_wr       : std_logic;
 
+--signal txdata_q          : std_logic_vector(7 downto 0);
+--signal txack_q           : std_logic;
+--signal txnack_q          : std_logic;
+
 begin
 
 ------------------------------------------------      
@@ -60,7 +64,9 @@ begin
   begin
     wait until rising_edge(CLK);
     BUS_TX.ack <= '0';
+--    txack_q  <= '0';
     BUS_TX.nack <= '0';
+--    txnack_q <= '0';
    
     SCI_WR <= next_sci_wr;
    
@@ -83,7 +89,6 @@ begin
           SCI_RD        <= BUS_RX.read  and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and     BUS_RX.addr(8));
           next_sci_wr   <= BUS_RX.write and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and     BUS_RX.addr(8));
           sci_state     <= SCTRL;
---        elsif( (sci_timer(sci_timer'left) = '1') and (wap_req_q(2) = '1') ) then
         elsif( (sci_timer(sci_timer'left) = '1') and (WA_REQ_IN = '1') ) then
           sci_timer     <= (others => '0');
           sci_state     <= GET_WA;
@@ -91,7 +96,9 @@ begin
       when SCTRL =>
         if( sci_reg_i = '1' ) then
           BUS_TX.data   <= MEDIA_STATUS_REG_IN(32*(to_integer(unsigned(BUS_RX.addr(3 downto 0))))+31 downto 32*(to_integer(unsigned(BUS_RX.addr(3 downto 0)))));
+--          txdata_q      <= MEDIA_STATUS_REG_IN(32*(to_integer(unsigned(BUS_RX.addr(3 downto 0))))+31 downto 32*(to_integer(unsigned(BUS_RX.addr(3 downto 0)))));
           BUS_TX.ack    <= '1';
+--          txack_q       <= '1';
           next_sci_wr   <= '0';
           SCI_RD        <= '0';
           sci_state     <= IDLE;
@@ -104,9 +111,11 @@ begin
         sci_state       <= SCTRL_FINISH;
       when SCTRL_FINISH =>
         BUS_TX.data(7 downto 0) <= SCI_RDDATA;
+--        txdata_q        <= SCI_RDDATA;
         BUS_TX.ack      <= '1';
+--        txack_q         <= '1';
         next_sci_wr     <= '0';
-         SCI_RD          <= '0';
+        SCI_RD          <= '0';
         sci_state       <= IDLE;
       when GET_WA =>
         if( ((cnt = 4) and (FPGA_TYPE = 3)) or ((cnt = 2) and (FPGA_TYPE = 5)) ) then
@@ -115,9 +124,9 @@ begin
         else
           sci_state     <= GET_WA_WAIT;
           if( FPGA_TYPE = 3 ) then
-            SCI_ADDR      <= "100010";--'0' & x"22"; --for ECP3
+            SCI_ADDR      <= "100010"; -- x"22" for ECP3
           elsif( FPGA_TYPE = 5 ) then
-            SCI_ADDR      <= "110010";--'0' & x"32"; --for ECP5
+            SCI_ADDR      <= "110010"; -- x"32" for ECP5
           end if;  
           SCI_SEL       <= (others => '0');
           SCI_SEL(cnt)  <= '1';
@@ -135,8 +144,15 @@ begin
   
     if( ((BUS_RX.read = '1') or (BUS_RX.write = '1')) and (sci_state /= IDLE) ) then
       BUS_TX.nack <= '1'; 
+--      txnack_q <= '1'; 
       BUS_TX.ack <= '0';
+--      txack_q  <= '0';
     end if;
+
+--    -- should fix timing errors while keeping constraints
+--    BUS_TX.data(7 downto 0) <= txdata_q;
+--    BUS_TX.ack              <= txack_q;
+--    BUS_TX.nack             <= txnack_q;
   end process PROC_SCI_CTRL;
 
   WA_POS_OUT <= wa_position;