*** empty log message ***

diff --git a/trb_net_sbuf5.vhd b/trb_net_sbuf5.vhd
index 805f3b3366e9128d31e58962e75c4792a8b9be09..b5eb11f8e209336a9acba0ab7684b7b069f60506 100644 (file)
--- a/trb_net_sbuf5.vhd
+++ b/trb_net_sbuf5.vhd
@@ -23,8 +23,9 @@ port(
        SYN_DATA_OUT       : out std_logic_vector(18 downto 0); -- Data word\r
        SYN_READ_IN        : in  std_logic;\r
        -- Status and control port\r
-       DEBUG              : out std_logic_vector(15 downto 0);\r
-       DEBUG_DATA         : out std_logic_vector(18 downto 0);\r
+       DEBUG              : out std_logic_vector(7 downto 0);\r
+       DEBUG_BSM          : out std_logic_vector(3 downto 0);\r
+       DEBUG_WCNT         : out std_logic_vector(4 downto 0);\r
        STAT_BUFFER        : out std_logic\r
 );\r
 end entity;\r
@@ -51,6 +52,7 @@ end component fifo_19x16_obuf;
 type STATES is (IDLE, RD1, RD2, RD3, RD4, RD5, WT5, WR5, WD5, DEL);\r
 signal CURRENT_STATE, NEXT_STATE: STATES;\r
 signal bsm_x                 : std_logic_vector(3 downto 0);\r
+signal bsm                   : std_logic_vector(3 downto 0);\r
 \r
 signal syn_dataready_x       : std_logic;\r
 signal syn_dataready         : std_logic;\r
@@ -71,7 +73,7 @@ signal fifo_wcnt             : std_logic_vector(4 downto 0);
 signal fifo_full             : std_logic;\r
 signal fifo_almostfull       : std_logic;\r
 \r
-signal debug_x               : std_logic_vector(15 downto 0);\r
+signal debug_x               : std_logic_vector(7 downto 0);\r
 \r
 attribute syn_preserve : boolean;\r
 attribute syn_keep     : boolean;\r
@@ -79,8 +81,6 @@ attribute syn_preserve of syn_data        : signal is true;
 attribute syn_keep of syn_data            : signal is true;\r
 attribute syn_preserve of syn_dataready   : signal is true;\r
 attribute syn_keep of syn_dataready       : signal is true;\r
-attribute syn_preserve of syn_dataready_x : signal is true;\r
-attribute syn_keep of syn_dataready_x     : signal is true;\r
 \r
 attribute syn_preserve of fifo_wcnt       : signal is true; \r
 attribute syn_keep of fifo_wcnt           : signal is true; \r
@@ -101,7 +101,8 @@ fifo_reset         <= RESET;
 COMB_next_READ_OUT <= not fifo_almostfull;\r
 \r
 DEBUG              <= debug_x;\r
-DEBUG_DATA         <= fifo_data_o;\r
+DEBUG_BSM          <= bsm;\r
+DEBUG_WCNT         <= fifo_wcnt;\r
 STAT_BUFFER        <= fifo_full;\r
 \r
 SYN_DATA_OUT       <= syn_data;\r
@@ -153,7 +154,7 @@ begin
 end process STATE_MEM;\r
 \r
 -- state transitions\r
-STATE_TRANSFORM: process( CURRENT_STATE, p_wait_x, p_avail_x, SYN_READ_IN, syn_dataready )\r
+STATE_TRANSFORM: process( CURRENT_STATE, p_wait_x, p_avail_x, SYN_READ_IN, syn_dataready, COMB_DATAREADY_IN )\r
 begin\r
        NEXT_STATE      <= IDLE; -- avoid latches\r
        fifo_rd_en_x    <= '0';\r
@@ -182,33 +183,30 @@ begin
                                                        syn_dataready_x <= '1';\r
                                                else\r
                                                        NEXT_STATE      <= RD2;\r
-                                                       syn_dataready_x <= p_avail_x;\r
+                                                       syn_dataready_x <= p_avail_x; --?!?\r
                                                end if;\r
-               when DEL        =>  if( SYN_READ_IN = '1' ) then\r
+               when DEL        =>  syn_dataready_x <= '1';\r
+                                               if( SYN_READ_IN = '1' ) then\r
                                                        NEXT_STATE      <= RD3;\r
                                                        fifo_rd_en_x    <= '1';\r
-                                                       syn_dataready_x <= '1';\r
                                                else\r
                                                        NEXT_STATE <= DEL;\r
-                                                       syn_dataready_x <= '1';\r
                                                end if;\r
-               when RD3    =>  if( SYN_READ_IN = '1' ) then\r
+               when RD3    =>  syn_dataready_x <= '1';\r
+                                               if( SYN_READ_IN = '1' ) then\r
                                                        NEXT_STATE      <= RD4;\r
-                                                       syn_dataready_x <= '1';\r
                                                        fifo_rd_en_x    <= '1';\r
                                                else\r
                                                        NEXT_STATE      <= RD3;\r
-                                                       syn_dataready_x <= '1';\r
                                                end if;\r
-               when RD4    =>  if( SYN_READ_IN = '1' ) then\r
+               when RD4    =>  syn_dataready_x <= '1';\r
+                                               if( SYN_READ_IN = '1' ) then\r
                                                        NEXT_STATE      <= RD5;\r
-                                                       syn_dataready_x <= '1';\r
                                                        fifo_rd_en_x    <= '1';\r
                                                else\r
                                                        NEXT_STATE      <= RD4;\r
-                                                       syn_dataready_x <= '1';\r
                                                end if;\r
-               when RD5    =>  syn_dataready_x <= '1';\r
+               when RD5    =>  syn_dataready_x <= '1'; \r
                                                if   ( (SYN_READ_IN = '1') and (p_avail_x = '1') ) then\r
                                                        NEXT_STATE      <= WR5;\r
                                                        fifo_rd_en_x    <= '1';\r
@@ -217,19 +215,20 @@ begin
                                                else\r
                                                        NEXT_STATE      <= RD5;\r
                                                end if;\r
-               when WT5    =>  if( SYN_READ_IN = '1' ) then\r
-                                                       NEXT_STATE <= IDLE;\r
-                                               else\r
-                                                       NEXT_STATE <= WT5;\r
-                                                       syn_dataready_x <= '1';\r
-                                               end if;\r
                when WR5    =>  if( (SYN_READ_IN = '1') and (p_avail_x = '1') ) then\r
                                                        NEXT_STATE      <= RD2;\r
                                                        fifo_rd_en_x    <= '1';\r
-                                                       syn_dataready_x <= '1';\r
+                                                       --syn_dataready_x <= '1';\r
+                                                       syn_dataready_x <= COMB_DATAREADY_IN;\r
                                                else\r
                                                        NEXT_STATE      <= WR5;\r
                                                end if;\r
+               when WT5    =>  if( SYN_READ_IN = '1' ) then\r
+                                                       NEXT_STATE <= IDLE;\r
+                                               else\r
+                                                       NEXT_STATE <= WT5;\r
+                                                       syn_dataready_x <= '1';\r
+                                               end if;\r
                when others =>  NEXT_STATE <= IDLE;\r
        end case;\r
 end process STATE_TRANSFORM;\r
@@ -254,7 +253,6 @@ end process THE_DECODE_PROC;
 THE_SYNC_PROC: process( CLK )\r
 begin\r
        if( rising_edge(CLK) ) then\r
---             if( ((syn_dataready_x = '1') and (syn_read_in = '1')) or (update = '1') ) then\r
                if( ((syn_dataready = '1') and (syn_read_in = '1')) or (update = '1') ) then\r
                        syn_data <= fifo_data_o;\r
                end if;\r
@@ -264,12 +262,10 @@ end process THE_SYNC_PROC;
 ---------------------------------------------------------------------\r
 -- DEBUG\r
 ---------------------------------------------------------------------\r
-debug_x(15 downto 12) <= bsm_x;\r
-debug_x(11)           <= '0';\r
-debug_x(10)           <= fifo_rd_en_x;\r
-debug_x(9)            <= p_avail_x;\r
-debug_x(8)            <= p_wait_x;\r
-debug_x(7 downto 5)   <= (others => '0');\r
-debug_x(4 downto 0)   <= fifo_wcnt;\r
+debug_x(7 downto 4)  <= x"0";\r
+debug_x(3)           <= '0';\r
+debug_x(2)           <= fifo_rd_en_x;\r
+debug_x(1)           <= p_avail_x;\r
+debug_x(0)           <= p_wait_x;\r
 \r
 end architecture;
\ No newline at end of file