<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="sgmii_gbe_pcs34" module="SGMII/Gb Ethernet PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 06 17 11:36:56.461" version="3.4" type="IP" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="sgmii_gbe_pcs34" module="SGMII/Gb Ethernet PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 10 04 13:50:40.319" version="3.4" type="IP" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="sgmii_gbe_pcs34.lpc" type="lpc" modified="2011 06 17 11:36:40.000"/>
- <File name="sgmii_gbe_pcs34.ngo" type="database" modified="2011 06 17 11:36:53.000"/>
- <File name="sgmii_gbe_pcs34_bb.v" type="black_box_verilog" modified="2011 06 17 11:36:53.000"/>
- <File name="sgmii_gbe_pcs34_beh.v" type="behavioral_verilog" modified="2011 06 17 11:36:53.000"/>
- <File name="sgmii_gbe_pcs34_inst.v" type="instantiation_verilog" modified="2011 06 17 11:36:53.000"/>
+ <File name="sgmii_gbe_pcs34.lpc" type="lpc" modified="2011 10 04 13:50:08.000"/>
+ <File name="sgmii_gbe_pcs34.ngo" type="database" modified="2011 10 04 13:50:20.000"/>
+ <File name="sgmii_gbe_pcs34_bb.v" type="black_box_verilog" modified="2011 10 04 13:50:20.000"/>
+ <File name="sgmii_gbe_pcs34_beh.v" type="behavioral_verilog" modified="2011 10 04 13:50:20.000"/>
+ <File name="sgmii_gbe_pcs34_inst.v" type="instantiation_verilog" modified="2011 10 04 13:50:20.000"/>
</Package>
</DiamondModule>
[Device]
-Family=ep5m00
-PartType=LFE2M100E
-PartName=LFE2M100E-5F900C
-SpeedGrade=5
-Package=FPBGA900
+Family=ep5c00
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN1156C
+SpeedGrade=8
+Package=FPBGA1156
OperatingCondition=COM
Status=P
ModuleName=sgmii_gbe_pcs34
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=06/17/2011
-Time=11:36:40
+Date=10/04/2011
+Time=13:50:08
[Parameters]
RX_CTC=2
//=============================================================================
-// Verilog module generated by IPExpress 06/17/2011 11:36:53
+// Verilog module generated by IPExpress 10/04/2011 13:50:20
// Filename: sgmii_gbe_pcs34_bb.v
// Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved.
//=============================================================================
`define SGMII_YES_CTC_DYNAMIC\r
-`define SGMII_FIFO_FAMILY_ECP2M\r
+`define SGMII_FIFO_FAMILY_ECP3\r
`define SGMII_YES_SINGLE_CLOCK\r
=============================================================================
-Filelist generated by IPexpress 06/17/2011 11:36:53
+Filelist generated by IPexpress 10/04/2011 13:50:21
Filename: sgmii_gbe_pcs34_filelist.log
Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved.
=============================================================================
-----------------------------------------------------------------------------
Basic IP Core Files
-Output Directory: /home/greg/projects/trbnet/gbe2_ecp2m/ipcores/sgmii_gbe_pcs34
+Output Directory: /home/greg/projects/trb3/trb3_gbe/ipcores
-----------------------------------------------------------------------------
sgmii_gbe_pcs34.lpc
: IP ispLEVER LPC File
---------------------------------:
Hardware Specific Models
- ../sgmii_pcs_eval/models/ecp2m/pcs_serdes
+ ../sgmii_pcs_eval/models/ecp3/pcs_serdes
Testbench
../sgmii_pcs_eval/testbench
------------------------------------------------
Source Files
- ../sgmii_pcs_eval/sgmii_gbe_pcs34/src/rtl/ecp2m
+ ../sgmii_pcs_eval/sgmii_gbe_pcs34/src/rtl/ecp3
Simulation
../sgmii_pcs_eval/sgmii_gbe_pcs34/sim/modelsim
Starting process: IPCFG
GenerateCore within package Core_Generate 1.0.0 in file LatticeIP_generate.tcl
-Starting process: '"/opt/lattice/diamond/1.1/bin/lin/synpwrap" -rem -e sgmii_gbe_pcs34 -target lattice-ecp2m'
+Starting process: '"/opt/lattice/diamond/1.3/bin/lin/synpwrap" -rem -e sgmii_gbe_pcs34 -target lattice-ecp3'
Warning: You are running on an unsupported platform
End process: completed successfully.
-Starting process: '"/opt/lattice/diamond/1.1/bin/lin/../../ispfpga/bin/lin/edif2ngd" -ip "/home/greg/sgmii_gbepcs_v3.4/lib/../.." -ic sgmii_gbepcs_v3.4 -l LatticeECP2M-DSP -nopropwarn "syn_results/sgmii_gbe_pcs34.edi" "sgmii_gbe_pcs34.ngo"'
-edif2ngd: version Diamond_1.1_Production (517)
+Starting process: '"/opt/lattice/diamond/1.3/bin/lin/../../ispfpga/bin/lin/edif2ngd" -ip "/home/greg/sgmii_gbepcs_v3.4/lib/../.." -ic sgmii_gbepcs_v3.4 -l LatticeECP3 -nopropwarn "syn_results/sgmii_gbe_pcs34.edi" "sgmii_gbe_pcs34.ngo"'
+edif2ngd: version Diamond_1.3_Production (92)
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
- Copyright (c) 2002-2010 Lattice Semiconductor Corporation, All rights reserved.
+ Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
No device specified. Will use default.
Writing the design to sgmii_gbe_pcs34.ngo...
End process: completed successfully.
=============================================================================
-Filelist generated by IPexpress 06/17/2011 11:36:53
+Filelist generated by IPexpress 10/04/2011 13:50:21
Filename: sgmii_gbe_pcs34_filelist.log
Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved.
=============================================================================
-----------------------------------------------------------------------------
Basic IP Core Files
-Output Directory: /home/greg/projects/trbnet/gbe2_ecp2m/ipcores/sgmii_gbe_pcs34
+Output Directory: /home/greg/projects/trb3/trb3_gbe/ipcores
-----------------------------------------------------------------------------
sgmii_gbe_pcs34.lpc
: IP ispLEVER LPC File
---------------------------------:
Hardware Specific Models
- ../sgmii_pcs_eval/models/ecp2m/pcs_serdes
+ ../sgmii_pcs_eval/models/ecp3/pcs_serdes
Testbench
../sgmii_pcs_eval/testbench
------------------------------------------------
Source Files
- ../sgmii_pcs_eval/sgmii_gbe_pcs34/src/rtl/ecp2m
+ ../sgmii_pcs_eval/sgmii_gbe_pcs34/src/rtl/ecp3
Simulation
../sgmii_pcs_eval/sgmii_gbe_pcs34/sim/modelsim
//=============================================================================
-// Verilog module generated by IPExpress 06/17/2011 11:36:53
+// Verilog module generated by IPExpress 10/04/2011 13:50:20
// Filename: sgmii_gbe_pcs34_inst.v
// Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved.
//=============================================================================