BETA. Changed TX_DIS to K_NULL

diff --git a/backplanemaster/trb3sc_master.vhd b/backplanemaster/trb3sc_master.vhd
index 5af3c8ef4ef17b5cfccd735744d43d684b327c4d..3e08028c46b69991b61e4f4192d26e9f46f6ab4f 100644 (file)
--- a/backplanemaster/trb3sc_master.vhd
+++ b/backplanemaster/trb3sc_master.vhd
@@ -186,14 +186,10 @@ architecture trb3sc_arch of trb3sc_master is
   signal global_reset_i              : std_logic;
   signal tx_pll_lol_qd_a_i           : std_logic;
   signal tx_pll_lol_qd_b_i           : std_logic;
-  signal tx_pll_lol_qd_c_i           : std_logic;
-  signal tx_pll_lol_qd_d_i           : std_logic;
-  signal tx_pll_lol_all_i            : std_logic;
   signal tx_clk_avail_i              : std_logic;
   signal tx_pcs_rst_i                : std_logic;
   signal sync_tx_quad_i              : std_logic;
   signal link_tx_ready_i             : std_logic;
-  signal slave_active_i              : std_logic;
   signal rx_dlm_i                    : std_logic;
   signal tx_reset_state              : std_logic_vector(3 downto 0);
   signal debug_i                     : std_logic_vector(31 downto 0);
@@ -213,7 +209,7 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
     EXT_CLK_IN        => CLK_EXT_PLL_LEFT,
     NET_CLK_FULL_IN   => med2int(4).clk_full,
     NET_CLK_HALF_IN   => med2int(4).clk_half,
-    GLOBAL_RESET_IN   => global_reset_i,
+    GLOBAL_RESET_IN   => '0', --global_reset_i,
     RESET_FROM_NET_IN => '0',
     BUS_RX            => bustc_rx,
     BUS_TX            => bustc_tx,
@@ -228,9 +224,7 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
     LED_GREEN_OUT     => LED_RJ_GREEN,
     DEBUG_OUT         => debug_clock_reset
   );
-  
-  tx_pll_lol_qd_c_i <= '0';
-  
+
 ---------------------------------------------------------------------------
 -- PCBSB: TrbNet Uplink
 ---------------------------------------------------------------------------
@@ -271,11 +265,10 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_RS
     WORD_SYNC_OUT      => word_sync_i,
     MASTER_CLK_IN      => master_clk_i,
     MASTER_CLK_OUT     => master_clk_i,
-    QUAD_RST_IN        => global_reset_i,
-    GLOBAL_RESET_OUT   => global_reset_i,
-    SLAVE_ACTIVE_OUT   => slave_active_i,
-    SLAVE_ACTIVE_IN    => slave_active_i,
-    TX_PLL_LOL_IN      => tx_pll_lol_all_i,
+    QUAD_RST_IN        => '0', --global_reset_i,
+    LINK_TX_NULL_IN    => global_reset_i,
+    LINK_RX_NULL_OUT   => global_reset_i,
+    SLAVE_ACTIVE_OUT   => open,
     TX_PLL_LOL_OUT     => tx_pll_lol_qd_b_i,
     TX_CLK_AVAIL_OUT   => tx_clk_avail_i,
     TX_PCS_RST_IN      => tx_pcs_rst_i,
@@ -308,8 +301,6 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_RS
 ---------------------------------------------------------------------------
 -- PCSC: not used
 ---------------------------------------------------------------------------    
-  tx_pll_lol_qd_c_i <= '0';
-
   bussci3_tx.data    <= (others => '0');
   bussci3_tx.ack     <= '0';
   bussci3_tx.nack    <= '0';
@@ -318,8 +309,6 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_RS
 ---------------------------------------------------------------------------
 -- PCSD: not used
 ---------------------------------------------------------------------------    
-  tx_pll_lol_qd_d_i <= '0';
-
   bussci4_tx.data    <= (others => '0');
   bussci4_tx.ack     <= '0';
   bussci4_tx.nack    <= '0';
@@ -334,9 +323,8 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_RS
     CLK_REF              => clk_full_osc,
     TX_PLL_LOL_QD_A_IN   => tx_pll_lol_qd_a_i,
     TX_PLL_LOL_QD_B_IN   => tx_pll_lol_qd_b_i,
-    TX_PLL_LOL_QD_C_IN   => tx_pll_lol_qd_c_i,
-    TX_PLL_LOL_QD_D_IN   => tx_pll_lol_qd_d_i,
-    TX_PLL_LOL_OUT       => tx_pll_lol_all_i,
+    TX_PLL_LOL_QD_C_IN   => '0',
+    TX_PLL_LOL_QD_D_IN   => '0',
     TX_CLOCK_AVAIL_IN    => tx_clk_avail_i,
     TX_PCS_RST_CH_C_OUT  => tx_pcs_rst_i,
     SYNC_TX_QUAD_OUT     => sync_tx_quad_i,
@@ -380,11 +368,10 @@ THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_all_RS
     WORD_SYNC_OUT      => open, 
     MASTER_CLK_IN      => master_clk_i,
     MASTER_CLK_OUT     => open,
-    QUAD_RST_IN        => global_reset_i,
-    GLOBAL_RESET_OUT   => open,
+    QUAD_RST_IN        => '0', --global_reset_i,
+    LINK_TX_NULL_IN    => global_reset_i,
+    LINK_RX_NULL_OUT   => open,
     SLAVE_ACTIVE_OUT   => open,
-    SLAVE_ACTIVE_IN    => slave_active_i,
-    TX_PLL_LOL_IN      => tx_pll_lol_all_i,
     TX_PLL_LOL_OUT     => tx_pll_lol_qd_a_i,
     TX_CLK_AVAIL_OUT   => open,
     TX_PCS_RST_IN      => tx_pcs_rst_i,

diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index 6019db43dafbd078ac08d4deab010fa590b6e87e..a0891b8ecd900f1b55834df76a64970c47924f18 100644 (file)
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -225,8 +225,6 @@ architecture trb3sc_arch of trb3sc_cts is
   signal enable_dlm_i                : std_logic;
   
   signal tx_pll_lol_qd_b_i           : std_logic;
-  signal tx_pll_lol_all_i            : std_logic;
-  signal tx_clk_avail_i              : std_logic;
   signal sync_tx_quad_i              : std_logic;
   signal link_tx_ready_i             : std_logic;
   signal tx_pcs_rst_i                : std_logic;
@@ -256,8 +254,9 @@ architecture trb3sc_arch of trb3sc_cts is
 
   signal wap_requested_i             : std_logic_vector(3 downto 0);
   
-  signal slv_act_cnt                 : unsigned(7 downto 0);
+  signal slv_act_cnt                 : unsigned(15 downto 0);
   signal slave_active_fake           : std_logic;
+  signal send_reset_i                : std_logic;
   
 --  attribute syn_keep : boolean;
 --  attribute syn_preserve : boolean;  
@@ -332,7 +331,9 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
     end if;
   end process THE_SLAVE_ACTIVE_FAKE_PROC;
 
-  slave_active_fake <= std_logic(slv_act_cnt(7));
+  slave_active_fake <= std_logic(slv_act_cnt(9));
+  
+  send_reset_i      <= not slave_active_fake;
   
   pll_calibration : entity work.pll_in125_out33
     port map (
@@ -390,12 +391,11 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
       MASTER_CLK_IN      => master_clk_i,
       MASTER_CLK_OUT     => open,
       QUAD_RST_IN        => '0', -- check
-      GLOBAL_RESET_OUT   => open,
+      LINK_TX_NULL_IN    => send_reset_i,
+      LINK_RX_NULL_OUT   => open,
       SLAVE_ACTIVE_OUT   => open,
-      SLAVE_ACTIVE_IN    => slave_active_fake,
-      TX_PLL_LOL_IN      => tx_pll_lol_all_i,
       TX_PLL_LOL_OUT     => tx_pll_lol_qd_b_i,
-      TX_CLK_AVAIL_OUT   => tx_clk_avail_i,
+      TX_CLK_AVAIL_OUT   => open,
       TX_PCS_RST_IN      => tx_pcs_rst_i,
       SYNC_TX_PLL_IN     => sync_tx_quad_i,
       LINK_TX_READY_IN   => link_tx_ready_i,
@@ -436,8 +436,7 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
     TX_PLL_LOL_QD_B_IN   => tx_pll_lol_qd_b_i,
     TX_PLL_LOL_QD_C_IN   => '0',
     TX_PLL_LOL_QD_D_IN   => '0',
-    TX_PLL_LOL_OUT       => tx_pll_lol_all_i,
-    TX_CLOCK_AVAIL_IN    => tx_clk_avail_i,
+    TX_CLOCK_AVAIL_IN    => '1',
     TX_PCS_RST_CH_C_OUT  => tx_pcs_rst_i,
     SYNC_TX_QUAD_OUT     => sync_tx_quad_i,
     LINK_TX_READY_OUT    => link_tx_ready_i,