fix clock for reset register

diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd
index d4b4147bcf47a76ede120412e0cda9854faa0a02..84d5536d87d5f913a29e23fd77da7e4721a055fe 100644 (file)
--- a/code/clock_reset_handler.vhd
+++ b/code/clock_reset_handler.vhd
@@ -109,10 +109,10 @@ THE_RESET_HANDLER : trb_net_reset_handler
   );  
 
 RESET_OUT <= reset_i;
-send_reset_detect <= SEND_RESET_IN when rising_edge(clock_200_raw);
+send_reset_detect <= SEND_RESET_IN when rising_edge(sys_clk_i);
 trb_reset_i <= RESET_FROM_NET or (send_reset_detect and not SEND_RESET_IN);
 
-last_reset_i <= reset_i when rising_edge(clock_200_raw);
+last_reset_i <= reset_i when rising_edge(sys_clk_i);
 reset_rising <= reset_i and not last_reset_i;
   
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