signal first_bits_slow : std_logic;
signal reg_MBS_IN : std_logic;
signal done : std_logic;
+signal done_slow : std_logic;
signal number_reg : std_logic_vector(23 downto 0);
signal status_reg : std_logic_vector(1 downto 0);
type state_t is (IDLE, WAIT1,WAIT2,WAIT3,WAIT4, FINISH);
signal state : state_t;
-type rdo_state_t is (RDO_IDLE, RDO_WRITE, RDO_FINISH);
+type rdo_state_t is (RDO_IDLE, RDO_WAIT, RDO_WRITE, RDO_FINISH);
signal rdostate : rdo_state_t;
signal config_rdo_disable_i : std_logic;
case state is
when IDLE =>
bitcnt <= 37;
+ done <= '1';
if reg_MBS_IN = '0' then
done <= '0';
state <= WAIT1;
end if;
end process;
+done_slow <= done when rising_edge(CLK);
+
PROC_REG_INFO : process begin
wait until rising_edge(CLK);
- if done = '1' then
+ if done_slow = '1' then
number_reg <= shift_reg(31 downto 8);
status_reg <= shift_reg(7 downto 6);
case rdostate is
when RDO_IDLE =>
if TRIGGER_IN = '1' and config_rdo_disable_i = '0' then
- rdostate <= RDO_FINISH;
- DATA_OUT <= error_reg & status_reg & "00000" & number_reg;
- WRITE_OUT <= '1';
+ if done_slow = '0' then
+ rdostate <= RDO_WAIT;
+ else
+ rdostate <= RDO_WRITE;
+ end if;
end if;
+ when RDO_WAIT =>
+ if done_slow = '1' then
+ rdostate <= RDO_WRITE;
+ end if;
+ when RDO_WRITE =>
+ rdostate <= RDO_FINISH;
+ DATA_OUT <= error_reg & status_reg & "00000" & number_reg;
+ WRITE_OUT <= '1';
+
when RDO_FINISH =>
FINISHED_OUT <= '1';
rdostate <= RDO_IDLE;
config_rdo_disable_i <= CONTROL_REG_IN(0);
-STATUS_REG_OUT <= error_reg & reg_MBS_IN & std_logic_vector(to_unsigned(bitcnt,6)) & number_reg;
-DEBUG <= x"0000" & done & reg_MBS_IN & shift_reg(13 downto 0);
+STATUS_REG_OUT <= error_reg & '0' & std_logic_vector(to_unsigned(bitcnt,6)) & number_reg;
+DEBUG <= x"00000000"; -- & done & '0' & shift_reg(13 downto 0);
end architecture;
\ No newline at end of file
###################################################################################
#Settings for this project
my $TOPNAME = "trb3_central"; #Name of top-level entity
-my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105';
-# my $synplify_path = '/d/jspc29/lattice/synplify/fpga_e201103/';
+my $lattice_path = '/d/jspc29/lattice/diamond/2.0';
my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
execute($c);
-$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
+$c=qq|multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
execute($c);
# IOR IO Timing Report
-n 1
-y
-s 12
--t 5
+-t 8
-c 1
-e 2
#-g guidefile.ncd
# BLKNAME THE_CTS;\r
# LOCATE UGROUP "cts_group" REGION "REGION_CTS"; \r
MULTICYCLE TO CELL "THE_CMB/trg_sync" 20 ns;\r
-\r
+MULTICYCLE TO CELL "THE_CMB/error_reg" 20 ns;\r
\r
#TrbNet Hub \r
REGION "REGION_IOBUF" "R54C90D" 60 86 DEVSIZE;\r
#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/TDC.vhd"
#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/up_counter.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/trb3_periph.vhd"
-##add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Adder_304.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/bit_sync.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Channel.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Encoder_304_Bit.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/FIFO_32x32_OutReg.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Reference_channel.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/ROM_encoder_3.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/ROM_FIFO.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/TDC.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/up_counter.vhd"
-
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/trb3_periph.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Adder_304.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/bit_sync.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Channel.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Channel_200.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Encoder_304_Bit.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/FIFO_32x32_OutReg.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Reference_Channel.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/ROM_encoder_3.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/ROM_FIFO.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/TDC.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/up_counter.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/trb3_periph.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Adder_304.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/bit_sync.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Channel.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Channel_200.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Encoder_304_Bit.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/FIFO_32x32_OutReg.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Reference_channel.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/ROM_encoder_3.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/ROM_FIFO.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/TDC.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/up_counter.vhd"
+
+# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/trb3_periph.vhd"
+# #add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Adder_304.vhd"
+# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/bit_sync.vhd"
+# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Channel.vhd"
+# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Channel_200.vhd"
+# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Encoder_304_Bit.vhd"
+# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/FIFO_32x32_OutReg.vhd"
+# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Reference_Channel.vhd"
+# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/ROM_encoder_3.vhd"
+# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/ROM_FIFO.vhd"
+# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/TDC.vhd"
+# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/up_counter.vhd"
entity trb3_central is
generic (
- USE_ETHERNET : integer range c_NO to c_YES := c_YES
+ USE_ETHERNET : integer range c_NO to c_YES := c_NO
);
port(
--Clocks
MII_IS_DOWNLINK => (4 => 0, others => 1),
MII_IS_UPLINK_ONLY=> (4 => 1, others => 0),
INT_NUMBER => 0,
- INT_CHANNELS => (0,1,3,3,3,3,3,3),
+ INT_CHANNELS => (others => 0),
USE_ONEWIRE => c_YES,
COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
- HARDWARE_VERSION => x"90000000",
+ HARDWARE_VERSION => x"90000030",
INIT_ENDPOINT_ID => x"0005",
INIT_ADDRESS => x"F305",
BROADCAST_SPECIAL_ADDR => x"40"
CTRL_DEBUG => (others => '0'),
STAT_DEBUG => open
);
+
+ reset_via_gbe <= '0';
end generate;
gen_ethernet_hub : if USE_ETHERNET = c_YES generate
###################################################################################
#Settings for this project
my $TOPNAME = "panda_dirc_wasa"; #Name of top-level entity
-my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105';
+my $lattice_path = '/d/jspc29/lattice/diamond/2.0';
my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
`timescale 1ns / 100ps
`include "efb_define_def.v"
+`include "/d/jspc29/lattice/diamond/2.0/ispfpga/verilog/data/machxo2/GSR.v"
+`include "/d/jspc29/lattice/diamond/2.0/ispfpga/verilog/data/machxo2/PUR.v"
module UFM_WB(
input clk_i
reg[4:0] n_count;
reg n_ufm_addr_MSB;
+ PUR PUR_INST (.PUR(1'b1));
+ GSR GSR_INST (.GSR(1'b1));
+
flash inst1 ( .wb_clk_i(clk_i ), // EFB with UFM enabled
.wb_rst_i(!rst_n ),
.wb_cyc_i(wb_cyc_i ),
begin
sm_rd_data <= mem_rd_data;
mem_we <= sm_we;
+ mem_ce <= sm_ce;
mem_clk <= clk_i;
mem_addr <= sm_addr;
mem_wr_data <= sm_wr_data;
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="flash" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2012 08 09 14:22:13.751" version="1.0" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="flash" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2012 12 10 14:50:18.087" version="1.1" type="Module" synthesis="" source_format="VHDL">
<Package>
- <File name="flash.lpc" type="lpc" modified="2012 08 09 14:22:11.000"/>
- <File name="flash.vhd" type="top_level_vhdl" modified="2012 08 09 14:22:11.000"/>
- <File name="flash_tmpl.vhd" type="template_vhdl" modified="2012 08 09 14:22:11.000"/>
+ <File name="flash.lpc" type="lpc" modified="2012 12 10 14:50:11.000"/>
+ <File name="flash.vhd" type="top_level_vhdl" modified="2012 12 10 14:50:11.000"/>
+ <File name="flash_tmpl.vhd" type="template_vhdl" modified="2012 12 10 14:50:11.000"/>
</Package>
</DiamondModule>
CoreType=LPM
CoreStatus=Demo
CoreName=EFB
-CoreRevision=1.0
+CoreRevision=1.1
ModuleName=flash
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=08/09/2012
-Time=14:22:11
+Date=12/10/2012
+Time=14:50:11
[Parameters]
Verilog=0
--- VHDL netlist generated by SCUBA Diamond_1.4_Production (87)
--- Module Version: 1.0
---/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 33.33 -ufm -ufm_ebr 0 -mem_size 767 -ufm_0 -wb -dev 4000 -e
+-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
+-- Module Version: 1.1
+--/d/jspc29/lattice/diamond/2.0/ispfpga/bin/lin/scuba -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 33.33 -ufm -ufm_ebr 0 -mem_size 767 -ufm_0 -wb -dev 4000 -e
--- Thu Aug 9 14:22:11 2012
+-- Mon Dec 10 14:50:11 2012
library IEEE;
use IEEE.std_logic_1164.all;
--- -- synopsys translate_off
+-- synopsys translate_off
library MACHXO2;
use MACHXO2.components.all;
--- -- synopsys translate_on
+-- synopsys translate_on
entity flash is
port (
SPI_PHASE_ADJ=> "DISABLED", SPI_CLK_INV=> "DISABLED",
SPI_LSB_FIRST=> "DISABLED", SPI_CLK_DIVIDER=> 1, SPI_MODE=> "MASTER",
EFB_SPI=> "DISABLED", I2C2_WAKEUP=> "DISABLED", I2C2_GEN_CALL=> "DISABLED",
- I2C2_CLK_DIVIDER=> 1, I2C2_BUS_PERF=> "100kHz", I2C2_SLAVE_ADDR=> "0b0011001",
+ I2C2_CLK_DIVIDER=> 1, I2C2_BUS_PERF=> "100kHz", I2C2_SLAVE_ADDR=> "0b1000010",
I2C2_ADDRESSING=> "7BIT", EFB_I2C2=> "DISABLED", I2C1_WAKEUP=> "DISABLED",
I2C1_GEN_CALL=> "DISABLED", I2C1_CLK_DIVIDER=> 1, I2C1_BUS_PERF=> "100kHz",
- I2C1_SLAVE_ADDR=> "0b0011001", I2C1_ADDRESSING=> "7BIT",
+ I2C1_SLAVE_ADDR=> "0b1000001", I2C1_ADDRESSING=> "7BIT",
EFB_I2C1=> "DISABLED", EFB_WB_CLK_FREQ=> "33.3")
port map (WBCLKI=>wb_clk_i, WBRSTI=>wb_rst_i, WBCYCI=>wb_cyc_i,
WBSTBI=>wb_stb_i, WBWEI=>wb_we_i, WBADRI7=>wb_adr_i(7),
signal inp_gated : std_logic_vector(15 downto 0);\r
signal inp_hold_reg: std_logic_vector(15 downto 0);\r
signal last_inp_hold_reg: std_logic_vector(15 downto 0);\r
+signal flash_go_tmp : std_logic_vector(5 downto 0);\r
+signal flash_reset_n : std_logic;\r
+\r
+signal pwm_data_i : std_logic_vector(15 downto 0);\r
+signal pwm_data_o : std_logic_vector(15 downto 0);\r
+signal pwm_write_i : std_logic;\r
+signal pwm_addr_i : std_logic_vector(3 downto 0);\r
+type fsm_state is (IDLE, PWM_WRITE_GET_1, PWM_WRITE_GET_2, PWM_WRITE, PWM_WAIT);\r
+signal fsm_copydat : fsm_state;\r
+\r
+signal pwm_fsm_data_i : std_logic_vector(15 downto 0);\r
+signal pwm_fsm_addr : std_logic_vector(3 downto 0);\r
+signal pwm_fsm_write : std_logic;\r
+signal fsm_job : std_logic_vector(1 downto 0);\r
+signal ram_fsm_data_i : std_logic_vector(7 downto 0);\r
+signal ram_fsm_addr_i : std_logic_vector(3 downto 0);\r
+signal ram_fsm_write_i: std_logic;\r
\r
begin\r
\r
--- PROC_RESET : process begin\r
--- wait until rising_edge(clk_osc);\r
--- reset_i <= not pll_lock;\r
--- -- if reset_cnt /= x"F" then\r
--- -- reset_cnt <= reset_cnt + 1;\r
--- -- reset_i <= '1';\r
--- -- end if;\r
--- end process;\r
-\r
-\r
\r
THE_PLL : pll\r
port map(\r
-- RAM Interface\r
--------------------------------------------------------------------------- \r
\r
-ram_write_i <= spi_write_i(4); --or signal from Flash entity\r
-ram_data_i <= spi_data_i(7 downto 0); --or signal from Flash entity\r
-ram_addr_i <= spi_channel_i(3 downto 0); --or signal from Flash entity\r
\r
-spi_reg40_i <= x"00" & ram_data_o;\r
+spi_reg40_i <= flash_busy & flash_err & "000000" & ram_data_o;\r
+\r
\r
\r
+PROC_CTRL_FLASH : process begin\r
+ wait until rising_edge(clk_i);\r
+ if(spi_write_i(5) = '1' and spi_channel_i(7 downto 4) = x"0") then\r
+ flash_command <= spi_data_i(14 downto 12);\r
+ flash_page <= spi_data_i(10 downto 0);\r
+ flash_go_tmp(0)<= '1';\r
+ else\r
+ flash_go_tmp(5 downto 0) <= flash_go_tmp(4 downto 0) & '0';\r
+ end if;\r
+ if flash_reset_n = '0' then\r
+ flash_go_tmp <= (others => '0');\r
+ end if;\r
+end process;\r
+\r
+ flash_go <= or_all(flash_go_tmp);\r
+\r
THE_FLASH_RAM : flashram\r
port map(\r
DataInA => ram_data_i,\r
-- Flash Controller\r
--------------------------------------------------------------------------- \r
\r
--- THE_FLASH : UFM_WB\r
--- port map(\r
--- clk_i => clk_26,\r
--- rst_n => '1',\r
--- cmd => flash_command,\r
--- ufm_page => flash_page,\r
--- GO => flash_go,\r
--- BUSY => flash_busy,\r
--- ERR => flash_err,\r
--- mem_clk => open,\r
--- mem_we => flashram_write_i,\r
--- mem_ce => flashram_cen_i,\r
--- mem_addr => flashram_addr_i,\r
--- mem_wr_data => flashram_data_i,\r
--- mem_rd_data => flashram_data_o\r
--- );\r
+THE_FLASH : UFM_WB\r
+ port map(\r
+ clk_i => clk_26,\r
+ rst_n => flash_reset_n,\r
+ cmd => flash_command,\r
+ ufm_page => flash_page,\r
+ GO => flash_go,\r
+ BUSY => flash_busy,\r
+ ERR => flash_err,\r
+ mem_clk => open,\r
+ mem_we => flashram_write_i,\r
+ mem_ce => flashram_cen_i,\r
+ mem_addr => flashram_addr_i,\r
+ mem_wr_data => flashram_data_i,\r
+ mem_rd_data => flashram_data_o\r
+ );\r
+\r
+PROC_DATA_COPY : process \r
+ variable count : integer range 0 to 31 := 0;\r
+ variable tmp : std_logic_vector(7 downto 0);\r
+begin\r
+ wait until rising_edge(clk_i);\r
+ pwm_fsm_write <= '0';\r
+ ram_fsm_write_i <= '0';\r
+ case fsm_copydat is\r
+ when IDLE => \r
+ count := 0;\r
+ if spi_write_i(5) = '1' and spi_channel_i(7 downto 4) = x"1" then\r
+ fsm_copydat <= PWM_WRITE_GET_1;\r
+ ram_fsm_addr_i <= std_logic_vector(to_unsigned(count,4));\r
+ fsm_job <= spi_channel_i(1 downto 0);\r
+ count := count + 1;\r
+ end if;\r
+ when PWM_WRITE_GET_1 =>\r
+ ram_fsm_addr_i <= std_logic_vector(to_unsigned(count,4));\r
+ count := count + 1;\r
+ fsm_copydat <= PWM_WRITE_GET_2;\r
+ when PWM_WRITE_GET_2 =>\r
+ fsm_copydat <= PWM_WRITE;\r
+ tmp := ram_data_o;\r
+ when PWM_WRITE =>\r
+ pwm_fsm_data_i <= tmp & ram_data_o;\r
+ pwm_fsm_write <= '1';\r
+ pwm_fsm_addr <= fsm_job(0) & std_logic_vector(to_unsigned(count/2-1,3));\r
+ \r
+ if(count < 15) then\r
+ fsm_copydat <= PWM_WRITE_GET_1;\r
+ else\r
+ fsm_copydat <= PWM_WAIT;\r
+ end if;\r
+ \r
+ ram_fsm_addr_i <= std_logic_vector(to_unsigned(count,4));\r
+ count := count + 1;\r
+ \r
+ when PWM_WAIT =>\r
+ fsm_copydat <= IDLE;\r
+ end case;\r
+ if onewire_reset = '1' then\r
+ fsm_copydat <= IDLE;\r
+ end if;\r
+end process;\r
\r
- \r
--- PUR_INST : PUR port map(PUR=>'1');\r
--- GSR_INST : GSR port map(GSR=>'1');\r
---------------------------------------------------------------------------\r
-- PWM\r
--------------------------------------------------------------------------- \r
THE_PWM_GEN : pwm_generator\r
port map(\r
CLK => clk_i,\r
- DATA_IN => spi_data_i,\r
- DATA_OUT => spi_reg00_i,\r
- WRITE_IN => spi_write_i(0),\r
- ADDR_IN => spi_channel_i(3 downto 0),\r
+ DATA_IN => pwm_data_i,\r
+ DATA_OUT => pwm_data_o,\r
+ WRITE_IN => pwm_write_i,\r
+ ADDR_IN => pwm_addr_i,\r
PWM => pwm_i\r
);\r
\r
PWM <= pwm_i(15 downto 0);\r
\r
--- PWM_ODDR : oddr16\r
--- port map(\r
--- clk => clk_i,\r
--- clkout => open,\r
--- reset => '0',\r
--- sclk => open,\r
--- dataout => pwm_i,\r
--- dout => PWM\r
--- );\r
+spi_reg00_i <= pwm_data_o;\r
+\r
+PROC_PWM_DATA_MUX : process(fsm_copydat, spi_data_i, spi_write_i, spi_channel_i,\r
+ pwm_fsm_addr, pwm_fsm_data_i, pwm_fsm_write,\r
+ ram_fsm_addr_i, ram_fsm_data_i, ram_fsm_write_i)\r
+begin\r
+ if(fsm_copydat = IDLE) then\r
+ pwm_data_i <= spi_data_i;\r
+ pwm_write_i <= spi_write_i(0);\r
+ pwm_addr_i <= spi_channel_i(3 downto 0);\r
+ ram_write_i <= spi_write_i(4);\r
+ ram_data_i <= spi_data_i(7 downto 0);\r
+ ram_addr_i <= spi_channel_i(3 downto 0);\r
+ else\r
+ pwm_data_i <= pwm_fsm_data_i;\r
+ pwm_write_i <= pwm_fsm_write;\r
+ pwm_addr_i <= pwm_fsm_addr;\r
+ ram_write_i <= ram_fsm_write_i;\r
+ ram_data_i <= ram_fsm_data_i;\r
+ ram_addr_i <= ram_fsm_addr_i;\r
+ end if;\r
+end process;\r
+\r
\r
\r
- \r
---------------------------------------------------------------------------\r
-- Temperature Sensor\r
--------------------------------------------------------------------------- \r
end if;\r
end process;\r
\r
-\r
+flash_reset_n <= not onewire_reset;\r
\r
---------------------------------------------------------------------------\r
-- I/O Register 0x20\r
\r
inp_status <= INP when rising_edge(clk_i);\r
last_inp <= inp_status(3 downto 0) when rising_edge(clk_i);\r
+\r
+\r
---------------------------------------------------------------------------\r
-- LED blinking when activity on inputs\r
---------------------------------------------------------------------------\r
SPARE_LINE(3) <= '0';\r
\r
\r
-\r
--- process(inp_gated,clk_i); \r
--- begin\r
--- if inp_gated(i) then\r
--- inp_hold(i) <= inp_gated(i);\r
--- elsif rising_edge(clk_i) then\r
--- inp_hold(i) <= inp_hold(i) and not inp_hold_reg(i);\r
--- end if;\r
--- end process;\r
--- \r
-\r
inp_hold <= (inp_gated or inp_hold) and not inp_hold_reg;\r
inp_hold_reg <= inp_hold when rising_edge(clk_i);\r
last_inp_hold_reg <= inp_hold_reg when rising_edge(clk_i);\r
-- TEST_LINE(0) <= '0';\r
-- TEST_LINE(15 downto 1) <= (others => '0');\r
\r
-TEST_LINE(7 downto 0) <= spi_debug_i(7 downto 0);\r
-TEST_LINE(10 downto 8) <= id_addr_i(2 downto 0);\r
-TEST_LINE(11) <= onewire_monitor;\r
-TEST_LINE(12) <= id_write_i;\r
-TEST_LINE(15 downto 13) <= id_data_i(2 downto 0);\r
+-- TEST_LINE(0) <= '0';\r
+-- TEST_LINE(1) <= spi_write_i(5);\r
+-- TEST_LINE(2) <= pwm_write_i;\r
+-- TEST_LINE(3) <= ram_write_i;\r
+-- TEST_LINE(7 downto 4) <= pwm_addr_i;\r
+-- TEST_LINE(11 downto 8) <= ram_addr_i;\r
+-- TEST_LINE(12) <= spi_write_i(4);\r
+-- TEST_LINE(13) <= ;\r
+-- TEST_LINE(14) <= '1' when fsm_copydat = PWM_WRITE_GET_1 or fsm_copydat = PWM_WRITE_GET_2 else '0';\r
+-- TEST_LINE(15) <= '1' when fsm_copydat = PWM_WRITE_GET_2 or fsm_copydat = PWM_WRITE else '0';\r
+-- \r
+\r
\r
LED_GREEN <= not leds(0) when led_status(4) = '0' else not led_status(0);\r
LED_ORANGE <= not leds(1) when led_status(4) = '0' else not led_status(1);\r
\r
end architecture;\r
\r
+\r
+\r
+\r
+-- PWM_ODDR : oddr16\r
+-- port map(\r
+-- clk => clk_i,\r
+-- clkout => open,\r
+-- reset => '0',\r
+-- sclk => open,\r
+-- dataout => pwm_i,\r
+-- dout => PWM\r
+-- );\r
+\r
+-- PROC_RESET : process begin\r
+-- wait until rising_edge(clk_osc);\r
+-- reset_i <= not pll_lock;\r
+-- -- if reset_cnt /= x"F" then\r
+-- -- reset_cnt <= reset_cnt + 1;\r
+-- -- reset_i <= '1';\r
+-- -- end if;\r
+-- end process;\r
+\r
+\r
+-- process(inp_gated,clk_i); \r
+-- begin\r
+-- if inp_gated(i) then\r
+-- inp_hold(i) <= inp_gated(i);\r
+-- elsif rising_edge(clk_i) then\r
+-- inp_hold(i) <= inp_hold(i) and not inp_hold_reg(i);\r
+-- end if;\r
+-- end process;\r
+-- \r
UserTimeUnit = default
; Default run length
-RunLength = 10 us
+RunLength = 200 us
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
-Project_Files_Count = 17
+Project_Files_Count = 18
Project_File_0 = /d/jspc22/trb/cvs/trb3/wasa/cores/efb_define_def.v
-Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1344528395 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1344528395 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = /d/jspc22/trb/cvs/trbnet/trb_net_components.vhd
-Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346851369 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346851369 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_2 = /d/jspc22/trb/cvs/trb3/wasa/source/pwm.vhd
-Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346679540 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_3 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/full_tb.vhd
-Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346680480 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_4 = /d/jspc22/trb/cvs/trb3/wasa/source/spi_slave.vhd
-Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346854393 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_5 = /d/jspc22/trb/cvs/trb3/wasa/version.vhd
-Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346921672 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_6 = /d/jspc22/trb/cvs/trb3/base/trb3_components.vhd
-Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346765030 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_7 = /d/jspc22/trb/cvs/trb3/wasa/panda_dirc_wasa.vhd
-Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346921711 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_8 = /d/jspc22/trb/cvs/trbnet/trb_net_std.vhd
-Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346849814 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_9 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/pwm_tb.vhd
-Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344272681 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_10 = /d/jspc22/trb/cvs/trb3/wasa/cores/UFM_WB.v
-Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1344852401 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+/d/jspc22/trb/cvs/trb3/wasa/cores\7f compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_11 = /d/jspc22/trb/cvs/trbnet/trb_net_onewire.vhd
-Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344350049 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_12 = /d/jspc22/trb/cvs/trbnet/special/spi_ltc2600.vhd
-Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344353596 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_13 = /d/jspc22/trb/cvs/trb3/wasa/cores/flash.vhd
-Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344852431 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355218918 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_3 = /d/jspc22/trb/cvs/trb3/tdc_test/modelsim/sim_pulsestretch.vhd
+Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1348848169 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_4 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/full_tb.vhd
+Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355226184 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_5 = /d/jspc22/trb/cvs/trb3/wasa/source/spi_slave.vhd
+Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346854393 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_6 = /d/jspc22/trb/cvs/trb3/wasa/version.vhd
+Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355228266 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_7 = /d/jspc22/trb/cvs/trb3/base/trb3_components.vhd
+Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1348839333 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_8 = /d/jspc22/trb/cvs/trb3/wasa/panda_dirc_wasa.vhd
+Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355228319 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_9 = /d/jspc22/trb/cvs/trbnet/trb_net_std.vhd
+Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346849814 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_10 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/pwm_tb.vhd
+Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344272681 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_11 = /d/jspc22/trb/cvs/trb3/wasa/cores/UFM_WB.v
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1355162337 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+/d/jspc22/trb/cvs/trb3/wasa/cores\7f compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_12 = /d/jspc22/trb/cvs/trbnet/trb_net_onewire.vhd
+Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344350049 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 12 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_13 = /d/jspc22/trb/cvs/trbnet/special/spi_ltc2600.vhd
+Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1350664433 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_14 = /d/jspc22/trb/cvs/trb3/wasa/cores/flashram.vhd
-Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344516091 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_15 = /d/jspc22/trb/cvs/trb3/wasa/cores/oddr16.vhd
-Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344002544 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344516091 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 14 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_15 = /d/jspc22/trb/cvs/trb3/wasa/cores/flash.vhd
+Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355147411 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_16 = /d/jspc22/trb/cvs/trb3/wasa/cores/pll.vhd
-Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346849713 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 15 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346849713 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_17 = /d/jspc22/trb/cvs/trb3/wasa/cores/oddr16.vhd
+Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344002544 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
WRITE_IN : in std_logic := '0';
ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0');
+
PWM : out std_logic_vector(31 downto 0)
);
process begin
wait for 101 ns;
bus_addr <= "00000";
- bus_data <= x"0010abcd";
+ bus_data <= x"51800000";
bus_write <= '1';
wait for 10 ns;
bus_write <= '0';
wait for 10010 ns;
bus_addr <= "00000";
- bus_data <= x"0013cd46";
+ bus_data <= x"51810000";
bus_write <= '1';
wait for 10 ns;
bus_write <= '0';
BROADCAST_BITMASK => x"FF",
BROADCAST_SPECIAL_ADDR => x"48",
REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"91004060",
+ REGIO_HARDWARE_VERSION => x"91004950",
REGIO_INIT_ADDRESS => x"f306",
REGIO_USE_VAR_ENDPOINT_ID => c_YES,
CLOCK_FREQUENCY => 100,
CONTROL_REG_IN => ctrl_reg);
- hit_in_i <= INP;
+-- hit_in_i <= INP;
-- to detect rising & falling edges
--hit_in_i(1) <= not timing_trg_received_i;
- --Gen_Hit_In_Signals : for i in 1 to 15 generate
- -- hit_in_i(i*2) <= INPUT(i-1);
- -- hit_in_i(i*2+1) <= not INPUT(i-1);
- --end generate Gen_Hit_In_Signals;
+ Gen_Hit_In_Signals : for i in 0 to 31 generate
+ hit_in_i(i*2) <= INP(i);
+ hit_in_i(i*2+1) <= not INP(i);
+ end generate Gen_Hit_In_Signals;
end architecture;
jspc29 / trb3.git / commitdiff