increase coincidence window and delay from 150 to 630 ns.

diff --git a/cts/compile_central_frankfurt.pl b/cts/compile_central_frankfurt.pl
index 6678525db6c29afa5e560b6d6e1d1aba2b8272be..3101f6348c958ba9d375f26f67f98265061d986b 100755 (executable)
--- a/cts/compile_central_frankfurt.pl
+++ b/cts/compile_central_frankfurt.pl
@@ -17,7 +17,7 @@ my $lm_license_file_for_synplify = "27020\@jspc29"; #"27000\@lxcad01.gsi.de";
 my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
 
 my $lattice_path                 = '/d/jspc29/lattice/diamond/3.10_x64';
-my $synplify_path                = '/d/jspc29/lattice/synplify/O-2018.09-SP1';
+my $synplify_path                = '/d/jspc29/lattice/synplify/P-2019.09-SP1';
 ###################################################################################
 
 

diff --git a/cts/config_straw.vhd b/cts/config_straw.vhd
new file mode 100644 (file)
index 0000000..302d0dc
--- /dev/null
+++ b/cts/config_straw.vhd
@@ -0,0 +1,160 @@
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+package config is
+------------------------------------------------------------------------------
+--Begin of configuration
+------------------------------------------------------------------------------
+
+   constant INCLUDE_CTS : integer range c_NO to c_YES := c_YES;
+--    constant INCLUDE_CBMNET : integer range c_NO to c_YES := c_NO;
+   constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO; 
+   constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_NO;
+
+--include TDC for all four trigger input lines
+
+   constant INCLUDE_TDC : integer range c_NO to c_YES := c_NO;
+   constant TDC_CHANNEL_NUMBER : integer := 5;
+   constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 0;  --double edge type:  0, 1, 2,  3
+   -- 0: single edge only,
+   -- 1: same channel,
+   -- 2: alternating channels,
+   -- 3: same channel with stretcher
+   constant RING_BUFFER_SIZE        : integer range 0 to 7  := 7;  --ring buffer size:  0, 1, 2,  3,  7
+                                                                   --ring buffer size: 32,64,96,128,dyn
+-- Include SFP power readout
+   constant INCLUDE_SFP_DDM : integer range c_NO to c_YES := c_NO;
+   
+--use all four SFP (1-4) as downlink to other boards (only w/o CBMNET)
+    constant USE_4_SFP   : integer range c_NO to c_YES := c_YES;
+
+--Run wih 125 MHz instead of 100 MHz     
+    constant USE_125_MHZ : integer range c_NO to c_YES := c_NO;    
+
+--Run external 200 MHz clock source
+    constant USE_EXTERNAL_CLOCK : integer range c_NO to c_YES := c_YES;    
+       
+--Which external trigger module (ETM) to use?
+    constant INCLUDE_ETM : integer range c_NO to c_YES := c_NO;
+    type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26);
+    constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM;
+    
+    constant ETM_ID : std_logic_vector(7 downto 0);
+
+--output busy signal on pair 4 of Trigger RJ45?    
+    constant GEN_BUSY_OUTPUT : integer := c_NO;
+
+--CLK RJ 3&4 can be used as output multiplexers?    
+    constant USE_CLKRJ_AS_OUTMUX : integer := c_NO;
+    
+    constant TRIGGER_COIN_COUNT   : integer := 2;
+    constant TRIGGER_PULSER_COUNT : integer := 1;
+    constant TRIGGER_RAND_PULSER  : integer := 1;
+    constant TRIGGER_ADDON_COUNT  : integer := 8;
+    constant PERIPH_TRIGGER_COUNT : integer := 4;
+    constant ADDON_LINE_COUNT        : integer := 38;    
+    constant CTS_OUTPUT_MULTIPLEXERS : integer := 8;
+    
+------------------------------------------------------------------------------
+--End of configuration
+------------------------------------------------------------------------------
+   
+--Ports:
+--        LVL1/IPU       SCtrl
+--  0     FPGA 1         FPGA 1
+--  1     FPGA 2         FPGA 2
+--  2     FPGA 3         FPGA 3
+--  3     FPGA 4         FPGA 4
+--  4     opt. link      opt. link
+--  5-7   SFP 2-4
+--  5(8)  CTS read-out   internal         0 1 -   X X O   --downlink only
+--  6(9)  CTS TRG        Sctrl GbE        2 3 4   X X X   --uplink only
+ 
+------------------------------------------------------------------------------
+--Hub configuration 
+------------------------------------------------------------------------------
+    type hub_mii_t is array(0 to 1) of integer;    
+    type hub_ct    is array(0 to 16) of integer;
+    type hub_cfg_t is array(0 to 1) of hub_ct;    
+    type hw_info_t is array(0 to 1) of std_logic_vector(31 downto 0);
+    
+  --this is used to select the proper configuration in the main code    
+    constant CFG_MODE : integer;
+    
+    
+  --first entry is normal CTS with one optical output, second one is with four optical outputs
+  --slow-control is accepted on SFP1 only, triggers are sent to all used SFP
+    constant INTERNAL_NUM_ARR     : hub_mii_t := (5,5);
+    constant INTERFACE_NUM_ARR    : hub_mii_t := (5,8);
+--                                                 0 1 2 3 4 5 6 7 8 9 a b c d e f 
+    constant IS_UPLINK_ARR        : hub_cfg_t := ((0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0),
+                                                  (0,0,0,0,1,0,0,0,0,1,0,0,0,0,0,0,0));
+    constant IS_DOWNLINK_ARR      : hub_cfg_t := ((1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0),
+                                                  (1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0));
+    constant IS_UPLINK_ONLY_ARR   : hub_cfg_t := ((0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0),
+                                                  (0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0)); 
+    constant HARDWARE_INFO_ARR    : hw_info_t := (x"9000CEE0",x"9000CEE2");
+                          
+    constant INTERNAL_NUM         : integer;
+    constant INTERFACE_NUM        : integer;
+    constant IS_UPLINK            : hub_ct;
+    constant IS_DOWNLINK          : hub_ct;
+    constant IS_UPLINK_ONLY       : hub_ct;
+    constant HARDWARE_INFO        : std_logic_vector(31 downto 0);
+    
+    -- MII_NUMBER        => 5, --(8)
+    -- INT_NUMBER        => 5,
+    -- INT_CHANNELS      => (0,1,0,1,3),
+
+    -- No trigger / sctrl sent to optical link, slow control receiving possible
+    -- MII_IS_UPLINK        => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0);
+    -- MII_IS_DOWNLINK      => (1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0);
+    -- MII_IS_UPLINK_ONLY   => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0);
+
+    -- Trigger / sctrl sent to optical link, slow control receiving possible
+    -- MII_IS_UPLINK        => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0);
+    -- MII_IS_DOWNLINK      => (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0);
+    -- MII_IS_UPLINK_ONLY   => (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0);
+    -- & disable port 4 in c0 and c1 -- no triggers from/to optical link
+
+    -- Trigger / sctrl sent to 4 optical links
+    -- MII_IS_UPLINK        => (0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0,0);
+    -- MII_IS_DOWNLINK      => (1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0);
+    -- MII_IS_UPLINK_ONLY   => (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0);
+    -- & disable port 4 in c0 and c1 -- no triggers from/to optical link
+
+------------------------------------------------------------------------------
+--CTS configuration
+------------------------------------------------------------------------------
+    constant cts_rdo_additional_ports : integer;
+
+end;
+
+package body config is
+--compute correct configuration mode
+  constant CFG_MODE : integer := USE_4_SFP;
+  constant cts_rdo_additional_ports : integer := 1 + INCLUDE_TDC;
+
+  constant HARDWARE_INFO        : std_logic_vector (31 downto 0) := HARDWARE_INFO_ARR(INCLUDE_TDC);
+  constant INTERNAL_NUM         : integer := INTERNAL_NUM_ARR(CFG_MODE);
+  constant INTERFACE_NUM        : integer := INTERFACE_NUM_ARR(CFG_MODE);
+  constant IS_UPLINK            : hub_ct  := IS_UPLINK_ARR(CFG_MODE);
+  constant IS_DOWNLINK          : hub_ct  := IS_DOWNLINK_ARR(CFG_MODE);
+  constant IS_UPLINK_ONLY       : hub_ct  := IS_UPLINK_ONLY_ARR(CFG_MODE); 
+  
+  function etm_id_func return std_logic_vector is
+   variable res : unsigned(7 downto 0);
+  begin
+   res := x"00";
+   if INCLUDE_ETM=c_YES then
+      res := x"60";
+      res := res + TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4);
+   end if;
+   return std_logic_vector(res);
+  end function;
+  
+  constant ETM_ID : std_logic_vector(7 downto 0) := etm_id_func;
+  
+end package body;

diff --git a/cts/source/cts_pkg.vhd b/cts/source/cts_pkg.vhd
index d486dd287d31a886fbb34c1bfd4c634b985c6634..8fe25a05539e35d95c9cc7034e3a8ec5cb5e4114 100755 (executable)
--- a/cts/source/cts_pkg.vhd
+++ b/cts/source/cts_pkg.vhd
@@ -249,7 +249,7 @@ package cts_pkg is
       RST_IN      : in  std_logic;
       DATA_IN     : in  std_logic;
       DATA_OUT    : out std_logic;
-      CONFIG_IN   : in  std_logic_vector(10 downto 0) := (others => '0')
+      CONFIG_IN   : in  std_logic_vector(15 downto 0) := (others => '0')
    );
    end component;
    

diff --git a/cts/source/cts_trg_coin.vhd b/cts/source/cts_trg_coin.vhd
index 4fbe27f504d1e0409883daa9dc32340e123d5fd4..4721ad513325b752ffc473aaf663a433034982f3 100644 (file)
--- a/cts/source/cts_trg_coin.vhd
+++ b/cts/source/cts_trg_coin.vhd
@@ -12,7 +12,7 @@ library ieee;
 --          coincidence window.
 --   15:8   Inhibit bitmask. Corresponds to trigger input signals. Each mask channel
 --          has to be asserted.  
---   19:16  Coincidence window (0 to 15 clock cycles)
+--   21:16  Coincidence window (0 to 15 clock cycles)
 -- </reg_table>
 entity CTS_TRG_COIN is
    generic (
@@ -32,7 +32,7 @@ end CTS_TRG_COIN;
 
 architecture rtl of CTS_TRG_COIN is
    alias CONFIG_COIN_MASK_IN : STD_LOGIC_VECTOR(15 downto 0) is CONFIG_IN(15 downto 0);
-   alias CONFIG_WINDOW_IN : STD_LOGIC_VECTOR(3 downto 0) is CONFIG_IN(19 downto 16);
+   alias CONFIG_WINDOW_IN : STD_LOGIC_VECTOR(5 downto 0) is CONFIG_IN(21 downto 16);
 
    constant MAX_COIN_WINDOW : integer := 2**CONFIG_WINDOW_IN'LENGTH - 1;
 
@@ -102,4 +102,4 @@ begin
          config_window_i <= MAX_COIN_WINDOW;
       end if;
    end process;
-end architecture;
\ No newline at end of file
+end architecture;

diff --git a/cts/source/cts_trg_input.vhd b/cts/source/cts_trg_input.vhd
index 2427fa5b067f7c6d434f2de8c3f07e4cc4fc9b26..32c2614652a9b324d00748b8008e1bf306c749b3 100644 (file)
--- a/cts/source/cts_trg_input.vhd
+++ b/cts/source/cts_trg_input.vhd
@@ -5,11 +5,11 @@
 --    Bit   Description
 -- <reg_table name="cts_trg_input_register" >
 --          Input Module Configuration
---    3:0   Delay (0 to 15 cycles)
---    7:4   Spike Rejection. Number of clock cycles the signal has to be stably asserted until it is interpreted high.
---    8     Invert (0: Bypass, 1: Invert Input)
---    9     Override Enable (0: Bypass, 1: Set Value of 10. Bit)
---    10    Override Value
+--    5:0   Delay (0 to 15 cycles)
+--    11:8   Spike Rejection. Number of clock cycles the signal has to be stably asserted until it is interpreted high.
+--    12     Invert (0: Bypass, 1: Invert Input)
+--    13     Override Enable (0: Bypass, 1: Set Value of 10. Bit)
+--    14    Override Value
 -- </reg_table>
 
 library ieee;
@@ -22,13 +22,13 @@ entity CTS_TRG_INPUT is
       RST_IN      : in  std_logic;
       DATA_IN     : in  std_logic;
       DATA_OUT    : out std_logic;
-      CONFIG_IN   : in  std_logic_vector(10 downto 0) := (others => '0')
+      CONFIG_IN   : in  std_logic_vector(15 downto 0) := (others => '0')
    );
 end CTS_TRG_INPUT;
 
 architecture rtl of CTS_TRG_INPUT is
 -- setup
-   constant MAX_DELAY      : integer := 16;
+   constant MAX_DELAY      : integer := 64;
    constant MAX_SPIKE_REJ  : integer := 16;
 
 -- config mapping
@@ -101,9 +101,9 @@ begin
    end process;
    
 -- config mapping
-   config_delay_i    <= to_integer(unsigned(CONFIG_IN(3 downto 0)));
-   config_spike_i    <= to_integer(unsigned(CONFIG_IN(7 downto 4)));
-   config_invert_i   <= CONFIG_IN(8);
-   config_over_ena_i <= CONFIG_IN(9);
-   config_over_val_i <= CONFIG_IN(10);
+   config_delay_i    <= to_integer(unsigned(CONFIG_IN(5 downto 0)));
+   config_spike_i    <= to_integer(unsigned(CONFIG_IN(11 downto 8)));
+   config_invert_i   <= CONFIG_IN(12);
+   config_over_ena_i <= CONFIG_IN(13);
+   config_over_val_i <= CONFIG_IN(14);
 end architecture;

diff --git a/cts/source/cts_trigger.vhd b/cts/source/cts_trigger.vhd
index ada52fe053ab1475a8675cb6d6a395c9e968546f..99ffb8e70eb067bb60dab596b90473afffd93fa4 100755 (executable)
--- a/cts/source/cts_trigger.vhd
+++ b/cts/source/cts_trigger.vhd
@@ -113,7 +113,7 @@ architecture RTL of CTS_TRIGGER is
 -- Trigger Inputs (Spike Rejection, Negation, Override ...)
    signal triggers_i : std_logic_vector(EFFECTIVE_INPUT_COUNT - 1 downto 0);
 
-   type trigger_input_configs_t is array(EFFECTIVE_INPUT_COUNT - 1 downto 0) of std_logic_vector(10 downto 0);
+   type trigger_input_configs_t is array(EFFECTIVE_INPUT_COUNT - 1 downto 0) of std_logic_vector(15 downto 0);
    signal trigger_input_configs_i : trigger_input_configs_t;
 
    type   trigger_input_counters_t is array(EFFECTIVE_INPUT_COUNT - 1 downto 0) of unsigned(31 downto 0);
@@ -426,9 +426,9 @@ begin
             
             trigger_input_configs_i <= (others => (others => '0'));
             coin_config_i <= (others => X"000F0000");
-            pulser_interval_i <= (1 => X"00000003",  others => (others => '1'));
+--             pulser_interval_i <= (others => (others => '1'));
             
-            rand_pulser_threshold_i <= (others => (others => '0'));
+--             rand_pulser_threshold_i <= (others => (others => '0'));
 
             ext_control_i <= (others => '0');
             
@@ -510,10 +510,10 @@ begin
                   REGIO_DATAREADY_OUT <= REGIO_READ_ENABLE_IN;
                   REGIO_WRITE_ACK_OUT <= REGIO_WRITE_ENABLE_IN;
                   
-                  REGIO_DATA_OUT(10 downto 0) <= trigger_input_configs_i(i);
+                  REGIO_DATA_OUT(15 downto 0) <= trigger_input_configs_i(i);
                   
                   if REGIO_WRITE_ENABLE_IN = '1' then
-                     trigger_input_configs_i(i) <= REGIO_DATA_IN(10 downto 0);
+                     trigger_input_configs_i(i) <= REGIO_DATA_IN(15 downto 0);
                   end if;
                end if;
                ref_addr := ref_addr + 1;