architecture handler_ipu_arch of handler_ipu is
type cnt10_DAT_t is array (DATA_INTERFACE_NUMBER-1 downto 0) of unsigned(15 downto 0);
- type fsm_state_t is (IDLE, WAIT_FOR_LENGTH, GOT_LENGTH, WAITING_FOR_EVENT, SEND_DHDR, READ_DATA, END_READOUT);
+ type fsm_state_t is (IDLE, WAIT_FOR_LENGTH, WAITING_FOR_EVENT, SEND_DHDR, READ_DATA, END_READOUT);
signal current_state, next_state : fsm_state_t;
signal state_bits : std_logic_vector(3 downto 0);
end if;
when WAIT_FOR_LENGTH =>
- if DAT_HDR_DATA_EMPTY_IN = '0' then
- next_state <= WAITING_FOR_EVENT;
- else
- next_state <= GOT_LENGTH;
- end if;
-
- when GOT_LENGTH =>
+ --missing: compare data flags and hdr fifo data
+-- next_state <= GOT_LENGTH;
if last_hdr_fifo_valid_read = '1' then
next_state <= SEND_DHDR;
end if;
- --missing: compare data flags and hdr fifo data
+
+-- when GOT_LENGTH =>
+
+
when SEND_DHDR =>
next_ipu_data_i <= x"0" & DAT_HDR_DATA_IN(27 downto 0);
---------------------------------------------------------------------------
state_bits <= x"0" when current_state = IDLE
else x"1" when current_state = WAIT_FOR_LENGTH
- else x"2" when current_state = GOT_LENGTH
+-- else x"2" when current_state = GOT_LENGTH
else x"3" when current_state = SEND_DHDR
else x"4" when current_state = READ_DATA
else x"5" when current_state = END_READOUT