add master trigger output 3 and 4

diff --git a/backplanemaster/trb3sc_master.vhd b/backplanemaster/trb3sc_master.vhd
index cab6cb4a246a46f9b4a0c0555272da0b9c13ab22..b75b6280ff005a8dc11895e8ab24d6a9a4ac994e 100644 (file)
--- a/backplanemaster/trb3sc_master.vhd
+++ b/backplanemaster/trb3sc_master.vhd
@@ -831,6 +831,7 @@ end generate;
   BACK_LVDS(1) <= TRIG_LEFT;
 
   RJ_IO(3 downto 2) <= trig_gen_out_i(1 downto 0);  
+  RJ_IO(1 downto 0) <= trig_gen_out_i(3 downto 2);  
   
 ---------------------------------------------------------------------------
 -- Test Circuits