TRIGGER_COIN_COUNT : integer range 0 to 15 := 4;
TRIGGER_PULSER_COUNT: integer range 0 to 15 := 4;
TRIGGER_RAND_PULSER : integer range 0 to 1 := 1;
+
+ ADDON_LINE_COUNT : integer := 22; -- number of lines available from add-on board
+ TRIGGER_ADDON_COUNT : integer range 0 to 15 := 2; -- number of module instances used to patch through those lines
+
EXTERNAL_TRIGGER_ID : std_logic_vector(7 downto 0) := X"00";
TIME_REFERENCE_COUNT : positive := 10;
TRIGGER_BUSY_OUT : out std_logic;
TIME_REFERENCE_OUT : out std_logic;
+ ADDON_TRIGGERS_IN : in std_logic_vector(ADDON_LINE_COUNT-1 downto 0) := (others => '0');
+
-- External trigger logic
EXT_TRIGGER_IN : in std_logic;
EXT_STATUS_IN : in std_logic_vector(31 downto 0) := X"00000000";
signal input_counters_i,
input_counters_buf_i,
input_edge_counters_i,
- input_edge_counters_buf_i : std_logic_vector(32 * TRIGGER_INPUT_COUNT - 1 downto 0);
+ input_edge_counters_buf_i : std_logic_vector(32 * (TRIGGER_INPUT_COUNT+TRIGGER_ADDON_COUNT) - 1 downto 0);
signal channel_counters_i,
channel_counters_buf_i,
-- Trigger Distribution
-----------------------------------------
td_proc: process(CLK) is
- variable fee_input_counter_v : integer range 0 to 2*TRIGGER_INPUT_COUNT - 1 := 0;
+ variable fee_input_counter_v : integer range 0 to 2*(TRIGGER_INPUT_COUNT+TRIGGER_ADDON_COUNT) - 1 := 0;
variable fee_channel_counter_v : integer range 0 to 2* channel_counters_i'LENGTH / 32 - 1 := 0;
begin
-- write packet header
FEE_DATA_OUT(15 downto 0) <= trigger_bitmask_buf_i;
if ro_configuration_buf_i(0) = '1' then
- FEE_DATA_OUT(19 downto 16) <= STD_LOGIC_VECTOR(TO_UNSIGNED(TRIGGER_INPUT_COUNT, 4));
+ FEE_DATA_OUT(19 downto 16) <= STD_LOGIC_VECTOR(TO_UNSIGNED(TRIGGER_INPUT_COUNT+TRIGGER_ADDON_COUNT, 4));
end if;
if ro_configuration_buf_i(1) = '1' then
end if;
end if;
- if fee_input_counter_v = 2*TRIGGER_INPUT_COUNT - 1 or ro_configuration_buf_i(0) = '0' then
+ if fee_input_counter_v = 2*(TRIGGER_INPUT_COUNT+TRIGGER_ADDON_COUNT) - 1 or ro_configuration_buf_i(0) = '0' then
td_fsm_i <= TD_FSM_FEE_ENQUEUE_CHANNEL_COUNTER;
end if;
TRIGGER_COIN_COUNT => TRIGGER_COIN_COUNT,
TRIGGER_PULSER_COUNT => TRIGGER_PULSER_COUNT,
TRIGGER_RAND_PULSER => TRIGGER_RAND_PULSER,
+ ADDON_LINE_COUNT => ADDON_LINE_COUNT,
+ TRIGGER_ADDON_COUNT => TRIGGER_ADDON_COUNT,
EXTERNAL_TRIGGER_ID => EXTERNAL_TRIGGER_ID
)
port map (
RESET_IN => RESET,
TRIGGERS_IN => TRIGGERS_IN,
+ ADDON_TRIGGERS_IN => ADDON_TRIGGERS_IN,
EXT_TRIGGER_IN => EXT_TRIGGER_IN,
EXT_STATUS_IN => EXT_STATUS_IN,
TRIGGER_INPUT_COUNT : integer range 1 to 8 := 4;
TRIGGER_COIN_COUNT : integer range 0 to 15 := 4;
TRIGGER_PULSER_COUNT: integer range 0 to 15 := 4;
- TRIGGER_RAND_PULSER : integer range 0 to 15 := 1;
- EXTERNAL_TRIGGER_ID : std_logic_vector(7 downto 0) := X"00";
+ TRIGGER_RAND_PULSER : integer range 0 to 15 := 1;
+
+ ADDON_LINE_COUNT : integer range 0 to 255 := 22; -- number of lines available from add-on board
+ TRIGGER_ADDON_COUNT : integer range 0 to 15 := 2; -- number of module instances used to patch through those lines
+
+ EXTERNAL_TRIGGER_ID : std_logic_vector(7 downto 0) := X"00";
- TIME_REFERENCE_COUNT : positive := 10; -- Number of clock cycles the time reference needs to stay asserted (100ns)
- FIFO_ADDR_WIDTH : integer range 1 to 31 := 9 -- 2**(FIFO_ADDR_WIDTH-1) events can be stored in read-out buffer of CTS
+ TIME_REFERENCE_COUNT: positive := 10; -- Number of clock cycles the time reference needs to stay asserted (100ns)
+ FIFO_ADDR_WIDTH : integer range 1 to 31 := 9 -- 2**(FIFO_ADDR_WIDTH-1) events can be stored in read-out buffer of CTS
);
port (
TRIGGERS_IN : in std_logic_vector(TRIGGER_INPUT_COUNT-1 downto 0);
TRIGGER_BUSY_OUT : out std_logic;
TIME_REFERENCE_OUT : out std_logic;
+
+ ADDON_TRIGGERS_IN : in std_logic_vector(ADDON_LINE_COUNT-1 downto 0) := (others => '0');
-- External trigger logic
EXT_TRIGGER_IN : in std_logic;
);
end component;
- component mainz_a2_recv is
- port (
- CLK : in std_logic;
- RESET_IN : in std_logic;
- TIMER_TICK_1US_IN : in std_logic;
- SERIAL_IN : in std_logic;
- EXT_TRG_IN : in std_logic;
- TRG_SYNC_OUT : out std_logic;
- TRIGGER_IN : in std_logic;
- DATA_OUT : out std_logic_vector(31 downto 0);
- WRITE_OUT : out std_logic;
- STATUSBIT_OUT : out std_logic_vector(31 downto 0);
- FINISHED_OUT : out std_logic;
- CONTROL_REG_IN : in std_logic_vector(31 downto 0);
- STATUS_REG_OUT : out std_logic_vector(31 downto 0) := (others => '0');
- HEADER_REG_OUT : out std_logic_vector(1 downto 0);
- DEBUG : out std_logic_vector(31 downto 0));
- end component mainz_a2_recv;
-
+ component mainz_a2_recv is
+ port (
+ CLK : in std_logic;
+ RESET_IN : in std_logic;
+ TIMER_TICK_1US_IN : in std_logic;
+ SERIAL_IN : in std_logic;
+ EXT_TRG_IN : in std_logic;
+ TRG_SYNC_OUT : out std_logic;
+ TRIGGER_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(31 downto 0);
+ WRITE_OUT : out std_logic;
+ STATUSBIT_OUT : out std_logic_vector(31 downto 0);
+ FINISHED_OUT : out std_logic;
+ CONTROL_REG_IN : in std_logic_vector(31 downto 0);
+ STATUS_REG_OUT : out std_logic_vector(31 downto 0) := (others => '0');
+ HEADER_REG_OUT : out std_logic_vector(1 downto 0);
+ DEBUG : out std_logic_vector(31 downto 0));
+ end component mainz_a2_recv;
+
component CTS_TRIGGER is
generic (
TRIGGER_INPUT_COUNT : integer range 1 to 8 := 4;
TRIGGER_COIN_COUNT : integer range 0 to 15 := 4;
TRIGGER_PULSER_COUNT : integer range 0 to 15 := 2;
TRIGGER_RAND_PULSER : integer range 0 to 15 := 1;
+
+ ADDON_LINE_COUNT : integer range 0 to 255 := 22; -- number of lines available from add-on board
+ TRIGGER_ADDON_COUNT : integer range 0 to 15 := 2; -- number of module instances used to patch through those lines
+
EXTERNAL_TRIGGER_ID : std_logic_vector(7 downto 0) := X"00"
);
-- Input pins
TRIGGERS_IN : in std_logic_vector(TRIGGER_INPUT_COUNT - 1 downto 0);
+ ADDON_TRIGGERS_IN : in std_logic_vector(ADDON_LINE_COUNT-1 downto 0) := (others => '0');
-- External
EXT_TRIGGER_IN : in std_logic;
trigger_out : out std_logic
);
end component;
-
-- Block identification header
-- Bit Description
TRIGGER_COIN_COUNT : integer range 0 to 15 := 4;
TRIGGER_PULSER_COUNT : integer range 0 to 15 := 2;
TRIGGER_RAND_PULSER : integer range 0 to 15 := 1;
+ TRIGGER_ADDON_COUNT : integer range 0 to 15 := 2;
+
+ ADDON_LINE_COUNT : integer range 0 to 255 := 22;
+
EXTERNAL_TRIGGER_ID : std_logic_vector(7 downto 0) := X"00"
);
RESET_IN : in std_logic;
-- Trigger Inputs
- TRIGGERS_IN : in std_logic_vector(TRIGGER_INPUT_COUNT - 1 downto 0);
+ TRIGGERS_IN : in std_logic_vector(TRIGGER_INPUT_COUNT-1 downto 0);
+ ADDON_TRIGGERS_IN : in std_logic_vector(ADDON_LINE_COUNT-1 downto 0) := (others => '0');
-- External
EXT_TRIGGER_IN : in std_logic;
TRIGGER_BITMASK_OUT : out std_logic_vector(15 downto 0);
-- Counters
- INPUT_COUNTERS_OUT : out std_logic_vector(32 * TRIGGER_INPUT_COUNT - 1 downto 0) := (others => '0');
- INPUT_EDGE_COUNTERS_OUT : out std_logic_vector(32 * TRIGGER_INPUT_COUNT - 1 downto 0) := (others => '0');
+ INPUT_COUNTERS_OUT : out std_logic_vector(32 * (TRIGGER_INPUT_COUNT + TRIGGER_ADDON_COUNT) - 1 downto 0) := (others => '0');
+ INPUT_EDGE_COUNTERS_OUT : out std_logic_vector(32 * (TRIGGER_INPUT_COUNT + TRIGGER_ADDON_COUNT) - 1 downto 0) := (others => '0');
CHANNEL_COUNTERS_OUT : out std_logic_vector(32 * 16 - 1 downto 0) := (others => '0');
CHANNEL_EDGE_COUNTERS_OUT : out std_logic_vector(32 * 16 - 1 downto 0) := (others => '0');
NUM_OF_ITC_USED_OUT : out std_logic_vector(4 downto 0);
signal channels_i : std_logic_vector(15 downto 0) := (others => '0');
signal channel_mask_i : std_logic_vector(15 downto 0);
signal channel_edge_select_i : std_logic_vector(15 downto 0);
+
+ -- internal trigger lines (i.e. all signals that are piped through the trigger input modules)
+ constant ITL_NUM : integer := TRIGGER_INPUT_COUNT + TRIGGER_ADDON_COUNT;
constant ITC_NUM_EXT_BUF : unsigned(0 downto 0) := (others => or_all(EXTERNAL_TRIGGER_ID)); -- oh, that's dirty, but dont know a better solution (but define a func)
constant ITC_NUM_EXT : integer := to_integer( ITC_NUM_EXT_BUF ) ;
- constant ITC_BASE_EXT : integer := 0;
+ constant ITC_BASE_EXT : integer := 0;
constant ITC_BASE_PULSER : integer := ITC_BASE_EXT + ITC_NUM_EXT;
constant ITC_BASE_RAND_PULSER : integer := ITC_BASE_PULSER + TRIGGER_PULSER_COUNT;
constant ITC_BASE_INPUTS : integer := ITC_BASE_RAND_PULSER + TRIGGER_RAND_PULSER;
- constant ITC_BASE_COINS : integer := ITC_BASE_INPUTS + TRIGGER_INPUT_COUNT;
+ constant ITC_BASE_COINS : integer := ITC_BASE_INPUTS + ITL_NUM;
- constant ITC_NUM_USED : integer := ITC_BASE_COINS + TRIGGER_COIN_COUNT;
+ constant ITC_NUM_USED : integer := ITC_BASE_COINS + TRIGGER_COIN_COUNT;
- alias trigger_inputs_i : std_logic_vector(TRIGGER_INPUT_COUNT - 1 downto 0)
- is channels_i(ITC_BASE_INPUTS + TRIGGER_INPUT_COUNT - 1 downto ITC_BASE_INPUTS);
+ alias trigger_inputs_i : std_logic_vector(ITL_NUM - 1 downto 0)
+ is channels_i(ITC_BASE_INPUTS + ITL_NUM - 1 downto ITC_BASE_INPUTS);
alias coins_i : std_logic_vector(TRIGGER_COIN_COUNT - 1 downto 0)
is channels_i(ITC_BASE_COINS + TRIGGER_COIN_COUNT - 1 downto ITC_BASE_COINS);
signal channel_edge_counters_i : channel_counters_t;
-- Trigger Inputs (Spike Rejection, Negation, Override ...)
- signal triggers_i : std_logic_vector(TRIGGERS_IN'RANGE);
+ signal triggers_i : std_logic_vector(ITL_NUM - 1 downto 0);
- type trigger_input_configs_t is array(TRIGGER_INPUT_COUNT - 1 downto 0) of std_logic_vector(10 downto 0);
+ type trigger_input_configs_t is array(ITL_NUM - 1 downto 0) of std_logic_vector(10 downto 0);
signal trigger_input_configs_i : trigger_input_configs_t;
- type trigger_input_counters_t is array(TRIGGER_INPUT_COUNT - 1 downto 0) of unsigned(31 downto 0);
+ type trigger_input_counters_t is array(ITL_NUM - 1 downto 0) of unsigned(31 downto 0);
signal trigger_input_counters_i : trigger_input_counters_t;
signal trigger_input_edge_counters_i : trigger_input_counters_t;
type rand_pulser_threshold_t is array(TRIGGER_RAND_PULSER - 1 downto 0) of std_logic_vector(31 downto 0);
signal rand_pulser_threshold_i : rand_pulser_threshold_t := (others => (others => '0'));
+-- Add On
+ type trigger_addon_configs_t is array(TRIGGER_ADDON_COUNT - 1 downto 0) of std_logic_vector(7 downto 0);
+ signal trigger_addon_configs_i : trigger_addon_configs_t;
+
-- Trigger Type Assoc
type trigger_type_assoc_t is array(0 to 15) of std_logic_vector(3 downto 0);
signal trigger_type_assoc_i : trigger_type_assoc_t := (others => X"1");
proc_input_ffs: process(CLK_IN) is
begin
if rising_edge(CLK_IN) then
- triggers_i <= TRIGGERS_IN;
+ triggers_i(TRIGGER_INPUT_COUNT-1 downto 0) <= TRIGGERS_IN;
+ end if;
+ end process;
+
+ proc_addon_multi: process(CLK_IN) is
+ begin
+ if rising_edge(CLK_IN) then
+ for i in 0 to TRIGGER_ADDON_COUNT - 1 loop
+ triggers_i(TRIGGER_INPUT_COUNT + i)
+ <= ADDON_TRIGGERS_IN( to_integer( UNSIGNED(trigger_addon_configs_i(i)) ) );
+ end loop;
end if;
end process;
channels_i(ITC_BASE_EXT) <= EXT_TRIGGER_IN;
end generate;
- gen_trigger_inputs: for i in 0 to TRIGGER_INPUT_COUNT-1 generate
+ gen_trigger_inputs: for i in 0 to ITL_NUM-1 generate
my_trigger_input: CTS_TRG_INPUT port map (
CLK_IN => CLK_IN,
RST_IN => RESET_IN,
CONFIG_IN => trigger_input_configs_i(i)
);
end generate;
-
+
gen_coin: for i in 0 to TRIGGER_COIN_COUNT - 1 generate
my_coin: CTS_TRG_COIN
generic map (
- INPUT_COUNT => TRIGGER_INPUT_COUNT
+ INPUT_COUNT => ITL_NUM
)
port map (
CLK_IN => CLK_IN,
end if;
end process;
--- Common
+-- Common
proc_output: process(CLK_IN) is
variable channels_delay_v : std_logic_vector(15 downto 0) := (others => '1');
begin
channel_edge_counters_i <= (others => (others => '0'));
else
- for i in 0 to TRIGGER_INPUT_COUNT-1 loop
+ for i in 0 to ITL_NUM-1 loop
if triggers_i(i) = '1' then
trigger_input_counters_i(i) <= trigger_input_counters_i(i) + "1";
end if;
end process;
- gen_input_counter: for i in 0 to TRIGGER_INPUT_COUNT-1 generate
+ gen_input_counter: for i in 0 to ITL_NUM-1 generate
INPUT_COUNTERS_OUT(i*32 + 31 downto i*32) <= trigger_input_counters_i(i);
INPUT_EDGE_COUNTERS_OUT(i*32 + 31 downto i*32) <= trigger_input_edge_counters_i(i);
end generate;
REGIO_DATAREADY_OUT <= REGIO_READ_ENABLE_IN;
REGIO_DATA_OUT <= CTS_BLOCK_HEADER(
id => 16#10#,
- len => TRIGGER_INPUT_COUNT,
+ len => ITL_NUM,
itc_base => ITC_BASE_INPUTS,
- itc_num => TRIGGER_INPUT_COUNT
+ itc_num => ITL_NUM
);
end if;
ref_addr := ref_addr + 1;
-- INPUT CONFIGURATION
- for i in 0 to TRIGGER_INPUT_COUNT - 1 loop
+ for i in 0 to ITL_NUM - 1 loop
if addr = ref_addr then
REGIO_UNKNOWN_ADDR_OUT <= '0';
REGIO_DATAREADY_OUT <= REGIO_READ_ENABLE_IN;
if addr = ref_addr then
REGIO_UNKNOWN_ADDR_OUT <= '0';
REGIO_DATAREADY_OUT <= REGIO_READ_ENABLE_IN;
- REGIO_DATA_OUT <= CTS_BLOCK_HEADER(id => 16#11#, len => 2*TRIGGER_INPUT_COUNT);
+ REGIO_DATA_OUT <= CTS_BLOCK_HEADER(id => 16#11#, len => 2*ITL_NUM);
end if;
ref_addr := ref_addr + 1;
- for i in 0 to TRIGGER_INPUT_COUNT - 1 loop
+ for i in 0 to ITL_NUM - 1 loop
if addr = ref_addr then
REGIO_UNKNOWN_ADDR_OUT <= '0';
REGIO_DATAREADY_OUT <= REGIO_READ_ENABLE_IN;
end loop;
end if;
+
+-- ADDON MULTIPLEXER
+ if TRIGGER_ADDON_COUNT > 0 then
+ if addr = ref_addr then
+ REGIO_UNKNOWN_ADDR_OUT <= '0';
+ REGIO_DATAREADY_OUT <= REGIO_READ_ENABLE_IN;
+ REGIO_DATA_OUT <= CTS_BLOCK_HEADER(
+ id => 16#12#,
+ len => TRIGGER_ADDON_COUNT,
+ itc_base => ITC_BASE_INPUTS + TRIGGER_INPUT_COUNT,
+ itc_num => TRIGGER_ADDON_COUNT
+ );
+ end if;
+ ref_addr := ref_addr + 1;
+
+ for i in 0 to TRIGGER_ADDON_COUNT - 1 loop
+ if addr=ref_addr then
+ REGIO_UNKNOWN_ADDR_OUT <= '0';
+ REGIO_DATAREADY_OUT <= REGIO_READ_ENABLE_IN;
+ REGIO_WRITE_ACK_OUT <= REGIO_WRITE_ENABLE_IN;
+
+ REGIO_DATA_OUT <= (others => '0');
+ REGIO_DATA_OUT(trigger_addon_configs_i(i)'RANGE) <= trigger_addon_configs_i(i);
+
+ if REGIO_WRITE_ENABLE_IN = '1' then
+ trigger_addon_configs_i(i) <= REGIO_DATA_IN(trigger_addon_configs_i(i)'RANGE);
+ end if;
+ end if;
+ ref_addr := ref_addr + 1;
+
+ end loop;
+ end if;
-- TRIGGER_PULSER_COUNT CONFIGURATION
if TRIGGER_PULSER_COUNT > 0 then
signal cts_rdo_trg_information : std_logic_vector(23 downto 0);
signal cts_rdo_trg_number : std_logic_vector(15 downto 0);
-
+ constant CTS_ADDON_LINE_COUNT : integer := 14;
+ signal cts_addon_triggers_in : std_logic_vector(CTS_ADDON_LINE_COUNT-1 downto 0);
signal cts_trg_send : std_logic;
signal cts_trg_type : std_logic_vector(3 downto 0);
EXTERNAL_TRIGGER_ID => X"60"+ETM_CHOICE_type'pos(ETM_CHOICE), --, fill in trigger logic enumeration id of external trigger logic
TRIGGER_INPUT_COUNT => 4,
TRIGGER_COIN_COUNT => 4,
- TRIGGER_PULSER_COUNT => 4,
- TRIGGER_RAND_PULSER => 1
+ TRIGGER_PULSER_COUNT => 2,
+ TRIGGER_RAND_PULSER => 1,
+ TRIGGER_ADDON_COUNT => 2,
+ ADDON_LINE_COUNT => CTS_ADDON_LINE_COUNT
)
port map (
CLK => clk_100_i,
RESET => reset_i,
TRIGGERS_IN => trigger_in_buf_i,
+ ADDON_TRIGGERS_IN => cts_addon_triggers_in,
TRIGGER_BUSY_OUT => trigger_busy_i,
TIME_REFERENCE_OUT => cts_trigger_out,
FEE_DATA_FINISHED_OUT => cts_rdo_finished
);
+ process is begin
+ wait until rising_edge(clk_100_i);
+ cts_addon_triggers_in( 3 downto 0) <= ECL_IN;
+ cts_addon_triggers_in( 7 downto 4) <= JIN1;
+ cts_addon_triggers_in(11 downto 8) <= JIN2;
+ cts_addon_triggers_in(13 downto 12) <= NIM_IN;
+ end process;
+
+
+
-- cts_rdo_trg_status_bits <= cts_rdo_trg_status_bits_cts OR cts_rdo_trg_status_bits_additional;
---------------------------------------------------------------------------
wait until rising_edge(clk_200_i);
TRIGGER_OUT <= cts_trigger_out;
TRIGGER_OUT2 <= cts_trigger_out;
+ TRG_FANOUT_ADDON <= cts_trigger_out;
end process;
JOUT2 <= x"0";
JOUTLVDS <= x"00";
JTTL <= x"0000";
- TRG_FANOUT_ADDON <= '0';
LED_BANK <= x"FF";
LED_RJ_GREEN <= "111111";
jspc29 / trb3.git / commitdiff