signal tx_length_data_in : std_logic_vector(7 downto 0) := (others => '0');
signal tx_length_data_out : std_logic_vector(7 downto 0) := (others => '0');
- type copy_state_t is (IDLE, RUNNING, LAST_WORD, BUFFER_FULL_WAIT);
+ type copy_state_t is (IDLE, RUNNING, LAST_WORD, BUFFER_FULL_WAIT, WAIT_ONE);
signal copy_state : copy_state_t;
signal copy_length : unsigned(6 downto 0) := (others => '0');
signal current_address : unsigned(31 downto 0) := (others => '0');
signal buf_API_READ_OUT : std_logic := '0';
- type send_state_t is (SEND_IDLE, SEND_CREDIT_WAIT, SEND_START, SEND_FIRST, SEND_DATA);
+ type send_state_t is (SEND_IDLE, SEND_CREDIT_WAIT, SEND_START, SEND_DATA);
signal send_state : send_state_t;
signal tx_length : unsigned(6 downto 0) := (others => '0');
signal last_words : std_logic := '0';
signal buffer_full_strobe : std_logic;
signal buffer_full : std_logic;
+ signal current_burst_length : unsigned(6 downto 0);
+ signal buffer_space_available : std_logic;
+
begin
-----------------------------------------------------------------------
-- I/O
-----------------------------------------------------------------------
-reset_i <= RESET_IN;
+reset_i <= RESET_IN or DMA_CONTROL_IN(1);
API_READ_OUT <= buf_API_READ_OUT;
+PROC_COPY_DATA : process(CLK_IN)
+ begin
+ if rising_edge(CLK_IN) then
+ buffer_space_available <= '1';
+ current_burst_length <= unsigned(DMA_CONFIG_IN(6 downto 0));
+
+-- if current_address + unsigned(DMA_CONFIG_IN(7 downto 0)) * to_unsigned(4,32)
+-- < unsigned(DMA_START_ADDR_IN) + unsigned(DMA_LENGTH_IN) * to_unsigned(4,32) then
+-- end if;
+ end if;
+ end process;
+
+
PROC_DETECT_START : process(CLK_IN)
begin
if rising_edge(CLK_IN) then
else
tx_wr_en <= '0';
tx_length_wr_en <= '0';
- last_words <= '0';
+ last_words <= not API_RUNNING_IN;
tx_fifo_padding <= x"0";
buffer_full_strobe <= '0';
case copy_state is
total_length <= (others => '0');
current_address <= unsigned(DMA_START_ADDR_IN);
end if;
- if busy = '1' and API_RUNNING_IN = '1' and tx_almost_full = '0' then --DMA enable and API running
+ if busy = '1' and (API_RUNNING_IN = '1' or API_DATAREADY_IN = '1') and tx_almost_full = '0' then --DMA enable and API running
if --Enough space in buffer for one burst
- current_address + unsigned(DMA_CONTROL_IN(7 downto 0)) * to_unsigned(4,32)
+ current_address + unsigned(DMA_CONFIG_IN(7 downto 0)) * to_unsigned(4,32)
< unsigned(DMA_START_ADDR_IN) + unsigned(DMA_LENGTH_IN) * to_unsigned(4,32) then
tx_data_in( 7 downto 0) <= std_logic_vector(current_address(31 downto 24));
tx_data_in(15 downto 8) <= std_logic_vector(current_address(23 downto 16));
-- if copy_length = unsigned(DMA_CONFIG_IN(6 downto 0)) - to_unsigned(1,1) then
-- buf_API_READ_OUT <= '0';
-- els
- if copy_length = unsigned(DMA_CONFIG_IN(6 downto 0)) then
+ if copy_length = current_burst_length then
buf_API_READ_OUT <= '0';
- copy_state <= LAST_WORD;
+ copy_state <= WAIT_ONE;
end if;
end if;
if API_RUNNING_IN = '0' then
buf_API_READ_OUT <= '0';
+ copy_state <= WAIT_ONE;
+ end if;
+
+ when WAIT_ONE =>
+ if API_RUNNING_IN = '0' or API_DATAREADY_IN = '1' then
copy_state <= LAST_WORD;
end if;
tx_data_in <= (others => '0');
tx_wr_en <= not copy_length(0); --write padding
tx_fifo_padding <= x"8";
- last_words <= not API_RUNNING_IN;
tx_length_wr_en <= '1';
copy_state <= IDLE;
copy_state_bits <= "11";
if DMA_CONTROL_IN(0) = '1' then
copy_state <= IDLE;
+ total_length <= (others => '0');
+ current_address <= unsigned(DMA_START_ADDR_IN);
end if;
end case;
if tx_length_data_out(6 downto 0) = "0000000" then --no data
finished <= tx_length_data_out(7);
send_state <= SEND_IDLE;
- elsif (TX_CA_PH_IN(8) = '1' or unsigned(TX_CA_PH_IN(7 downto 0)) > to_unsigned(1,8))
- and (TX_CA_PD_IN(12) = '1' or unsigned(TX_CA_PD_IN(8 downto 2)) >= unsigned(tx_length_data_out(6 downto 0)))
+ elsif (TX_CA_PH_IN(8) = '1' or (unsigned(TX_CA_PH_IN(7 downto 0)) > to_unsigned(1,8)))
+ and (TX_CA_PD_IN(12) = '1' or (unsigned(TX_CA_PD_IN(8 downto 2)) >= unsigned(tx_length_data_out(6 downto 0))))
then
TX_ST_OUT <= '0';
tx_end_i <= '0';
end if;
end if;
--- when SEND_FIRST =>
--- send_state_bits <= x"3";
--- TX_ST_OUT <= '0';
--- TX_DWEN_OUT <= tx_fifo_data_out(71);
--- buf_TX_DATA_OUT <= tx_fifo_data_out(31 downto 0) & tx_fifo_data_out(67 downto 36);
--- if TX_VAL_IN = '1' then
--- if tx_length > to_unsigned(2,3) then
--- tx_rd_en <= '1';
--- tx_length <= tx_length - to_unsigned(2,3);
--- send_state <= SEND_DATA;
--- elsif tx_length > to_unsigned(1,3) then
--- tx_length <= tx_length - to_unsigned(2,3);
--- send_state <= SEND_DATA;
--- elsif tx_length = to_unsigned(1,3) then
--- finished <= tx_length_data_out(7);
--- tx_length <= tx_length - to_unsigned(1,3);
--- send_state <= SEND_DATA;
--- else
--- tx_end_i <= '1';
--- finished <= tx_length_data_out(7);
--- send_state <= SEND_IDLE;
--- end if;
--- end if;
-
when SEND_DATA =>
send_state_bits <= x"7";
TX_ST_OUT <= '0';
send_state <= SEND_IDLE;
end if;
end if;
---
--- if TX_VAL_IN = '1' and tx_length > to_unsigned(2,3) then
--- tx_rd_en <= '1';
--- end if;
---
--- if TX_VAL_IN = '1' and tx_length > to_unsigned(1,3) then
--- tx_length <= tx_length - to_unsigned(2,3);
--- elsif TX_VAL_IN = '1' and tx_length = to_unsigned(1,3) then
--- tx_length <= tx_length - to_unsigned(1,3);
--- end if;
---
--- if TX_VAL_IN = '1' and tx_length = to_unsigned(0,7) then
--- tx_end_i <= '1';
--- finished <= tx_length_data_out(7);
--- send_state <= SEND_IDLE;
--- else
--- tx_end_i <= '0';
--- end if;
-
-
end case;
THE_finished_strobe_SYNC : pulse_sync
port map(
CLK_A_IN => CLK_125_IN,
- RESET_A_IN => RESET_IN,
+ RESET_A_IN => reset_i,
PULSE_A_IN => finished,
CLK_B_IN => CLK_IN,
- RESET_B_IN => RESET_IN,
+ RESET_B_IN => reset_i,
PULSE_B_OUT => finished_sys
);
PROC_BUSY : process(CLK_IN)
begin
if rising_edge(CLK_IN) then
- if RESET_IN = '1' then
+ if reset_i = '1' then
busy <= '0';
elsif DMA_CONTROL_IN(0) = '1' then
busy <= '1';
PROC_BUFFER_FULL : process(CLK_IN)
begin
if rising_edge(CLK_IN) then
- if RESET_IN = '1' or DMA_CONTROL_IN(0) = '1' then
+ if reset_i = '1' or DMA_CONTROL_IN(0) = '1' then
buffer_full <= '0';
elsif buffer_full_strobe = '1' then
buffer_full <= '1';
STATUS_REG_OUT(62 downto 54) <= TX_CA_NPH_IN;
STATUS_REG_OUT(63) <= '0';
-STATUS_REG_OUT(95 downto 64) <= x"00000000";
+STATUS_REG_OUT(95 downto 64) <= x"000" & tx_length_data_in & "00" & tx_length_rd_en & tx_rd_en & tx_length_data_out;
STATUS_REG_OUT(127 downto 96)<= std_logic_vector(current_address);
DEBUG_OUT(7) <= tx_length_data_out(7);
DEBUG_OUT(8) <= tx_req_i;
DEBUG_OUT(9) <= TX_RDY_IN;
- DEBUG_OUT(10)<= TX_VAL_IN;
+ DEBUG_OUT(10)<= tx_length_data_out(7);
DEBUG_OUT(11)<= tx_end_i;
DEBUG_OUT(13 downto 12) <= copy_state_bits;
DEBUG_OUT(15 downto 14) <= send_state_bits(1 downto 0);
-- end if;
-- end if;
-- end process;
+
+
+
+-- when SEND_FIRST =>
+-- send_state_bits <= x"3";
+-- TX_ST_OUT <= '0';
+-- TX_DWEN_OUT <= tx_fifo_data_out(71);
+-- buf_TX_DATA_OUT <= tx_fifo_data_out(31 downto 0) & tx_fifo_data_out(67 downto 36);
+-- if TX_VAL_IN = '1' then
+-- if tx_length > to_unsigned(2,3) then
+-- tx_rd_en <= '1';
+-- tx_length <= tx_length - to_unsigned(2,3);
+-- send_state <= SEND_DATA;
+-- elsif tx_length > to_unsigned(1,3) then
+-- tx_length <= tx_length - to_unsigned(2,3);
+-- send_state <= SEND_DATA;
+-- elsif tx_length = to_unsigned(1,3) then
+-- finished <= tx_length_data_out(7);
+-- tx_length <= tx_length - to_unsigned(1,3);
+-- send_state <= SEND_DATA;
+-- else
+-- tx_end_i <= '1';
+-- finished <= tx_length_data_out(7);
+-- send_state <= SEND_IDLE;
+-- end if;
+-- end if;
+
+
+--
+-- if TX_VAL_IN = '1' and tx_length > to_unsigned(2,3) then
+-- tx_rd_en <= '1';
+-- end if;
+--
+-- if TX_VAL_IN = '1' and tx_length > to_unsigned(1,3) then
+-- tx_length <= tx_length - to_unsigned(2,3);
+-- elsif TX_VAL_IN = '1' and tx_length = to_unsigned(1,3) then
+-- tx_length <= tx_length - to_unsigned(1,3);
+-- end if;
+--
+-- if TX_VAL_IN = '1' and tx_length = to_unsigned(0,7) then
+-- tx_end_i <= '1';
+-- finished <= tx_length_data_out(7);
+-- send_state <= SEND_IDLE;
+-- else
+-- tx_end_i <= '0';
+-- end if;
jspc29 / pexor.git / commitdiff