DAT_UNKNOWN_ADDR_OUT => BUS_TX.unknown,
--Bus Handler (SPI CTRL)
+ --Bus Handler (SPI Memory)
BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
+ BUS_READ_ENABLE_OUT(1) => spimem_read_en,
BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
+ BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
BUS_ADDR_OUT(0*16) => spictrl_addr,
BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
- BUS_TIMEOUT_OUT(0) => open,
- BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
- BUS_DATAREADY_IN(0) => spictrl_ack,
- BUS_WRITE_ACK_IN(0) => spictrl_ack,
- BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
- BUS_UNKNOWN_ADDR_IN(0) => '0',
-
- --Bus Handler (SPI Memory)
- BUS_READ_ENABLE_OUT(1) => spimem_read_en,
- BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
- BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
+ BUS_TIMEOUT_OUT(0) => open,
BUS_TIMEOUT_OUT(1) => open,
+ BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
+ BUS_DATAREADY_IN(0) => spictrl_ack,
BUS_DATAREADY_IN(1) => spimem_ack,
+ BUS_WRITE_ACK_IN(0) => spictrl_ack,
BUS_WRITE_ACK_IN(1) => spimem_ack,
+ BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(0) => '0',
BUS_UNKNOWN_ADDR_IN(1) => '0',
+
STAT_DEBUG => open
);
);
-end architecture;
\ No newline at end of file
+end architecture;