*** empty log message ***

diff --git a/testbench/trb_net16_dummy_apl.vhd b/testbench/trb_net16_dummy_apl.vhd
index e205274e904e29a67bee5837956a2a25b5f52290..1a9cead465920453a20396c449866e66c639b4f7 100644 (file)
--- a/testbench/trb_net16_dummy_apl.vhd
+++ b/testbench/trb_net16_dummy_apl.vhd
@@ -59,15 +59,18 @@ architecture trb_net16_dummy_apl_arch of trb_net16_dummy_apl is
   signal next_packet_counter, packet_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
   signal address, reghigh, reglow : std_logic_vector(15 downto 0);
   signal state_bits : std_logic_vector(2 downto 0);
+  signal reg_F0, reg_F1, reg_F2, reg_F3 : std_logic_vector(15 downto 0);
 begin
 
 --   address <= x"0008";
 --   reghigh <= x"DEAD";
 --   reglow  <= x"AFFE";
-  address <= x"10AB"; --x"0001";
-  reghigh <= x"0022";
-  reglow  <= xor_all(APL_DATA_IN) & "000000000000011";
-  APL_DTYPE_OUT <= x"A";
+  reg_F0 <= x"5EAD"; --x"0001";
+
+  reg_F1 <= x"0001";
+  reg_F2 <= x"F00E";--xor_all(APL_DATA_IN) & "000000000000011";
+  reg_F3 <= x"2222";
+  APL_DTYPE_OUT <= x"F";
   APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS;
 
   process(current_state)
@@ -112,7 +115,7 @@ begin
           next_state <=  IDLE;
         else
           next_state <=  WRITING;
-          next_APL_DATA_OUT <= address;
+          next_APL_DATA_OUT <= reg_F0;
           next_APL_WRITE_OUT <=  '1';
           next_packet_counter <= c_F0;
           next_APL_SEND_OUT <=  '1';
@@ -125,15 +128,15 @@ begin
         next_state <= WRITING;
         if packet_counter = c_F0 then
           next_APL_WRITE_OUT <=  '1';
-          next_APL_DATA_OUT <= reghigh;
+          next_APL_DATA_OUT <= reg_F1;
           next_packet_counter <= c_F1;
         elsif packet_counter = c_F1 then
           next_APL_WRITE_OUT <=  '1';
-          next_APL_DATA_OUT <= reglow;
+          next_APL_DATA_OUT <= reg_F2;
           next_packet_counter <= c_F2;
         elsif packet_counter = c_F2 then
           next_APL_WRITE_OUT <=  '1';
-          next_APL_DATA_OUT <= (2 => '1', others => '0');
+          next_APL_DATA_OUT <= reg_F3;
           next_packet_counter <= c_F3;
         elsif packet_counter = c_F3 then
           next_state <= IDLE;

diff --git a/trb_net16_addresses.vhd b/trb_net16_addresses.vhd
index bc239501c8eb97ad36ee921e7413096aa9f4726f..675d0b7a094068226f1760e65d6746eb36f859b8 100644 (file)
--- a/trb_net16_addresses.vhd
+++ b/trb_net16_addresses.vhd
@@ -96,12 +96,13 @@ begin
           buf_ADDRESS_OUT <= INIT_ADDRESS;
           ram_read_addr1 <= (others => '0');
           matching_counter <= (others => '0');
+          recv_set_address <= '0';
           sending_state <= sending_idle;
         elsif CLK_EN = '1' then
           buf_API_READ_OUT <= '1';
           ADDRESS_REJECTED <= '0';
           read_UNIQUE_ID <= '0';
-          recv_set_address    <= '0';
+          --recv_set_address    <= '0';
 
           --control sending state
           if buf_API_SEND_OUT = '0' then
@@ -132,7 +133,7 @@ begin
                 matching_counter <= "000";
                 ram_read_addr1   <= "0000";
                 recv_set_address <= '0';
-                if matching_counter = "100" then
+                if matching_counter = "101" then
                   buf_ADDRESS_OUT   <= API_DATA_IN;
                   sending_state <= send_ack_address;
                 else

diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd
index efef63b9ad06f16767dcaa201d2064e7d25bbf7e..5ce3a6ca022ab35c8e864dcb9b7d1d06f3b3008c 100644 (file)
--- a/trb_net16_hub_logic.vhd
+++ b/trb_net16_hub_logic.vhd
@@ -119,8 +119,10 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is
   signal REPLY_reading_trm                     : std_logic_vector(POINT_NUMBER-1  downto 0);
   signal next_REPLY_reading_trm                : std_logic_vector(POINT_NUMBER-1  downto 0);
   signal current_REPLY_reading_trm             : std_logic_vector(POINT_NUMBER-1  downto 0);
-  signal reading_trmF0, reading_trmF1, reading_trmF2 : std_logic_vector(POINT_NUMBER-1  downto 0);
-  signal REPLY_combined_trm_F0,REPLY_combined_trm_F1, REPLY_combined_trm_F2 : std_logic_vector(c_DATA_WIDTH-1  downto 0);
+  signal reading_trmF0, reading_trmF1 : std_logic_vector(POINT_NUMBER-1  downto 0);
+  signal reading_trmF2, reading_trmF3 : std_logic_vector(POINT_NUMBER-1  downto 0);
+  signal REPLY_combined_trm_F0, REPLY_combined_trm_F1 : std_logic_vector(c_DATA_WIDTH-1  downto 0);
+  signal REPLY_combined_trm_F2, REPLY_combined_trm_F3 : std_logic_vector(c_DATA_WIDTH-1  downto 0);
   signal REPLY_MUX_real_reading                : std_logic;
   signal real_activepoints                     : std_logic_vector(POINT_NUMBER-1 downto 0);
 
@@ -469,29 +471,35 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2;
                      and REPLY_reading_trm(i) and REPLY_DATAREADY_IN(i);
     reading_trmF2(i) <= REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH)
                      and REPLY_reading_trm(i) and REPLY_DATAREADY_IN(i);
+    reading_trmF3(i) <= REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH)
+                     and REPLY_reading_trm(i) and REPLY_DATAREADY_IN(i);
   end generate;
 
   gen_combining_trm : for j in 0 to c_DATA_WIDTH-1 generate
     process(CLK)
-      variable tmpF1, tmpF2, tmpF0 : std_logic;
+      variable tmpF1, tmpF2, tmpF3, tmpF0 : std_logic;
       begin
         if rising_edge(CLK) then
           if RESET = '1' or locked = '0' then
             REPLY_combined_trm_F0(j) <= '0';
             REPLY_combined_trm_F1(j) <= '0';
             REPLY_combined_trm_F2(j) <= '0';
+            REPLY_combined_trm_F3(j) <= '0';
           else
             tmpF0 := '0';
             tmpF1 := '0';
             tmpF2 := '0';
+            tmpF3 := '0';
             for i in 0 to POINT_NUMBER-1 loop
               tmpF0 := tmpF0 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reading_trmF0(i));
               tmpF1 := tmpF1 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reading_trmF1(i));
               tmpF2 := tmpF2 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reading_trmF2(i));
+              tmpF3 := tmpF3 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reading_trmF3(i));
             end loop;
             REPLY_combined_trm_F0(j) <= REPLY_combined_trm_F0(j) or tmpF0;
             REPLY_combined_trm_F1(j) <= REPLY_combined_trm_F1(j) or tmpF1;
             REPLY_combined_trm_F2(j) <= REPLY_combined_trm_F2(j) or tmpF2;
+            REPLY_combined_trm_F3(j) <= REPLY_combined_trm_F3(j) or tmpF3;
           end if;
         end if;
       end process;
@@ -735,11 +743,11 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2;
           when c_F2 =>
             comb_REPLY_POOL_DATA <= REPLY_combined_trm_F2;
           when c_F3 =>
-            comb_REPLY_POOL_DATA <= "0000" & SEQ_NR & "0000";
+            comb_REPLY_POOL_DATA <= REPLY_combined_trm_F3;
             if REPLY_POOL_next_read = '1' and (init_locked = '1') then
               release_locked <= '1';  --release only when init has finished too
               next_state <= SENDING_DATA;
-            elsif init_locked = '0' then
+            elsif REPLY_POOL_next_read = '1' and init_locked = '0' then
               next_waiting_for_init_finish <= '1';
             end if;
           when others =>