Update compile settings to defaults from Diamond

diff --git a/combiner/config_compile_frankfurt.pl b/combiner/config_compile_frankfurt.pl
index 383cf489858a12dbb474f5d22f43ce623178ba1b..c92c5010ee6127926df0c0754e9f3bebc274b8ec 100644 (file)
--- a/combiner/config_compile_frankfurt.pl
+++ b/combiner/config_compile_frankfurt.pl
@@ -1,11 +1,11 @@
 TOPNAME                      => "combiner",
 lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@jspc29",
-lattice_path                 => '/d/jspc29/lattice/diamond/3.8_x64',
+lattice_path                 => '/d/jspc29/lattice/diamond/3.9_x64',
 synplify_path                => '/d/jspc29/lattice/synplify/K-2015.09/',
 # synplify_command             => "/d/jspc29/lattice/diamond/3.7_x64/bin/lin64/synpwrap -fg -options",
 #synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
-synplify_command             => "ssh -p 52238 jmichel\@cerberus \"cd /home/jmichel/git/dirich/combiner/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/L-2016.09-1/bin/synplify_premier_dp -batch ../combiner.prj\" #",
+#synplify_command             => "ssh -p 52238 jmichel\@cerberus \"cd /home/jmichel/git/dirich/combiner/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/L-2016.09-1/bin/synplify_premier_dp -batch ../combiner.prj\" #",
 nodelist_file                => 'nodelist_frankfurt.txt',
 
 

diff --git a/dirich/config_compile_frankfurt.pl b/dirich/config_compile_frankfurt.pl
index b440f7fe8bf2250dde32064f5a31a29a7aedfdc3..600380b417a77c3892a367f007bea4366bc7fc51 100644 (file)
--- a/dirich/config_compile_frankfurt.pl
+++ b/dirich/config_compile_frankfurt.pl
@@ -8,7 +8,8 @@ TOPNAME                      => "dirich",
 lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@jspc29",
 lattice_path                 => '/d/jspc29/lattice/diamond/3.9_x64',
-synplify_path                => '/d/jspc29/lattice/synplify/L-2016.09-1/',
+synplify_path                => '/d/jspc29/lattice/synplify/K-2015.09/',
+#synplify_path                => '/d/jspc29/lattice/synplify/L-2016.09-1/',
 # synplify_command             => "/d/jspc29/lattice/diamond/3.7_x64/bin/lin64/synpwrap -fg -options",
 # synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
 # synplify_command             => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #",

diff --git a/dirich/diamond/dirich.ldf b/dirich/diamond/dirich.ldf
index f98bc48ab54fef0172a3fb00983f4216dc4b9574..f3c8efb1450705ad8fc601b6c9e5384ae0c981da 100644 (file)
--- a/dirich/diamond/dirich.ldf
+++ b/dirich/diamond/dirich.ldf
@@ -2,7 +2,7 @@
 <BaliProject version="3.2" title="d" device="LFE5UM-85F-8BG381C" default_implementation="p">
     <Options/>
     <Implementation title="p" dir="project" description="project" synthesis="synplify" default_strategy="Strategy1">
-        <Options def_top="f_divider" top="dirich"/>
+        <Options def_top="fifo_18x8k_oreg" top="dirich"/>
         <Source name="../workdir/version.vhd" type="VHDL" type_short="VHDL">
             <Options lib="work"/>
         </Source>

diff --git a/dirich/diamond/dirich1.sty b/dirich/diamond/dirich1.sty
index 02f8941e004777dc052e04bab92838a458fbe853..d01cd92e51058616d4c4005b0806f7dc1debf63e 100644 (file)
--- a/dirich/diamond/dirich1.sty
+++ b/dirich/diamond/dirich1.sty
@@ -189,6 +189,7 @@
     <Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
     <Property name="PROP_SYN_UseLPF" value="True" time="0"/>
     <Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
+    <Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
     <Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
     <Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
     <Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
@@ -196,6 +197,7 @@
     <Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
     <Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
     <Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
+    <Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
     <Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
     <Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
 </Strategy>

diff --git a/dirich/dirich.prj b/dirich/dirich.prj
index 5035fd1a56f7eb32e747cf16c16859ea3e0be1d8..09416613a6fa332fdafff4f5bedede1bcaa7e617 100644 (file)
--- a/dirich/dirich.prj
+++ b/dirich/dirich.prj
@@ -10,42 +10,41 @@ set_option -speed_grade -8
 set_option -part_companion ""
 
 # compilation/mapping options
-set_option -default_enum_encoding sequential
-set_option -symbolic_fsm_compiler 1
 set_option -top_module "dirich"
-set_option -resource_sharing false
-
-# map options
-set_option -frequency 120
-set_option -fanout_limit 100
-set_option -disable_io_insertion 0
-set_option -retiming 1
-set_option -pipe 1
-set_option -forcegsr false
-set_option -fixgatedclocks 3
-set_option -fixgeneratedclocks 3
-set_option -compiler_compatible true
-set_option -multi_file_compilation_unit 1
-
-set_option -max_parallel_jobs 3
-#set_option -automatic_compile_point 1
-#set_option -continue_on_error 1
-set_option -resolve_multiple_driver 1
-
-# simulation options
-set_option -write_verilog 0
-set_option -write_vhdl 1
-
-# automatic place and route (vendor) options
-set_option -write_apr_constraint 0
-
 # set result format/file last
 project -result_format "edif"
 project -result_file "workdir/dirich.edf"
-set_option log_file "workdir/dirich_project.srf" 
-#implementation attributes
 
+
+#compilation/mapping options
+set_option -symbolic_fsm_compiler true
+set_option -resource_sharing true
+
+#use verilog 2001 standard option
 set_option -vlog_std v2001
+
+#map options
+set_option -frequency auto
+set_option -maxfan 1000
+set_option -auto_constrain_io 0
+set_option -disable_io_insertion false
+set_option -retiming false; 
+set_option -pipe true
+set_option -force_gsr false
+set_option -compiler_compatible 0
+set_option -dup false
+
+set_option -default_enum_encoding default
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#synplifyPro options
+set_option -fix_gated_and_generated_clocks 1
+set_option -update_models_cp 0
+set_option -resolve_multiple_driver 0
+
+
 set_option -project_relative_includes 1
 impl -active "workdir"
 
@@ -206,7 +205,7 @@ add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
 add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
 add_file -vhdl -lib work "tdc_release/up_counter.vhd"
 
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd"
+#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd"

diff --git a/dirich/par.p2t b/dirich/par.p2t
index 37870ba9559af2c429a33ef6644faf31f22b81f7..2491d2dbc77713755eb4e2d018c2b161a7a8cec7 100644 (file)
--- a/dirich/par.p2t
+++ b/dirich/par.p2t
@@ -1,16 +1,19 @@
 -w
--y
+#-y
 -l 5
 #-m nodelist.txt       # Controlled by the compile.pl script.
 #-n 1                          # Controlled by the compile.pl script.
--s 12
+-s 1
 -t 1
--c 1
--e 2
--i 15
--exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
-
+-c 0
+-e 0
+-i 6
+-exp parCDP=auto:parCDR=1:parPathBased=OFF:paruseNBR=1
 
+#-exp parPlcInLimit=0
+#-exp parPlcInNeighborSize=1
+#-exp parHold=ON
+#-exp parHoldLimit=10000
 #General PAR Command Line Options
 #  -w    With this option, any files generated will overwrite existing files
 #        (e.g., any .par, .pad files).
@@ -67,3 +70,4 @@
 #                    parHold. 
 #  parPlcInLimit              Cannot find in the online help
 #  parPlcInNeighborSize        Cannot find in the online help
+