update tools: disabling SPI interface, reduce counter sizes

diff --git a/.gitignore b/.gitignore
index 99a485fd334c42721ce7db0366ef8559740b2db0..fdfab64efc17275ab7619fe0d782d17c9846319a 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -33,3 +33,4 @@ licbug.txt
 old
 config_compile.pl
 ._Real_._Math_.vhd
+_math_real*

diff --git a/code/load_settings.vhd b/code/load_settings.vhd
index 3f206afd5c93125d79683a60e8091da23563752d..adc673fce0e51749e9d7b374705f03b8368655b1 100644 (file)
--- a/code/load_settings.vhd
+++ b/code/load_settings.vhd
@@ -135,14 +135,14 @@ signal parse_counter : integer range 0 to 255;
 
 signal parse_feedback : std_logic_vector(31 downto 0) := (others=>'0');
 
-signal registers_to_read : std_logic_vector(31 downto 0);
-signal     pages_to_read : std_logic_vector(31 downto 0);
+signal registers_to_read : std_logic_vector(15 downto 0);
+signal     pages_to_read : std_logic_vector(15 downto 0);
 
 signal current_sc_addr  : std_logic_vector(15 downto 0);
 signal current_sc_value : std_logic_vector(31 downto 0);
 
 signal sc_ack_timeout   : integer range 0 to 31;
-signal sc_write_errors  : std_logic_vector(31 downto 0) := (others =>'0');
+signal sc_write_errors  : std_logic_vector(15 downto 0) := (others =>'0');
 
 
 
@@ -464,7 +464,7 @@ PARSE : process begin
       parse_state <= WAIT4RAM;
     
     when STORE_NO_REGISTERS =>
-      registers_to_read <= pop_page_data_word;
+      registers_to_read <= pop_page_data_word(15 downto 0);
       parse_state <= GET_NO_PAGES;
     
     when GET_NO_PAGES =>
@@ -474,7 +474,7 @@ PARSE : process begin
       parse_state <= WAIT4RAM;
       
     when STORE_NO_PAGES =>
-      pages_to_read <= pop_page_data_word;
+      pages_to_read <= pop_page_data_word(15 downto 0);
       parse_state <= READ_NEXT_PAGE;
       
       
@@ -621,7 +621,7 @@ sync : process begin
   
   if( BUS_RX.read = '1') then -- got a read command
     BUS_TX.ack <= '1';
-    BUS_TX.data(15 downto 0) <= (others => '0');
+    BUS_TX.data(31 downto 0) <= (others => '0');
     case BUS_RX.addr(7 downto 0) is
       when ADDR_TAKE_SPI =>
         BUS_TX.data(0) <= take_spi;
@@ -643,7 +643,7 @@ sync : process begin
       when ADDR_FEEDBACK =>
         BUS_TX.data <= parse_feedback;
       when ADDR_SC_WRITE_ERRORS =>
-        BUS_TX.data <= sc_write_errors;
+        BUS_TX.data(15 downto 0) <= sc_write_errors;
       -- DEFAULT --
       when others =>
         BUS_TX.ack <= '0';

diff --git a/code/trb3sc_tools.vhd b/code/trb3sc_tools.vhd
index 386d005b47070b38d70bdcc91d93a056112c45d3..b4d67511a8c5b687ca81ca5093e557b421757d03 100644 (file)
--- a/code/trb3sc_tools.vhd
+++ b/code/trb3sc_tools.vhd
@@ -89,9 +89,12 @@ signal flash_cs_s, flash_clk_s, flash_out_s  : std_logic;
 signal debug_rx, debug_tx : std_logic;
 signal debug_status : std_logic_vector(31 downto 0);
 signal additional_reg_i : std_logic_vector(31 downto 0) := x"00000000";
-signal control_reg_i    : std_logic_vector(15 downto 0);
-signal dtrout           : std_logic_vector(7 downto 0) := x"00"; --temperature in ECP5
+signal control_reg_i    : std_logic_vector(15 downto 0) := x"0000";
+    alias CONF_spi_disable      : std_logic is control_reg_i(14);
+    alias CONF_reboot_on_reset  : std_logic is control_reg_i(15);
 
+signal dtrout           : std_logic_vector(7 downto 0) := x"00"; --temperature in ECP5
+signal sed_reload_i     : std_logic := '0';
 
 attribute syn_black_box: boolean ;
 component dtr
@@ -162,8 +165,8 @@ begin
       BUS_RX               => busflash_rx,
       BUS_TX               => busflash_tx,
       
-      DO_REBOOT_IN         => REBOOT_IN,     
-      REBOOT_ON_RESET      => control_reg_i(15),
+      DO_REBOOT_IN         => REBOOT_IN or sed_reload_i,     
+      REBOOT_ON_RESET      => CONF_reboot_on_reset,
       PROGRAMN             => PROGRAMN,
       PREPARE_FOR_RELOAD   => PREPARE_FOR_RELOAD,
       
@@ -202,9 +205,14 @@ THE_FLASH_REGS : entity work.load_settings
     );      
 
   BUS_MASTER_ACTIVE <= flashset_active or debug_active;
-  FLASH_CS  <= flash_cs_i  when flashset_active = '0' else flash_cs_s;
-  FLASH_CLK <= flash_clk_i when flashset_active = '0' else flash_clk_s;
-  FLASH_OUT <= flash_out_i when flashset_active = '0' else flash_out_s;
+  -- FLASH_CS  <= 'Z' when CONF_spi_disable = '1' else flash_cs_i  when flashset_active = '0' else flash_cs_s;
+  -- FLASH_CLK <= 'Z' when CONF_spi_disable = '1' else flash_clk_i when flashset_active = '0' else flash_clk_s;
+  -- FLASH_OUT <= 'Z' when CONF_spi_disable = '1' else flash_out_i when flashset_active = '0' else flash_out_s;
+
+  FLASH_CS  <= flash_cs_s  when flashset_active = '1' else flash_cs_i;--  when CONF_spi_disable = '0' else 'Z';
+  FLASH_CLK <= flash_clk_s when flashset_active = '1' else flash_clk_i when CONF_spi_disable = '0' else 'Z';
+  FLASH_OUT <= flash_out_s when flashset_active = '1' else flash_out_i; -- when CONF_spi_disable = '0' else 'Z';
+  
   
   bus_flash_tx_in <= BUS_MASTER_IN;
   bus_debug_tx_in <= BUS_MASTER_IN;
@@ -216,21 +224,22 @@ THE_FLASH_REGS : entity work.load_settings
 ---------------------------------------------------------------------------
 -- SED Detection
 ---------------------------------------------------------------------------
-gen_sed : if FPGA_TYPE = 3 generate
+-- gen_sed : if FPGA_TYPE = 3 generate
   THE_SED : entity work.sedcheck
     port map(
       CLK       => CLK,
       ERROR_OUT => SED_ERROR_OUT,
+      RELOAD_OUT => sed_reload_i,
       BUS_RX    => bussed_rx,
       BUS_TX    => bussed_tx,
       DEBUG     => open
       );        
-else generate
-  bussed_tx.unknown <= bussed_rx.write or bussed_rx.read;
-  bussed_tx.ack <= '0'; bussed_tx.nack <= '0';
-  bussed_tx.data <= (others => '0');
-  SED_ERROR_OUT <= '0';
-end generate;
+-- else generate
+--   bussed_tx.unknown <= bussed_rx.write or bussed_rx.read;
+--   bussed_tx.ack <= '0'; bussed_tx.nack <= '0';
+--   bussed_tx.data <= (others => '0');
+--   SED_ERROR_OUT <= '0';
+-- end generate;
 
       
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