updated description of trigger/monitoring module

diff --git a/trb3/CtsHowtos.tex b/trb3/CtsHowtos.tex
index 7386cc657bbf784ea9f7cac39721a08b1a3cf0a3..6dfbae2528d981ef16b49d95c9eb5e1ea7e19652 100644 (file)
--- a/trb3/CtsHowtos.tex
+++ b/trb3/CtsHowtos.tex
@@ -87,7 +87,8 @@ very straight-forward:
       just leave it unconnected - the default values instruct the frontend to send no data. The Read-Out Channel is directly
       connected to a FEE IPU Channel. See the HADES DAQ manual for more information.
 
-      \item \signal{cts\_ext\_control} offers you a 32~bit control register without any restrictions on the mapping.
+      \item \signal{cts\_ext\_control} offers you a 32~bit control register without any restrictions on the mapping. Bit 0 should be
+      used to disable the trigger module, e.g. switch of writing of the data word for read-out.
       It is connected to a synchronous output of the CTS and controlled by the trigger logic. If you need more than 4~byte,
       just connect to the TrbNet regio bus handler (\texttt{THE\_BUS\_HANDLER}).
 

diff --git a/trb3/TriggerModule.tex b/trb3/TriggerModule.tex
index eb8b9f01ce3362d19716c068e87939b335db4911..e19572b88297048f850c4bfa59ad90a7e7d12a93 100644 (file)
--- a/trb3/TriggerModule.tex
+++ b/trb3/TriggerModule.tex
@@ -19,24 +19,27 @@ peripheral FPGAs to one common signal forwarded on the trigger output on the RJ-
 to one of the RJ-45 sockets on the CTS-AddOn.
 
 \paragraph*{SlowControl}
-Configuration of the module can be done in registers 0xcf00 to 0xcf3f. Each output has four 
-configuration registers. The first one contains a bit mask to enable individual inputs. The second 
-one contains a bitmask to invert individual input signals.
-
+Configuration of the module can be done in registers 0xcf00 to 0xcf3f. Each output has two 
+configuration registers. The first one contains a bit mask to enable individual inputs, the second is unused. 
 In case of four outputs configured, registers 0xcf00, 0xcf02, 0xcf04 and 0xcf06 contain the enable 
-bit mask and registers 0xcf01, 0xcf03, 0xcf05 and 0xcf07 contain the inverter bits.
+bit mask.
+Additionally, inputs can be inverted (0xcf24) and short signals can be stretched to at least 10 ns length (0xcf22).
+
 
 \paragraph*{Input Scalers}
 An additional module is used to have counters for each of up to 32 input channels. These values can
 be stored in a Fifo at an adjustable rate. The Fifos for all channels are controlled by a common
 logic and store their data synchronously. Filling of the Fifos has to be triggered and stops after
 1024 samples have been acquired.
+To save ressources, it is also possible to use only one monitoring fifo combined with a multiplexer
+to select one of the inputs as source.
 
 \begin{description*}
  \item[cf00, cf02 .. cf1e] Input enable mask. Up to 16 times, according to number of outputs.
- \item[cf01, cf03 .. cf1f] Input invert mask. Up to 16 times, according to number of outputs.
  \item[cf20] Status of all input signals
  \item[cf21] Status of all trigger output signals
+ \item[cf22] Signal stretcher (at least 10 ns long) for each input
+ \item[cf24] Invert of all input signals
  \item[cf80] Input enable for monitoring
  \item[cf81] Input invert for monitoring
  \item[cf82] Set the monitoring rate in units of 10 ns (FPGA clock frequency)
@@ -44,8 +47,9 @@ logic and store their data synchronously. Filling of the Fifos has to be trigger
  \item[cf84] Debug: Status register
  \item[cf8e] Status of all input signals
  \item[cf8f] Bit 0: Trigger recording of data. Fifo are cleared, then 1024 samples are acquired\\
-             Bit 1: Reset counters
+             Bit 1: Reset counters\\
+             Bit 20-16: Input select (if only a single fifo is used)
  \item[cfa0 .. cfbf] One fifo for each input. Up to 1024 values of 18 Bit are stored. The uppermost
 bit is the Fifo empty signal (data invalid)
  \item[cfc0 .. cfdf] One counter for each input. The width is 24 Bit.
-\end{description*}
\ No newline at end of file
+\end{description*}