16 bit flash, IF

diff --git a/thresholds/thresholds.prj b/thresholds/thresholds.prj
index d570bd6614e357fc84b932efd5c64b04f4ccc88a..c68aaaa80c50c31f31942911641495fb028f9bfd 100644 (file)
--- a/thresholds/thresholds.prj
+++ b/thresholds/thresholds.prj
@@ -5,6 +5,7 @@
 #project files
 
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "workdir/version.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/interface/spi_slave.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/sedcheck.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/io/pwm.vhd"
@@ -12,7 +13,7 @@ add_file -vhdl -lib work "../../vhdlbasics/io/pwm.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flashram.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flash.vhd"
 add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/efb_define_def.v"
-add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB.v"
+add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB_16bit.v"
 
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/generic_flash_ctrl.vhd"
 add_file -vhdl -lib work "thresholds.vhd"

diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd
index a00dd8b93ec48245f0f168da75d00a31c1d59f78..d06996f9e6a47a320c5695a4087cd94c22813323 100644 (file)
--- a/thresholds/thresholds.vhd
+++ b/thresholds/thresholds.vhd
@@ -7,6 +7,7 @@ use machxo3lf.all;
 \r
 library work;\r
 use work.trb_net_std.all;\r
+use work.version.all;\r
 \r
 entity thresholds is\r
   port(\r
@@ -141,33 +142,31 @@ PROC_REGS : process begin
   \r
     if bus_read = '1' then\r
       bus_ready <= '1';\r
-      if (spi_addr >= x"10") and (spi_addr < X"20") then\r
+      if (spi_addr >= x"00") and (spi_addr < x"10") then\r
        spi_tx_data <= ram_data(to_integer(unsigned(spi_addr(3 downto 0)))); -- Read RAM\r
-        --spi_tx_data <= "00000000" & spi_addr; \r
       else\r
         case spi_addr is\r
-             when x"ee" => spi_tx_data <= sed_debug(15 downto 0);\r
-             when x"ef" => spi_tx_data <= sed_debug(31 downto 16);\r
-             when others => null;\r
+          when x"30" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16));\r
+          when x"31" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16));\r
+          when x"ee" => spi_tx_data <= sed_debug(15 downto 0);\r
+          when x"ef" => spi_tx_data <= sed_debug(31 downto 16);\r
+          when x"ff" => spi_tx_data <= x"0100"; --version number\r
+          when others => spi_tx_data <= x"0000";\r
         end case; \r
       end if;\r
       \r
     elsif bus_write = '1' then\r
-      if (spi_addr >= x"00") and (spi_addr < x"10") then  -- write directly to PWM\r
-         pwm_data  <= spi_rx_data;\r
-         pwm_addr  <= spi_addr(4 downto 0);\r
-         pwm_write <= '1';\r
-      elsif (spi_addr >= x"10") and (spi_addr <  x"20") then  -- write to RAM\r
+--      if (spi_addr >= x"00") and (spi_addr < x"10") then  -- write directly to PWM\r
+--       pwm_data  <= spi_rx_data;\r
+--       pwm_addr  <= spi_addr(4 downto 0);\r
+--       pwm_write <= '1';\r
+      if (spi_addr >= x"00") and (spi_addr <  x"10") then  -- write to RAM\r
          ram_data(to_integer(unsigned(spi_addr(3 downto 0)))) <= spi_rx_data;\r
          pwm_data  <= spi_rx_data;\r
          pwm_addr  <= spi_addr(4 downto 0);\r
          pwm_write <= '1';\r
       else\r
           case spi_addr is\r
---           when x"20" => flash_command <= '1'; --write to flash;\r
---                         flash_go      <= '1';\r
---           when x"21" => flash_command <= '0'; --read from flash;\r
---                         flash_go      <= '1';\r
               when x"22" => compensate_i  <= signed(spi_rx_data(15 downto 0));--signed(uart_rx_data(15 downto 0);\r
               when x"ee" => controlsed_i  <= spi_rx_data(3 downto 0);\r
              when others => null;\r