debug pins unified

diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
index ced1d905a70e80710a0e8a787458a670facc26fe..03de147d278aa47c9e14173d5edb7796aef34dce 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
@@ -26,12 +26,12 @@ entity med_ecp3_sfp_sync_all_RS is
     MEDIA_MED2INT      : out med2int_array_t(0 to 3);
     MEDIA_INT2MED      : in  int2med_array_t(0 to 3);
     -- komma operation
-    RX_DLM_OUT         : out std_logic_vector(3 downto 0); -- DLM received
-    RX_DLM_WORD_OUT    : out std_logic_vector(4*8-1 downto 0);
+    RX_DLM_OUT         : out std_logic_vector(3 downto 0); -- DLM received, one clock cycle active
+    RX_DLM_WORD_OUT    : out std_logic_vector(4*8-1 downto 0); -- DLM data byte, registered
     TX_DLM_IN          : in  std_logic;
     TX_DLM_WORD_IN     : in  std_logic_vector(7 downto 0);
-    RX_RST_OUT         : out std_logic; -- RST received
-    RX_RST_WORD_OUT    : out std_logic_vector(7 downto 0);
+    RX_RST_OUT         : out std_logic; -- RST received, one clock cycle active
+    RX_RST_WORD_OUT    : out std_logic_vector(7 downto 0); -- RST data byte, registered
     TX_RST_IN          : in  std_logic;
     TX_RST_WORD_IN     : in  std_logic_vector(7 downto 0);
     -- sync operation
@@ -477,8 +477,8 @@ end generate;
       BUS_RX      => BUS_RX,
       BUS_TX      => BUS_TX,
       -- 
-      MEDIA_STATUS_REG_IN(31 downto 0)   => stat_rx_control_i(31 downto 0),
-      MEDIA_STATUS_REG_IN(63 downto 32)  => stat_tx_control_i(31 downto 0),
+      MEDIA_STATUS_REG_IN(31 downto 0)    => stat_rx_control_i(31 downto 0),
+      MEDIA_STATUS_REG_IN(63 downto 32)   => stat_tx_control_i(31 downto 0),
       MEDIA_STATUS_REG_IN(191 downto 64)  => stat_fsm_reset_i(127 downto 0),
       MEDIA_STATUS_REG_IN(199 downto 192) => cv_cnt_sys(0),
       MEDIA_STATUS_REG_IN(207 downto 200) => cv_cnt_sys(1),
@@ -493,11 +493,12 @@ end generate;
   STAT_DEBUG(63 downto 0)  <= (others => '0');
   
 --  DEBUG_OUT <= debug_i(3*32+31 downto 3*32);
-  DEBUG_OUT(8 downto 0)   <= debug_i(3*32+8 downto 3*32);
-  DEBUG_OUT(9)            <= wa_read_i;
-  DEBUG_OUT(10)           <= tx_clk_avail_sel;
-  DEBUG_OUT(11)           <= GLOBAL_RESET_IN;
-  DEBUG_OUT(31 downto 12) <= debug_i(3*32+31 downto 3*32+12);
+  DEBUG_OUT(11 downto 0)  <= debug_i(3*32+11 downto 3*32);
+  DEBUG_OUT(12)           <= wa_read_i;
+  DEBUG_OUT(13)           <= tx_clk_avail_sel;
+  DEBUG_OUT(14)           <= GLOBAL_RESET_IN;
+  DEBUG_OUT(15)           <= '0';
+  DEBUG_OUT(31 downto 16) <= debug_i(3*32+31 downto 3*32+16);
   
 end architecture;
 

diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd
index e28b7f81867699863b34685007f88f227e63b8b9..a46bdef423cf0f525535b83e29636732a021455b 100644 (file)
--- a/media_interfaces/sync/med_sync_control_RS.vhd
+++ b/media_interfaces/sync/med_sync_control_RS.vhd
@@ -289,19 +289,20 @@ begin
                                          else x"7";
 
 -- TEST_LINE signals
-  DEBUG_OUT(0)            <= SFP_LOS_IN;
-  DEBUG_OUT(1)            <= RX_LOS_IN;
-  DEBUG_OUT(2)            <= RX_CDR_LOL_IN;
-  DEBUG_OUT(3)            <= rx_pcs_rst_i;
-  DEBUG_OUT(4)            <= rx_serdes_rst_i;
-  DEBUG_OUT(5)            <= TX_PLL_LOL_IN;
-  DEBUG_OUT(6)            <= is_wap_zero_i;
-  DEBUG_OUT(7)            <= link_rx_ready_i;
-  DEBUG_OUT(8)            <= LINK_TX_READY_IN;
-  DEBUG_OUT(9)            <= '0';
-  DEBUG_OUT(10)           <= '0';
-  DEBUG_OUT(11)           <= '0';
-  DEBUG_OUT(15 downto 12) <= rx_fsm_state;
+  DEBUG_OUT(3 downto 0)   <= rx_fsm_state;
+  DEBUG_OUT(4)            <= RX_LOS_IN;
+  DEBUG_OUT(5)            <= RX_CDR_LOL_IN;
+  DEBUG_OUT(6)            <= TX_PLL_LOL_IN;
+  DEBUG_OUT(7)            <= LINK_TX_READY_IN;
+  DEBUG_OUT(8)            <= link_rx_ready_i;
+  DEBUG_OUT(9)            <= is_wap_zero_i;
+  DEBUG_OUT(10)           <= link_half_done_i;
+  DEBUG_OUT(11)           <= link_full_done_i;
+  DEBUG_OUT(12)           <= '0';
+  DEBUG_OUT(13)           <= '0';
+  DEBUG_OUT(14)           <= '0';
+  DEBUG_OUT(15)           <= '0';
+-- 16 pin debug connector ends here
   DEBUG_OUT(21 downto 16) <= debug_tx_control_i(5 downto 0);
   DEBUG_OUT(31 downto 22) <= (others => '0');
 --  DEBUG_OUT        <= (others => '0');

diff --git a/media_interfaces/sync/rx_rsl.vhd b/media_interfaces/sync/rx_rsl.vhd
index 0e3cabf153b31c01edd4c06466522637be005a44..019a9038c5b9461dbdc3c299af80643de9d55fc6 100644 (file)
--- a/media_interfaces/sync/rx_rsl.vhd
+++ b/media_interfaces/sync/rx_rsl.vhd
@@ -42,8 +42,8 @@ architecture rx_rsl_arc of rx_rsl is
   signal cnt          : unsigned(31 downto 0);\r
 \r
   type rx_sm_state is (POWERUP, APPLY_CDR_RST, WAIT_CDR_LOCK, TEST_CDR, \r
-                       APPLY_RXPCS_RST, WAIT_RXPCS_LOCK, TEST_RXPCS, \r
-                       CHECK_WAP, TX_SYNC, NORMAL_OP);\r
+                       CHECK_WAP, APPLY_RXPCS_RST, WAIT_RXPCS_LOCK, \r
+                       TEST_RXPCS, NORMAL_OP);\r
 \r
   signal rx_sm : rx_sm_state;\r
   \r
@@ -131,15 +131,28 @@ begin
         else\r
           if( cnt = Tcdr ) then\r
             cnt <= (others => '0');\r
-            rx_sm <= APPLY_RXPCS_RST;\r
+            rx_sm <= CHECK_WAP;\r
           else\r
             cnt <= cnt + 1;\r
           end if;\r
         end if;\r
 \r
-      when APPLY_RXPCS_RST =>\r
+      -- THIS STATE CAN BE ASSIMILATED INTO TEST_CDR\r
+      when CHECK_WAP => \r
         STATE_OUT <= x"4";\r
         RX_SERDES_RST_OUT <= '0';\r
+        RX_PCS_RST_OUT    <= '1'; -- really?\r
+        LINK_RX_READY_OUT <= '0';\r
+        cnt <= (others => '0');\r
+        if( WAP_ZERO_IN = '1' ) then\r
+          rx_sm <= NORMAL_OP;\r
+        else\r
+          rx_sm <= APPLY_CDR_RST;\r
+        end if;\r
+\r
+      when APPLY_RXPCS_RST =>\r
+        STATE_OUT <= x"5";\r
+        RX_SERDES_RST_OUT <= '0';\r
         RX_PCS_RST_OUT    <= '1';\r
         LINK_RX_READY_OUT <= '0';\r
         if( cnt = Tshort ) then\r
@@ -150,7 +163,7 @@ begin
         end if;\r
 \r
       when WAIT_RXPCS_LOCK =>\r
-        STATE_OUT <= x"5";\r
+        STATE_OUT <= x"6";\r
         RX_SERDES_RST_OUT <= '0';\r
         RX_PCS_RST_OUT    <= '0';\r
         LINK_RX_READY_OUT <= '0';\r
@@ -162,7 +175,7 @@ begin
         end if;\r
 \r
       when TEST_RXPCS =>\r
-        STATE_OUT <= x"6";\r
+        STATE_OUT <= x"7";\r
         RX_SERDES_RST_OUT <= '0';\r
         RX_PCS_RST_OUT    <= '0';\r
         LINK_RX_READY_OUT <= '0';\r
@@ -172,24 +185,11 @@ begin
         else\r
           if( cnt = Tviol ) then\r
             cnt <= (others => '0');\r
-            rx_sm <= CHECK_WAP;\r
+            rx_sm <= NORMAL_OP;\r
           else\r
             cnt <= cnt + 1;\r
           end if;\r
         end if;\r
-\r
-      when CHECK_WAP =>\r
-        STATE_OUT <= x"7";\r
-        RX_SERDES_RST_OUT <= '0';\r
-        RX_PCS_RST_OUT    <= '0';\r
-        LINK_RX_READY_OUT <= '0';\r
-        cnt <= (others => '0');\r
-        if( WAP_ZERO_IN = '1' ) then\r
-          rx_sm <= NORMAL_OP;\r
-        else\r
---          rx_sm <= APPLY_RXPCS_RST; -- DOESNT WORK\r
-          rx_sm <= APPLY_CDR_RST;\r
-        end if;\r
      \r
       when NORMAL_OP =>\r
         STATE_OUT <= x"8";\r

diff --git a/media_interfaces/sync/rx_rsl_ORIG.vhd b/media_interfaces/sync/rx_rsl_ORIG.vhd
new file mode 100644 (file)
index 0000000..0e3cabf
--- /dev/null
+++ b/media_interfaces/sync/rx_rsl_ORIG.vhd
@@ -0,0 +1,224 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+USE IEEE.numeric_std.all;\r
+\r
+entity rx_rsl is\r
+  port (\r
+    CLEAR             : in  std_logic;\r
+    CLK_REF           : in  std_logic;\r
+    PLL_LOL_IN        : in  std_logic;\r
+    CDR_LOL_IN        : in  std_logic;\r
+    CV_IN             : in  std_logic;\r
+    LSM_IN            : in  std_logic;\r
+    LOS_IN            : in  std_logic;\r
+    WAP_ZERO_IN       : in  std_logic;\r
+    -- outputs\r
+    RX_SERDES_RST_OUT : out std_logic;\r
+    RX_PCS_RST_OUT    : out std_logic;\r
+    LINK_RX_READY_OUT : out std_logic;\r
+    STATE_OUT         : out std_logic_vector(3 downto 0)\r
+  );\r
+end rx_rsl;  \r
+\r
+architecture rx_rsl_arc of rx_rsl is\r
+\r
+  attribute syn_keep : boolean;\r
+\r
+-- Remark: work of Christian Michel. Just re-edited to reflect necessary changes for ECP3.\r
+-- Without this piece of code, many things would have been a real pain.\r
+\r
+  constant Tshort     : unsigned(31 downto 0) := x"0000000a";\r
+-- @200MHz 100ms\r
+  constant Tplol      : unsigned(31 downto 0) := x"003fffff"; --x"01312d00";\r
+  constant Tcdr       : unsigned(31 downto 0) := x"003fffff"; --x"01312d00";\r
+  constant Tviol      : unsigned(31 downto 0) := x"003fffff"; --x"01312d00";\r
+\r
+  signal pll_lol_s    : std_logic;\r
+  signal cdr_lol_s    : std_logic;\r
+  signal cv_s         : std_logic;\r
+  signal lsm_s        : std_logic;\r
+  signal los_s        : std_logic;\r
+\r
+  signal cnt          : unsigned(31 downto 0);\r
+\r
+  type rx_sm_state is (POWERUP, APPLY_CDR_RST, WAIT_CDR_LOCK, TEST_CDR, \r
+                       APPLY_RXPCS_RST, WAIT_RXPCS_LOCK, TEST_RXPCS, \r
+                       CHECK_WAP, TX_SYNC, NORMAL_OP);\r
+\r
+  signal rx_sm : rx_sm_state;\r
+  \r
+  attribute syn_keep of rx_sm : signal is true;\r
+\r
+begin\r
+\r
+-- Remark: on ECP3, rx_serdes_rst sets RX_CDR_LOL. Deadlocks on POWERUP.\r
+-- Remark: RX_LOS is not necessary, as SFP_LOS keeps us safely in reset.\r
+-- Remark: syncing is done here by one FF only. Might be dangerous.\r
+\r
+------------------------------------------------------------------\r
+RX_RESET_PROC : process( CLEAR, CLK_REF )\r
+begin\r
+  if( CLEAR = '1' ) then\r
+    pll_lol_s         <= '1';\r
+    cdr_lol_s         <= '1';\r
+    cv_s              <= '1';\r
+    lsm_s             <= '0';\r
+    los_s             <= '1';\r
+\r
+    RX_SERDES_RST_OUT <= '1';\r
+    RX_PCS_RST_OUT    <= '1';\r
+    LINK_RX_READY_OUT <= '0';\r
+    \r
+    rx_sm         <= powerup;\r
+    STATE_OUT     <= x"f";\r
+    cnt           <= (others => '0');  \r
+  elsif( rising_edge(CLK_REF) ) then\r
+    pll_lol_s     <= PLL_LOL_IN;\r
+    cdr_lol_s     <= CDR_LOL_IN;\r
+    cv_s          <= CV_IN;    \r
+    lsm_s         <= LSM_IN;    \r
+    los_s         <= LOS_IN;  \r
+  \r
+    case rx_sm is\r
+      when POWERUP =>\r
+        STATE_OUT <= x"0";\r
+        RX_SERDES_RST_OUT <= '0'; -- needed for RX_LOS to be active\r
+        RX_PCS_RST_OUT    <= '1';\r
+        LINK_RX_READY_OUT <= '0';\r
+        if( (pll_lol_s = '1') or (los_s = '1') ) then\r
+          cnt <= (others => '0');\r
+        else\r
+          if( cnt = Tplol ) then\r
+            cnt <= (others => '0');\r
+            rx_sm <= APPLY_CDR_RST;\r
+          else\r
+          cnt <= cnt + 1;\r
+          end if;\r
+        end if;\r
+\r
+      when APPLY_CDR_RST =>\r
+        STATE_OUT <= x"1";\r
+        RX_SERDES_RST_OUT <= '1';\r
+        RX_PCS_RST_OUT    <= '1';\r
+        LINK_RX_READY_OUT <= '0';\r
+        if( cnt = Tshort ) then\r
+          cnt <= (others => '0');\r
+          rx_sm <= WAIT_CDR_LOCK;\r
+        else\r
+          cnt <= cnt + 1;  \r
+        end if;\r
+      \r
+      when WAIT_CDR_LOCK =>\r
+        STATE_OUT <= x"2";\r
+        RX_SERDES_RST_OUT <= '0';\r
+        RX_PCS_RST_OUT    <= '1';\r
+        LINK_RX_READY_OUT <= '0';\r
+        if( cnt = Tcdr ) then\r
+          cnt <= (others => '0');\r
+          rx_sm <= TEST_CDR;\r
+        else\r
+          cnt <= cnt + 1;  \r
+        end if;\r
+\r
+      when TEST_CDR =>\r
+        STATE_OUT <= x"3";\r
+        RX_SERDES_RST_OUT <= '0';\r
+        RX_PCS_RST_OUT    <= '1';\r
+        LINK_RX_READY_OUT <= '0';\r
+        if( cdr_lol_s = '1' ) then\r
+          cnt <= (others => '0');\r
+          rx_sm <= APPLY_CDR_RST;\r
+        else\r
+          if( cnt = Tcdr ) then\r
+            cnt <= (others => '0');\r
+            rx_sm <= APPLY_RXPCS_RST;\r
+          else\r
+            cnt <= cnt + 1;\r
+          end if;\r
+        end if;\r
+\r
+      when APPLY_RXPCS_RST =>\r
+        STATE_OUT <= x"4";\r
+        RX_SERDES_RST_OUT <= '0';\r
+        RX_PCS_RST_OUT    <= '1';\r
+        LINK_RX_READY_OUT <= '0';\r
+        if( cnt = Tshort ) then\r
+          cnt <= (others => '0');\r
+          rx_sm <= WAIT_RXPCS_LOCK;\r
+        else\r
+          cnt <= cnt + 1;  \r
+        end if;\r
+\r
+      when WAIT_RXPCS_LOCK =>\r
+        STATE_OUT <= x"5";\r
+        RX_SERDES_RST_OUT <= '0';\r
+        RX_PCS_RST_OUT    <= '0';\r
+        LINK_RX_READY_OUT <= '0';\r
+        if( cnt = Tviol ) then\r
+          cnt <= (others => '0');\r
+          rx_sm <= TEST_RXPCS;\r
+        else\r
+          cnt <= cnt + 1;  \r
+        end if;\r
+\r
+      when TEST_RXPCS =>\r
+        STATE_OUT <= x"6";\r
+        RX_SERDES_RST_OUT <= '0';\r
+        RX_PCS_RST_OUT    <= '0';\r
+        LINK_RX_READY_OUT <= '0';\r
+        if( (lsm_s = '0') or (cv_s = '1') ) then\r
+          cnt <= (others => '0');\r
+          rx_sm <= APPLY_RXPCS_RST;\r
+        else\r
+          if( cnt = Tviol ) then\r
+            cnt <= (others => '0');\r
+            rx_sm <= CHECK_WAP;\r
+          else\r
+            cnt <= cnt + 1;\r
+          end if;\r
+        end if;\r
+\r
+      when CHECK_WAP =>\r
+        STATE_OUT <= x"7";\r
+        RX_SERDES_RST_OUT <= '0';\r
+        RX_PCS_RST_OUT    <= '0';\r
+        LINK_RX_READY_OUT <= '0';\r
+        cnt <= (others => '0');\r
+        if( WAP_ZERO_IN = '1' ) then\r
+          rx_sm <= NORMAL_OP;\r
+        else\r
+--          rx_sm <= APPLY_RXPCS_RST; -- DOESNT WORK\r
+          rx_sm <= APPLY_CDR_RST;\r
+        end if;\r
+     \r
+      when NORMAL_OP =>\r
+        STATE_OUT <= x"8";\r
+        RX_SERDES_RST_OUT <= '0';\r
+        RX_PCS_RST_OUT    <= '0';\r
+        LINK_RX_READY_OUT <= '1';\r
+        cnt <= (others => '0');\r
+        if( (lsm_s = '0') or (cv_s = '1') ) then\r
+          rx_sm <= APPLY_RXPCS_RST;      \r
+        end if;\r
+\r
+      when others =>\r
+        -- just in case\r
+        STATE_OUT <= x"f";\r
+        RX_SERDES_RST_OUT <= '0';\r
+        RX_PCS_RST_OUT    <= '0';\r
+        LINK_RX_READY_OUT <= '0';\r
+        rx_sm <= POWERUP;\r
+\r
+    end case;\r
+  \r
+------------------------------------------------\r
+--  if (pll_lol_s = '1') or (los_s = '1') then\r
+    if( pll_lol_s = '1' ) then\r
+      rx_sm <= POWERUP;      \r
+      cnt <= (others => '0');\r
+    end if;\r
+\r
+  end if;\r
+end process rx_reset_proc;\r
+\r
+end rx_rsl_arc;\r