<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_source_downstream" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 01 30 17:46:08.463" version="8.1" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="serdes_sync_source_downstream" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 03 02 17:24:32.835" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_sync_source_downstream.lpc" type="lpc" modified="2015 01 30 17:46:06.000"/>
- <File name="serdes_sync_source_downstream.pp" type="pp" modified="2015 01 30 17:46:06.000"/>
- <File name="serdes_sync_source_downstream.sym" type="sym" modified="2015 01 30 17:46:07.000"/>
- <File name="serdes_sync_source_downstream.tft" type="tft" modified="2015 01 30 17:46:06.000"/>
- <File name="serdes_sync_source_downstream.txt" type="pcs_module" modified="2015 01 30 17:46:06.000"/>
- <File name="serdes_sync_source_downstream.vhd" type="top_level_vhdl" modified="2015 01 30 17:46:06.000"/>
+ <File name="serdes_sync_source_downstream.lpc" type="lpc" modified="2015 03 02 17:24:29.000"/>
+ <File name="serdes_sync_source_downstream.pp" type="pp" modified="2015 03 02 17:24:29.000"/>
+ <File name="serdes_sync_source_downstream.sym" type="sym" modified="2015 03 02 17:24:30.000"/>
+ <File name="serdes_sync_source_downstream.tft" type="tft" modified="2015 03 02 17:24:29.000"/>
+ <File name="serdes_sync_source_downstream.txt" type="pcs_module" modified="2015 03 02 17:24:29.000"/>
+ <File name="serdes_sync_source_downstream.vhd" type="top_level_vhdl" modified="2015 03 02 17:24:29.000"/>
</Package>
</DiamondModule>
CoreType=LPM
CoreStatus=Demo
CoreName=PCS
-CoreRevision=8.1
+CoreRevision=8.2
ModuleName=serdes_sync_source_downstream
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=01/30/2015
-Time=17:46:06
+Date=03/02/2015
+Time=17:24:29
[Parameters]
Verilog=0
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 12 03 15:52:30.411" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 03 04 13:04:52.349" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_sync_upstream.lpc" type="lpc" modified="2014 12 03 15:52:28.000"/>
- <File name="serdes_sync_upstream.pp" type="pp" modified="2014 12 03 15:52:28.000"/>
- <File name="serdes_sync_upstream.sym" type="sym" modified="2014 12 03 15:52:29.000"/>
- <File name="serdes_sync_upstream.tft" type="tft" modified="2014 12 03 15:52:28.000"/>
- <File name="serdes_sync_upstream.txt" type="pcs_module" modified="2014 12 03 15:52:28.000"/>
- <File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2014 12 03 15:52:28.000"/>
+ <File name="serdes_sync_upstream.lpc" type="lpc" modified="2015 03 04 13:04:49.000"/>
+ <File name="serdes_sync_upstream.pp" type="pp" modified="2015 03 04 13:04:49.000"/>
+ <File name="serdes_sync_upstream.sym" type="sym" modified="2015 03 04 13:04:49.000"/>
+ <File name="serdes_sync_upstream.tft" type="tft" modified="2015 03 04 13:04:49.000"/>
+ <File name="serdes_sync_upstream.txt" type="pcs_module" modified="2015 03 04 13:04:49.000"/>
+ <File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2015 03 04 13:04:49.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_sync_upstream
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=12/03/2014
-Time=15:52:28
+Date=03/04/2015
+Time=13:04:49
[Parameters]
Verilog=0
_tx_data_width1=8
_tx_data_width2=8
_tx_data_width3=8
-_tx_fifo0=DISABLED
+_tx_fifo0=ENABLED
_tx_fifo1=ENABLED
_tx_fifo2=ENABLED
_tx_fifo3=DISABLED
_tx_ficlk_rate1=200
_tx_ficlk_rate2=200
_tx_ficlk_rate3=200
-_pll_rxsrc0=INTERNAL
+_pll_rxsrc0=EXTERNAL
_pll_rxsrc1=EXTERNAL
_pll_rxsrc2=EXTERNAL
_pll_rxsrc3=INTERNAL
Multiplier1=
Multiplier2=
Multiplier3=
-_rx_datarange0=2
+_rx_datarange0=2.5
_rx_datarange1=2.5
_rx_datarange2=2.5
_rx_datarange3=2
_rx_data_rate1=FULL
_rx_data_rate2=FULL
_rx_data_rate3=FULL
-_rxrefclk_rate0=200
+_rxrefclk_rate0=250.0
_rxrefclk_rate1=250.0
_rxrefclk_rate2=250.0
_rxrefclk_rate3=200
_rx_data_width1=8
_rx_data_width2=8
_rx_data_width3=8
-_rx_fifo0=DISABLED
+_rx_fifo0=ENABLED
_rx_fifo1=ENABLED
_rx_fifo2=ENABLED
_rx_fifo3=DISABLED
-_rx_ficlk_rate0=200
+_rx_ficlk_rate0=250.0
_rx_ficlk_rate1=250.0
_rx_ficlk_rate2=250.0
_rx_ficlk_rate3=200
_rterm_rx1=50
_rterm_rx2=50
_rterm_rx3=50
-_rx_dcc0=DC
+_rx_dcc0=AC
_rx_dcc1=AC
_rx_dcc2=AC
_rx_dcc3=DC
_cc_match_mode1=1
_cc_match_mode2=1
_cc_match_mode3=1
-_k00=01
+_k00=00
_k01=00
_k02=00
-_k03=01
+_k03=00
_k10=00
_k11=00
_k12=00
_k31=01
_k32=01
_k33=01
-_byten00=00011100
+_byten00=00000000
_byten01=00000000
_byten02=00000000
-_byten03=00011100
+_byten03=00000000
_byten10=00000000
_byten11=00000000
_byten12=00000000
CH3_RXWA "ENABLED"
CH3_ILSM "ENABLED"
CH3_CTC "DISABLED"
-CH3_CC_MATCH4 "0100011100"
+CH3_CC_MATCH4 "0000000000"
CH3_CC_MATCH_MODE "1"
CH3_CC_MIN_IPG "3"
CCHMARK "9"
PLL_SRC : String
-- CONFIG_FILE : String := "serdes_sync_upstream.txt";
-- QUAD_MODE : String := "SINGLE";
--- CH0_CDR_SRC : String := "REFCLK_CORE";
+-- CH0_CDR_SRC : String := "REFCLK_EXT";
-- CH1_CDR_SRC : String := "REFCLK_EXT";
-- CH2_CDR_SRC : String := "REFCLK_EXT";
-- CH3_CDR_SRC : String := "REFCLK_CORE";
attribute CH3_CDR_SRC: string;
attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "250.000";
attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "200.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "200.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "125.000";
attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "100.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "100.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
component DCS\r
-- synthesis translate_off\r
generic\r
- (\r
-DCSMODE : string :=“POS”\r
+(\r
+ DCSMODE : string :="POS"\r
);\r
-- synthesis translate_on\r
port (\r
component DCS
-- synthesis translate_off
-generic
- (
-DCSMODE : string :=“POS”
+generic(\r
+DSCMODE : string :="POS"\r
);
-- synthesis translate_on
port (
SCI_RD => sci_read_i,
SCI_WRN => sci_write_i,
- fpga_txrefclk => rx_full_clk,
+ fpga_txrefclk => clk_200_osc, --rx_full_clk,
tx_serdes_rst_c => tx_serdes_rst,
tx_pll_lol_qd_s => tx_pll_lol,
rst_qd_c => rst_qd,
SYSCLK : in std_logic; -- fabric clock
SODACLK : in std_logic; -- clock for data to serdes
RESET : in std_logic; -- synchronous reset
- --Internal Connection
+\r
SODA_BURST_PULSE_IN : in std_logic := '0'; --
+ SODA_CYCLE_IN : in std_logic := '0'; --
RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0');
RX_DLM_IN : in std_logic;
SODA_WRITE_IN : in std_logic := '0';
SODA_ACK_OUT : out std_logic := '0';
LEDS_OUT : out std_logic_vector(3 downto 0)
- );
+ );
end component;
\r
component soda_4source is
component DCS
-- synthesis translate_off
generic
- (
-DCSMODE : string :=“POS”
+(
+ DCSMODE : string :="POS"
);
-- synthesis translate_on
port (
--STAT_OP(5) <= request_retr_i;
--STAT_OP(4) <= start_retr_i;
--STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
-end soda_only_ecp3_sfp_sync_up_arch;
\ No newline at end of file
+end soda_only_ecp3_sfp_sync_up_arch;
SYSCLK : in std_logic; -- fabric clock
SODACLK : in std_logic; -- clock for data to serdes
RESET : in std_logic; -- synchronous reset
- --Internal Connection
+\r
SODA_BURST_PULSE_IN : in std_logic := '0'; --
+ SODA_CYCLE_IN : in std_logic := '0'; --
RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0');
RX_DLM_IN : in std_logic;
SODA_WRITE_IN : in std_logic := '0';
SODA_ACK_OUT : out std_logic := '0';
LEDS_OUT : out std_logic_vector(3 downto 0)
- );
+ );
end soda_source;
architecture Behavioral of soda_source is
packet_builder : soda_packet_builder
port map(
- SODACLK => SODACLK,
- RESET => RESET,
+ SODACLK => SODACLK,
+ RESET => RESET,
--Internal Connection
- LINK_PHASE_IN => LINK_PHASE_IN, --link_phase_S, PL!
- SODA_CMD_STROBE_IN => soda_send_cmd_S,
- START_OF_SUPERBURST => start_of_superburst_S,
- SUPER_BURST_NR_IN => super_burst_nr_S,
- SODA_CMD_WORD_IN => soda_cmd_word_S,
- EXPECTED_REPLY_OUT => expected_reply_S,
- TIME_CAL_OUT => start_calibration_S,\r
- TX_DLM_PREVIEW_OUT => TX_DLM_PREVIEW_OUT,
- TX_DLM_OUT => TX_DLM_OUT,
- TX_DLM_WORD_OUT => TX_DLM_WORD_OUT
- );
+ LINK_PHASE_IN => LINK_PHASE_IN, --link_phase_S, PL!
+ SODA_CYCLE_IN => SODA_CYCLE_IN,
+
+ SODA_CMD_STROBE_IN => soda_send_cmd_S,
+ START_OF_SUPERBURST => start_of_superburst_S,
+ SUPER_BURST_NR_IN => super_burst_nr_S,
+ SODA_CMD_WORD_IN => soda_cmd_word_S,
+ EXPECTED_REPLY_OUT => expected_reply_S,
+ TIME_CAL_OUT => start_calibration_S,\r
+ TX_DLM_PREVIEW_OUT => TX_DLM_PREVIEW_OUT,
+ TX_DLM_OUT => TX_DLM_OUT,
+ TX_DLM_WORD_OUT => TX_DLM_WORD_OUT
+ );
src_reply_handler : soda_reply_handler
port map(
signal txdn_half_clk : t_HUB_BIT;\r
signal txdn_full_clk : t_HUB_BIT;\r
\r
--- signal clk_tdc : std_logic;\r
- signal time_counter, time_counter2 : unsigned(31 downto 0);\r
+ signal time_counter : unsigned(31 downto 0);\r
--Media Interface\r
- signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');\r
- signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');\r
- signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0) := (others => '0');\r
- signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0) := (others => '0');\r
- signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');\r
- signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0) := (others => '0');\r
- signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');\r
- signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');\r
- signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');\r
- signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0) := (others => '0');\r
- signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');\r
- signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');\r
+ signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');\r
+ signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');\r
+ signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0) := (others => '0');\r
+ signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0) := (others => '0');\r
+ signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');\r
+ signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0) := (others => '0');\r
+ signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');\r
+ signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');\r
+ signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');\r
+ signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0) := (others => '0');\r
+ signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');\r
+ signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');\r
\r
--Slow Control channel\r
signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);\r
signal link_debug_in_S : std_logic_vector(31 downto 0);\r
signal general_reset_i : std_logic := '1';\r
\r
- signal soda_counter_i : unsigned(3 downto 0);\r
+-- signal soda_counter_i : unsigned(31 downto 0);\r
\r
\r
- attribute syn_keep of soda_counter_i : signal is true;\r
+-- attribute syn_keep of soda_counter_i : signal is true;\r
-- fix signal names for constraining\r
attribute syn_preserve of clk_100_osc : signal is true;\r
attribute syn_keep of clk_100_osc : signal is true;\r
---------------------------------------------------------------------------\r
-- LED\r
---------------------------------------------------------------------------\r
- LED_ORANGE <= SFP_LOS(3); --med_stat_op(8);\r
- LED_YELLOW <= sfp_txdis_S(3); --med_stat_op(10);\r
- LED_GREEN <= med_stat_op(12); --tx_pll_lol\r
- LED_RED <= med_stat_op(11); --rx_cdr_lol\r
+-- LED_ORANGE <= SFP_LOS(3); --med_stat_op(8);\r
+-- LED_YELLOW <= sfp_txdis_S(3); --med_stat_op(10);\r
+-- LED_GREEN <= med_stat_op(12); --tx_pll_lol\r
+-- LED_RED <= med_stat_op(11); --rx_cdr_lol\r
+ LED_ORANGE <= SFP_LOS(1); --'1' when (time_counter(26)='0') else '0';
+ LED_YELLOW <= SFP_LOS(2); --'1' when (time_counter(26)='0') else '0';
+ LED_GREEN <= SFP_LOS(3); --time_counter(26);
+ LED_RED <= SFP_LOS(4); --time_counter(26);
\r
- LED_RX(1) <= med_stat_op(8);\r
- LED_RX(2) <= med_stat_op(10);\r
- LED_RX(3) <= med_stat_op(9);\r
- LED_RX(4) <= med_stat_op(6);\r
- LED_RX(5) <= '0';\r
- LED_RX(6) <= '1';\r
+---------------------------------------------------------------------------
+-- GREEN LED under sfp
+---------------------------------------------------------------------------
+ LED_LINKOK(1) <= SFP_LOS(1);
+ LED_LINKOK(2) <= SFP_LOS(2);
+ LED_LINKOK(3) <= SFP_LOS(3);
+ LED_LINKOK(4) <= SFP_LOS(4);
+ LED_LINKOK(5) <= SFP_LOS(5);
+ LED_LINKOK(6) <= SFP_LOS(6);
+
+ LED_RX(1) <= '1' when (med_stat_op(10)='0') else '0'; -- rx_allow
+ LED_RX(2) <= '1';
+ LED_RX(3) <= '1';
+ LED_RX(4) <= '1';
+ LED_RX(5) <= '1';
+ LED_RX(6) <= '1';
+
+ LED_TX(1) <= '1' when (med_stat_op(9)='0') else '0'; -- tx_allow
+ LED_TX(2) <= '1';
+ LED_TX(3) <= '1';
+ LED_TX(4) <= '1';
+ LED_TX(5) <= '1';
+ LED_TX(6) <= '1';
\r
---------------------------------------------------------------------------\r
-- DEBUG\r
---------------------------------------------------------------------------\r
-- Test Circuits\r
---------------------------------------------------------------------------\r
--- clock_counter_proc : process(rxup_half_clk, --)\r
--- begin\r
--- if rising_edge(rxup_half_clk, --) then\r
--- time_counter <= time_counter + 1;\r
--- end if;\r
--- end process;\r
\r
--- process(rxup_full_clk) --clk_soda_i) \r
--- begin\r
--- if rising_edge(rxup_full_clk) then\r
--- soda_counter_i <= soda_counter_i+1;\r
--- end if;\r
--- end process;\r
+\r
+ blink : process (clk_200_osc)
+ begin
+ if rising_edge(clk_200_osc) then
+ if (time_counter = x"FFFFFFFF") then
+ time_counter <= x"00000000";
+ else
+ time_counter <= time_counter + 1;
+ end if;
+ end if;
+ end process;\r
\r
\r
end trb3_periph_sodahub_arch;
\ No newline at end of file
CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- --Trigger
- --TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
- --TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
- --Serdes Clocks - do not use
- --CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
- --CLK_SERDES_INT_RIGHT_P : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
- --CLK_SERDES_INT_RIGHT_N : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
- -- PCSA_REFCLKP : in std_logic; -- PL! external refclock straight into serdes
- -- PCSA_REFCLKN : in std_logic; -- PL! external refclock straight into serdes
-
--serdes I/O - connect as you like, no real use
SERDES_ADDON_TX : out std_logic_vector(15 downto 0);
SERDES_ADDON_RX : in std_logic_vector(15 downto 0);
SFP_MOD0 : in std_logic_vector(6 downto 1);
SFP_TXDIS : out std_logic_vector(6 downto 1);
SFP_LOS : in std_logic_vector(6 downto 1);
- --SFP_MOD1 : inout std_logic_vector(6 downto 1);
- --SFP_MOD2 : inout std_logic_vector(6 downto 1);
- --SFP_RATESEL : out std_logic_vector(6 downto 1);
- --SFP_TXFAULT : in std_logic_vector(6 downto 1);
-
- --Flash ROM & Reboot
+ --Flash ROM & Reboot
FLASH_CLK : out std_logic;
FLASH_CS : out std_logic;
FLASH_DIN : out std_logic;
--SODA
signal SOB_S : std_logic := '0';
+ signal soda_40mhz_cycle_S : std_logic := '0';
-- fix signal names for constraining
attribute syn_preserve of soda_rx_clock_full : signal is true;
attribute syn_keep of soda_rx_clock_full : signal is true;
attribute syn_keep of tx_dlm_i : signal is true;
attribute syn_preserve of rx_dlm_i : signal is true;
attribute syn_keep of rx_dlm_i : signal is true;
+ attribute syn_preserve of soda_40mhz_cycle_S : signal is true;
+ attribute syn_keep of soda_40mhz_cycle_S : signal is true;
begin
);
end generate;
-gen_125 : if USE_125_MHZ = c_YES generate
- clk_100_osc <= CLK_GPLL_LEFT;
- clk_200_osc <= CLK_GPLL_LEFT;
-end generate;
-
---gen_sync_clocks : if SYNC_MODE = c_YES generate
--- clk_sys_i <= soda_tx_clock_half;
--- clk_200_i <= soda_tx_clock_full;
--- clk_100_osc <= soda_tx_clock_half;
--- clk_200_osc <= soda_tx_clock_full;
---end generate;
-
---gen_local_clocks : if SYNC_MODE = c_NO generate
--- clk_sys_i <= clk_100_osc;
--- clk_200_ip <= clk_200_osc;
---end generate;
-
-
---------------------------------------------------------------------------
-- The TrbNet media interface (to other FPGA)
---------------------------------------------------------------------------
IS_SYNC_SLAVE => c_NO
)
port map(
- OSCCLK => clk_200_osc,
- SYSCLK => clk_100_osc,
- RESET => reset_i,
- CLEAR => clear_i,
+ OSCCLK => clk_200_osc,
+ SYSCLK => clk_100_osc,
+ RESET => reset_i,
+ CLEAR => clear_i,
--Internal Connection for TrbNet data -> not used a.t.m.
- MED_DATA_IN => med_data_out(31 downto 16),
- MED_PACKET_NUM_IN => med_packet_num_out(5 downto 3),
- MED_DATAREADY_IN => med_dataready_out(1),
- MED_READ_OUT => med_read_in(1),
- MED_DATA_OUT => med_data_in(31 downto 16),
- MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3),
- MED_DATAREADY_OUT => med_dataready_in(1),
- MED_READ_IN => med_read_out(1),
- RX_HALF_CLK_OUT => soda_rx_clock_half,
- RX_FULL_CLK_OUT => soda_rx_clock_full,
- TX_HALF_CLK_OUT => soda_tx_clock_half,
- TX_FULL_CLK_OUT => soda_tx_clock_full,
-
- RX_DLM => rx_dlm_i,
- RX_DLM_WORD => rx_dlm_word,
- TX_DLM => tx_dlm_i,
- TX_DLM_WORD => tx_dlm_word,
+ MED_DATA_IN => med_data_out(31 downto 16),
+ MED_PACKET_NUM_IN => med_packet_num_out(5 downto 3),
+ MED_DATAREADY_IN => med_dataready_out(1),
+ MED_READ_OUT => med_read_in(1),
+ MED_DATA_OUT => med_data_in(31 downto 16),
+ MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3),
+ MED_DATAREADY_OUT => med_dataready_in(1),
+ MED_READ_IN => med_read_out(1),
+ RX_HALF_CLK_OUT => soda_rx_clock_half,
+ RX_FULL_CLK_OUT => soda_rx_clock_full,
+ TX_HALF_CLK_OUT => soda_tx_clock_half,
+ TX_FULL_CLK_OUT => soda_tx_clock_full,
+
+ RX_DLM => rx_dlm_i,
+ RX_DLM_WORD => rx_dlm_word,
+ TX_DLM => tx_dlm_i,
+ TX_DLM_WORD => tx_dlm_word,
TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL!
LINK_PHASE_OUT => link_phase_S, --PL!
--SFP Connection
- SD_RXD_P_IN => SERDES_ADDON_RX(0),
- SD_RXD_N_IN => SERDES_ADDON_RX(1),
- SD_TXD_P_OUT => SERDES_ADDON_TX(0),
- SD_TXD_N_OUT => SERDES_ADDON_TX(1),
- SD_REFCLK_P_IN => '0',
- SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => SFP_MOD0(1),
- SD_LOS_IN => SFP_LOS(1),
- SD_TXDIS_OUT => sfp_txdis_S(1), --SFP_TXDIS(1),
-
- SCI_DATA_IN => sci2_data_in,
- SCI_DATA_OUT => sci2_data_out,
- SCI_ADDR => sci2_addr,
- SCI_READ => sci2_read,
- SCI_WRITE => sci2_write,
- SCI_ACK => sci2_ack,
- SCI_NACK => sci2_nack,
+ SD_RXD_P_IN => SERDES_ADDON_RX(0),
+ SD_RXD_N_IN => SERDES_ADDON_RX(1),
+ SD_TXD_P_OUT => SERDES_ADDON_TX(0),
+ SD_TXD_N_OUT => SERDES_ADDON_TX(1),
+ SD_REFCLK_P_IN => '0',
+ SD_REFCLK_N_IN => '0',
+ SD_PRSNT_N_IN => SFP_MOD0(1),
+ SD_LOS_IN => SFP_LOS(1),
+ SD_TXDIS_OUT => sfp_txdis_S(1), --SFP_TXDIS(1),
+
+ SCI_DATA_IN => sci2_data_in,
+ SCI_DATA_OUT => sci2_data_out,
+ SCI_ADDR => sci2_addr,
+ SCI_READ => sci2_read,
+ SCI_WRITE => sci2_write,
+ SCI_ACK => sci2_ack,
+ SCI_NACK => sci2_nack,
-- Status and control port
- STAT_OP => med_stat_op(31 downto 16),
- CTRL_OP => med_ctrl_op(31 downto 16),
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
+ STAT_OP => med_stat_op(31 downto 16),
+ CTRL_OP => med_ctrl_op(31 downto 16),
+ STAT_DEBUG => open,
+ CTRL_DEBUG => (others => '0')
);
SFP_TXDIS(1) <= sfp_txdis_S(1);
---------------------------------------------------------------------------
--- The Soda Central
+-- Burst- and 40MHz cycle generator
---------------------------------------------------------------------------
-THE_SOB_SOURCE : soda_start_of_burst_faker
+THE_SOB_SOURCE : soda_start_of_burst_control
generic map(
- CLOCK_PERIOD => cSYS_CLOCK_PERIOD, -- clock-period in ns
+ CLOCK_PERIOD => cSODA_CLOCK_PERIOD, -- clock-period in ns
+ CYCLE_PERIOD => cSODA_CYCLE_PERIOD, -- cycle-period in ns
BURST_PERIOD => cBURST_PERIOD -- burst-period in ns
)
port map(
- SYSCLK => soda_tx_clock_half, --clk_100_osc, PL! 30062014
+ SODA_CLK => clk_200_osc,
RESET => reset_i,
- SODA_BURST_PULSE_OUT => SOB_S
- );
-
-
+ SODA_BURST_PULSE_OUT => SOB_S,
+ SODA_40MHZ_CYCLE_OUT => soda_40mhz_cycle_S
+ );\r
+\r
+---------------------------------------------------------------------------
+-- The Soda Central
+---------------------------------------------------------------------------
THE_SODA_SOURCE : soda_source
port map(
SYSCLK => soda_tx_clock_half, --clk_100_osc, --clk_sys_i, PL! 30062014
SODACLK => soda_tx_clock_full, --clk_200_osc, -- PL! 30062014
RESET => reset_i,
- --Internal Connection
+\r
SODA_BURST_PULSE_IN => SOB_S,
+ SODA_CYCLE_IN => soda_40mhz_cycle_S,
RX_DLM_WORD_IN => rx_dlm_word,
RX_DLM_IN => rx_dlm_i,
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
- LED_ORANGE <= SFP_LOS(1); --med_stat_op(8);
- LED_YELLOW <= sfp_txdis_S(1); --med_stat_op(10);
- LED_GREEN <= med_stat_op(12); --tx_pll_lol
- LED_RED <= med_stat_op(11); --rx_cdr_lol
+-- LED_ORANGE <= SFP_LOS(3); --med_stat_op(8);
+-- LED_YELLOW <= sfp_txdis_S(3); --med_stat_op(10);
+-- LED_GREEN <= med_stat_op(12); --tx_pll_lol
+-- LED_RED <= med_stat_op(11); --rx_cdr_lol
+ LED_ORANGE <= '1' when (med_stat_op(26)='0') else '0';
+ LED_YELLOW <= '1' when (med_stat_op(26)='0') else '0';
+ LED_GREEN <= med_stat_op(11);
+ LED_RED <= med_stat_op(10);
+
+\r
+---------------------------------------------------------------------------
+-- GREEN LED under sfp
+---------------------------------------------------------------------------
+ LED_LINKOK(1) <= SFP_LOS(1); --med_stat_op(8);
+ LED_LINKOK(2) <= SFP_LOS(2);
+ LED_LINKOK(3) <= SFP_LOS(3);
+ LED_LINKOK(4) <= SFP_LOS(4);
+ LED_LINKOK(5) <= SFP_LOS(5);
+ LED_LINKOK(6) <= SFP_LOS(6);
+
+ LED_RX(1) <= '1' when (med_stat_op(10)='0') else '0'; -- rx_allow
+ LED_RX(2) <= '1';
+ LED_RX(3) <= '1';
+ LED_RX(4) <= '1';
+ LED_RX(5) <= '1';
+ LED_RX(6) <= '1';
+
+ LED_TX(1) <= '1' when (med_stat_op(9)='0') else '0'; -- tx_allow
+ LED_TX(2) <= '1';
+ LED_TX(3) <= '1';
+ LED_TX(4) <= '1';
+ LED_TX(5) <= '1';
+ LED_TX(6) <= '1';
---------------------------------------------------------------------------
-- Test Connector
---------------------------------------------------------------------------
-- Test Circuits
---------------------------------------------------------------------------
-process
- begin
- wait until rising_edge(soda_tx_clock_half); --clk_100_osc); PL! 30062014
- time_counter <= time_counter + 1;
-end process;
-
-
+ blink : process (clk_100_osc)
+ begin
+ if rising_edge(clk_100_osc) then
+ if (time_counter = x"FFFFFFFF") then
+ time_counter <= x"00000000";
+ else
+ time_counter <= time_counter + 1;
+ end if;
+ end if;
+ end process;
end trb3_periph_sodasource_arch;
\ No newline at end of file
BLOCK RESETPATHS;
BLOCK ASYNCPATHS;
BLOCK RD_DURING_WR_PATHS ;
+BLOCK JTAGPATHS ;\r
#################################################################
# Clock I/O
#################################################################
<Source name="code/trb3_periph_sodahub.vhd" type="VHDL" type_short="VHDL">
<Options top_module="trb3_periph_sodahub"/>
</Source>
- <Source name="code/trb3_periph_hub.vhd" type="VHDL" type_short="VHDL" excluded="TRUE">
- <Options/>
- </Source>
<Source name="code/soda_hub_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC" excluded="TRUE">
<Options/>
</Source>
<Source name="soda_hub.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
+ <Source name="soda_hub_probe.rvl" type="Reveal" type_short="Reveal">
+ <Options/>
+ </Source>
<Source name="trb3_soda_hub.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
\r
DEFINE PORT GROUP "SFP_group" "SFP*" ;\r
IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
- \r
-#################################################################\r
+#################################################################
# Additional Lines to AddOn\r
#################################################################\r
#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3\r
#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198\r
#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200\r
#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69\r
-#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71\r
-\r
+#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71
#################################################################\r
# Flash ROM and Reboot\r
#################################################################\r
IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;\r
LOCATE COMP "PROGRAMN" SITE "B11" ;\r
IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;\r
-\r
#################################################################\r
# Misc\r
#################################################################\r
IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
#terminated differential pair to pads\r
LOCATE COMP "SUPPL" SITE "C14" ;\r
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;\r
-\r
+#IOBUF PORT "SUPPL" IO_TYPE=LVDS25;
#################################################################\r
# LED\r
#################################################################\r
LOCATE COMP "LED_YELLOW" SITE "A16" ;\r
DEFINE PORT GROUP "LED_group" "LED*" ;\r
IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;\r
-\r
-\r
#################################################################\r
#GSR_NET NET "GSR_N"; \r
#################################################################\r
-rvl_alias "rxup_full_clk" "rxup_full_clk";\r
-BLOCK RESETPATHS ;\r
-BLOCK ASYNCPATHS ;\r
-BLOCK RD_DURING_WR_PATHS ;\r
-BLOCK JTAGPATHS ;\r
-#################################################################\r
-# Basic Settings\r
-#################################################################\r
-SYSCONFIG MCCLK_FREQ = 20;\r
-# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;\r
-# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;\r
-# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;\r
-#################################################################\r
-# Clock I/O\r
-#################################################################\r
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;\r
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;\r
+rvl_alias "rxup_full_clk" "rxup_full_clk";
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+BLOCK JTAGPATHS ;
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???\r
LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;\r
#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";\r
#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";\r
#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!\r
DEFINE PORT GROUP "CLK_group" "*CLK*" ;\r
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;\r
-#################################################################\r
-# To central FPGA\r
-#################################################################\r
-LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;\r
-LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ;\r
-LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ;\r
-LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ;\r
-LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ;\r
-LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ;\r
-LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ;\r
-LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ;\r
-LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ;\r
-LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ;\r
-LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ;\r
-LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ;\r
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;\r
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-LOCATE COMP "TEST_LINE[0]" SITE "A5" ;\r
-LOCATE COMP "TEST_LINE[1]" SITE "A6" ;\r
-LOCATE COMP "TEST_LINE[2]" SITE "G8" ;\r
-LOCATE COMP "TEST_LINE[3]" SITE "F9" ;\r
-LOCATE COMP "TEST_LINE[4]" SITE "D9" ;\r
-LOCATE COMP "TEST_LINE[5]" SITE "D10" ;\r
-LOCATE COMP "TEST_LINE[6]" SITE "F10" ;\r
-LOCATE COMP "TEST_LINE[7]" SITE "E10" ;\r
-LOCATE COMP "TEST_LINE[8]" SITE "A8" ;\r
-LOCATE COMP "TEST_LINE[9]" SITE "B8" ;\r
-LOCATE COMP "TEST_LINE[10]" SITE "G10" ;\r
-LOCATE COMP "TEST_LINE[11]" SITE "G9" ;\r
-LOCATE COMP "TEST_LINE[12]" SITE "C9" ;\r
-LOCATE COMP "TEST_LINE[13]" SITE "C10" ;\r
-LOCATE COMP "TEST_LINE[14]" SITE "H10" ;\r
-LOCATE COMP "TEST_LINE[15]" SITE "H11" ;\r
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;\r
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;\r
-#################################################################\r
-# Connection to AddOn\r
-#################################################################\r
-LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1\r
-LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3\r
-LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5\r
-LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7\r
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
+#################################################################
+# To central FPGA
+#################################################################
+LOCATE COMP "FPGA5_COMM_0" SITE "AD4" ;\r
+LOCATE COMP "FPGA5_COMM_1" SITE "AE3" ;\r
+LOCATE COMP "FPGA5_COMM_2" SITE "AA7" ;\r
+LOCATE COMP "FPGA5_COMM_3" SITE "AB7" ;\r
+LOCATE COMP "FPGA5_COMM_4" SITE "AD3" ;\r
+LOCATE COMP "FPGA5_COMM_5" SITE "AC4" ;\r
+LOCATE COMP "FPGA5_COMM_6" SITE "AE2" ;\r
+LOCATE COMP "FPGA5_COMM_7" SITE "AF3" ;\r
+LOCATE COMP "FPGA5_COMM_8" SITE "AE4" ;\r
+LOCATE COMP "FPGA5_COMM_9" SITE "AF4" ;\r
+LOCATE COMP "FPGA5_COMM_10" SITE "V10" ;\r
+LOCATE COMP "FPGA5_COMM_11" SITE "W10" ;\r
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+\r
+LOCATE COMP "TEST_LINE_0" SITE "A5" ;\r
+LOCATE COMP "TEST_LINE_1" SITE "A6" ;\r
+LOCATE COMP "TEST_LINE_2" SITE "G8" ;\r
+LOCATE COMP "TEST_LINE_3" SITE "F9" ;\r
+LOCATE COMP "TEST_LINE_4" SITE "D9" ;\r
+LOCATE COMP "TEST_LINE_5" SITE "D10" ;\r
+LOCATE COMP "TEST_LINE_6" SITE "F10" ;\r
+LOCATE COMP "TEST_LINE_7" SITE "E10" ;\r
+LOCATE COMP "TEST_LINE_8" SITE "A8" ;\r
+LOCATE COMP "TEST_LINE_9" SITE "B8" ;\r
+LOCATE COMP "TEST_LINE_10" SITE "G10" ;\r
+LOCATE COMP "TEST_LINE_11" SITE "G9" ;\r
+LOCATE COMP "TEST_LINE_12" SITE "C9" ;\r
+LOCATE COMP "TEST_LINE_13" SITE "C10" ;\r
+LOCATE COMP "TEST_LINE_14" SITE "H10" ;\r
+LOCATE COMP "TEST_LINE_15" SITE "H11" ;\r
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
+\r
+#################################################################
+# Connection to AddOn
+#################################################################
+LOCATE COMP "LED_LINKOK_1" SITE "P1" ;#DQLL0_0 #1\r
+LOCATE COMP "LED_RX_1" SITE "P2" ;#DQLL0_1 #3\r
+LOCATE COMP "LED_TX_1" SITE "T2" ;#DQLL0_2 #5\r
+LOCATE COMP "SFP_MOD0_1" SITE "U3" ;#DQLL0_3 #7\r
#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9\r
#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11\r
#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13\r
-LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15\r
-LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17\r
+LOCATE COMP "SFP_TXDIS_1" SITE "P3" ;#DQSLL0_C #15\r
+LOCATE COMP "SFP_LOS_1" SITE "P5" ;#DQLL0_6 #17\r
#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19\r
-LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21\r
-LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23\r
-LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25\r
-LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27\r
+LOCATE COMP "LED_LINKOK_2" SITE "N5" ;#DQLL0_8 #21\r
+LOCATE COMP "LED_RX_2" SITE "N6" ;#DQLL0_9 #23\r
+LOCATE COMP "LED_TX_2" SITE "AC2" ;#DQLL2_0 #25\r
+LOCATE COMP "SFP_MOD0_2" SITE "AC3" ;#DQLL2_1 #27\r
#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29\r
#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31\r
#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33\r
-LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35\r
-LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2\r
+LOCATE COMP "SFP_TXDIS_2" SITE "AA2" ;#DQLL2_5 #35\r
+LOCATE COMP "SFP_LOS_2" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2\r
#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2\r
-LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2\r
-LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4\r
-LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6\r
-LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8\r
+LOCATE COMP "LED_LINKOK_3" SITE "AD1" ;#DQLL3_0 #2\r
+LOCATE COMP "LED_RX_3" SITE "AD2" ;#DQLL3_1 #4\r
+LOCATE COMP "LED_TX_3" SITE "AB5" ;#DQLL3_2 #6\r
+LOCATE COMP "SFP_MOD0_3" SITE "AB6" ;#DQLL3_3 #8\r
#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10\r
#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12\r
#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3\r
-LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3\r
-LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18\r
+LOCATE COMP "SFP_TXDIS_3" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3\r
+LOCATE COMP "SFP_LOS_3" SITE "AA3" ;#DQLL3_6 #18
#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20\r
-LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22\r
-LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24\r
-LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26\r
-LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28\r
+LOCATE COMP "LED_LINKOK_4" SITE "W8" ;#DQLL3_8 #22\r
+LOCATE COMP "LED_RX_4" SITE "W9" ;#DQLL3_9 #24\r
+LOCATE COMP "LED_TX_4" SITE "V1" ;#DQLL1_0 #26\r
+LOCATE COMP "SFP_MOD0_4" SITE "U2" ;#DQLL1_1 #28\r
#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30\r
#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32\r
#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34\r
-LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36\r
-LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38\r
+LOCATE COMP "SFP_TXDIS_4" SITE "R3" ;#DQLL1_5 #36\r
+LOCATE COMP "SFP_LOS_4" SITE "T3" ;#DQSLL1_T #38\r
#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40\r
-LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169\r
-LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171\r
-LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173\r
-LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175\r
+LOCATE COMP "LED_LINKOK_5" SITE "W23" ;#DQLR1_0 #169\r
+LOCATE COMP "LED_RX_5" SITE "W22" ;#DQLR1_1 #171\r
+LOCATE COMP "LED_TX_5" SITE "AA25" ;#DQLR1_2 #173\r
+LOCATE COMP "SFP_MOD0_5" SITE "Y24" ;#DQLR1_3 #175\r
#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177\r
#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179\r
#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181\r
-LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183\r
-LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185\r
+LOCATE COMP "SFP_TXDIS_5" SITE "W20" ;#DQSLR1_C #183\r
+LOCATE COMP "SFP_LOS_5" SITE "AA24" ;#DQLR1_6 #185\r
#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187\r
-LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170\r
-LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172\r
-LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174\r
-LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176\r
+LOCATE COMP "LED_LINKOK_6" SITE "R25" ;#DQLR2_0 #170\r
+LOCATE COMP "LED_RX_6" SITE "R26" ;#DQLR2_1 #172\r
+LOCATE COMP "LED_TX_6" SITE "T25" ;#DQLR2_2 #174\r
+LOCATE COMP "SFP_MOD0_6" SITE "T24" ;#DQLR2_3 #176\r
#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178\r
#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180\r
#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182\r
-LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184\r
-LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186\r
+LOCATE COMP "SFP_TXDIS_6" SITE "V22" ;#DQSLR2_C #184\r
+LOCATE COMP "SFP_LOS_6" SITE "U24" ;#DQLR2_6 #186\r
#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188\r
-DEFINE PORT GROUP "SFP_group" "SFP*" ;\r
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-#################################################################\r
-# Additional Lines to AddOn\r
-#################################################################\r
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3\r
-#all lines are input only\r
-#line 4/5 go to PLL input\r
-#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194\r
-#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196\r
-#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198\r
-#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200\r
-#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69\r
-#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 \r
-#################################################################\r
-# Flash ROM and Reboot\r
-#################################################################\r
-LOCATE COMP "FLASH_CLK" SITE "B12" ;\r
-LOCATE COMP "FLASH_CS" SITE "E11" ;\r
-LOCATE COMP "FLASH_DIN" SITE "E12" ;\r
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;\r
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;\r
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;\r
-LOCATE COMP "PROGRAMN" SITE "B11" ;\r
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;\r
-#################################################################\r
-# Misc\r
-#################################################################\r
-LOCATE COMP "TEMPSENS" SITE "A13" ;\r
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;\r
-#coding of FPGA number\r
-LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;\r
-LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;\r
-IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-#terminated differential pair to pads\r
-LOCATE COMP "SUPPL" SITE "C14" ;\r
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;\r
-#################################################################\r
-# LED\r
-#################################################################\r
-LOCATE COMP "LED_GREEN" SITE "F12" ;\r
-LOCATE COMP "LED_ORANGE" SITE "G13" ;\r
-LOCATE COMP "LED_RED" SITE "A15" ;\r
-LOCATE COMP "LED_YELLOW" SITE "A16" ;\r
-DEFINE PORT GROUP "LED_group" "LED*" ;\r
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;\r
-\r
-\r
-#################################################################\r
-#GSR_NET NET "GSR_N"; \r
-#################################################################\r
-# Locate Serdes and media interfaces\r
-#################################################################\r
-LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;\r
-LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;\r
\r
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;\r
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;\r
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;\r
-MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;\r
-#MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/wa_pos*" 20.000000 ns ; # to debug only\r
-MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/SCI_DATA_OUT*" 20.000000 ns ;\r
-MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;\r
-MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;\r
+DEFINE PORT GROUP "SFP_group" "SFP*" ;
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+#################################################################
+# Additional Lines to AddOn
+#################################################################
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
+#all lines are input only
+#line 4/5 go to PLL input
+#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
+#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
+#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
+#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
+#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
+#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+LOCATE COMP "FLASH_CLK" SITE "B12" ;
+LOCATE COMP "FLASH_CS" SITE "E11" ;
+LOCATE COMP "FLASH_DIN" SITE "E12" ;
+LOCATE COMP "FLASH_DOUT" SITE "A12" ;
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
+LOCATE COMP "PROGRAMN" SITE "B11" ;
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP "TEMPSENS" SITE "A13" ;
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+#coding of FPGA number
+LOCATE COMP "CODE_LINE_1" SITE "AA20" ;\r
+LOCATE COMP "CODE_LINE_0" SITE "Y21" ;\r
+IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
+IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
+#terminated differential pair to pads
+LOCATE COMP "SUPPL" SITE "C14" ;
+#IOBUF PORT "SUPPL" IO_TYPE=LVDS25;
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_GREEN" SITE "F12" ;
+LOCATE COMP "LED_ORANGE" SITE "G13" ;
+LOCATE COMP "LED_RED" SITE "A15" ;
+LOCATE COMP "LED_YELLOW" SITE "A16" ;
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
+#################################################################
+#GSR_NET NET "GSR_N";
+#################################################################
+# Locate Serdes and media interfaces
+#################################################################
+LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
+
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;
+MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;
+#MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/wa_pos*" 20.000000 ns ; # to debug only
+MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/SCI_DATA_OUT*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;
+MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;
#MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/wa_pos*" 20.000000 ns ; # to debug only\r
#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;\r
-MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;\r
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ;\r
-\r
-BLOCK PATH FROM CLKNET "clk_100_osc_c" TO CLKNET "THE_HUB_SYNC_DOWNLINK/sci_write_i" ;\r
-BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_read_*";\r
-BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_write_*";\r
-\r
+MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ;
+
+BLOCK PATH FROM CLKNET "clk_100_osc_c" TO CLKNET "THE_HUB_SYNC_DOWNLINK/sci_write_i" ;
+BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_read_*";
+BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_write_*";
+
#UGROUP "SPIlogic" BBOX 20 20\r
# BLKNAME THE_SPI_RELOAD;\r
#LOCATE UGROUP "SPIlogic" SITE "R10C150D" ;\r
\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[0]";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[1]";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[2]";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[3]";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[0]";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[1]";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[2]";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[3]";\r
-\r
-## IOBUF ALLPORTS ;\r
-USE PRIMARY NET "clk_200_osc" ;\r
-USE PRIMARY NET "clk_100_osc" ;\r
-USE PRIMARY NET "rxup_full_clk" ;\r
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;\r
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;\r
-FREQUENCY NET "rxup_full_clk" 200.000000 MHz ;\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_0";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_1";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_2";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_3";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_0";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_1";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_2";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_3";\r
+
+## IOBUF ALLPORTS ;
+USE PRIMARY NET "clk_200_osc" ;
+USE PRIMARY NET "clk_100_osc" ;
+FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
+FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
+FREQUENCY NET "rxup_full_clk" 200.000000 MHz ;
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2015-01-20">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2015-03-04">
<IP Version="1_5_062609"/>
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_hub"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2087239949" Name="trb3_periph_sodahub_LA0" ID="0">
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2093545897" Name="trb3_periph_sodahub_LA0" ID="0">
<Setting>
<Clock SampleClk="rxup_full_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="64"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_hub_LA0_net"/>
+ <DistRAM Disable="0"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Type="SIG" Name="the_hub_sync_uplink/got_link_ready_i"/>
- <Sig Type="SIG" Name="downlink_clear"/>
- <Sig Type="SIG" Name="downlink_reset"/>
- <Bus Name="dnlink_phase_s">
- <Sig Type="SIG" Name="dnlink_phase_s:0"/>
- <Sig Type="SIG" Name="dnlink_phase_s:1"/>
- <Sig Type="SIG" Name="dnlink_phase_s:2"/>
- <Sig Type="SIG" Name="dnlink_phase_s:3"/>
- </Bus>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_k"/>
<Bus Name="the_hub_sync_uplink/rx_data">
<Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:0"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:1"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:6"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:7"/>
</Bus>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_k"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm"/>
+ <Bus Name="the_hub_sync_uplink/rx_dlm_word">
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:7"/>
+ </Bus>
+ <Bus Name="the_hub_sync_uplink/rx_fsm_state">
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:3"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_k"/>
<Bus Name="the_hub_sync_uplink/tx_data">
<Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:0"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:1"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:6"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:7"/>
</Bus>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_k"/>
- <Bus Name="med_ctrl_op">
- <Sig Type="SIG" Name="med_ctrl_op:15"/>
- <Sig Type="SIG" Name="med_ctrl_op:31"/>
- <Sig Type="SIG" Name="med_ctrl_op:47"/>
- <Sig Type="SIG" Name="med_ctrl_op:63"/>
- <Sig Type="SIG" Name="med_ctrl_op:79"/>
- <Sig Type="SIG" Name="med_ctrl_op:95"/>
- <Sig Type="SIG" Name="med_ctrl_op:111"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/send_link_reset_i">
- <Sig Type="SIG" Name="the_hub_sync_downlink/send_link_reset_i:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/send_link_reset_i:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/send_link_reset_i:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/send_link_reset_i:3"/>
- </Bus>
- <Sig Type="SIG" Name="the_hub_sync_downlink/ctrl_op:15"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/ctrl_op:31"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/ctrl_op:47"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/ctrl_op:63"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/stat_op:15"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/stat_op:31"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/stat_op:47"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/stat_op:63"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/send_link_reset_i"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(1)\/the_rx_control/send_link_reset_i"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(2)\/the_rx_control/send_link_reset_i"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(3)\/the_rx_control/send_link_reset_i"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/send_link_reset_out"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(1)\/the_rx_control/send_link_reset_out"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(2)\/the_rx_control/send_link_reset_out"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(3)\/the_rx_control/send_link_reset_out"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/send_link_reset_in"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(1)\/the_tx/send_link_reset_in"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(2)\/the_tx/send_link_reset_in"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(3)\/the_tx/send_link_reset_in"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/send_link_reset_i"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/ctrl_op:15"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/stat_op:15"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_control/send_link_reset_i"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_control/send_link_reset_out"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/the_tx/send_link_reset_in"/>
- <Bus Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_state">
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_state:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_state:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_state:2"/>
- </Bus>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_k_in"/>
- <Bus Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in">
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:7"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_state_bits">
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_state_bits:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_state_bits:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_state_bits:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_state_bits:3"/>
- </Bus>
- <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_allow_in"/>
- <Bus Name="the_hub_sync_downlink/rx_allow">
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_allow:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_allow:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_allow:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_allow:3"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/tx_allow">
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_allow:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_allow:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_allow:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_allow:3"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/got_link_ready_i">
- <Sig Type="SIG" Name="the_hub_sync_downlink/got_link_ready_i:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/got_link_ready_i:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/got_link_ready_i:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/got_link_ready_i:3"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/rx_allow_q">
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_allow_q:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_allow_q:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_allow_q:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_allow_q:3"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/tx_allow_q">
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_allow_q:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_allow_q:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_allow_q:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_allow_q:3"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/rx_data[3:0]">
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:7"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/rx_k">
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:3"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/tx_data[3:0]">
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:7"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/tx_k">
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:3"/>
- </Bus>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_preview_in"/>
+ <Bus Name="the_hub_sync_uplink/tx_dlm_word">
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:7"/>
+ </Bus>
+ <Bus Name="the_hub_sync_uplink/tx_fsm_state">
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:3"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/sd_los_in"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/sd_txdis_out"/>
+ <Bus Name="the_hub_sync_uplink/wa_position_rx">
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:8"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:9"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:10"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:11"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:12"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:13"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:14"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:15"/>
+ </Bus>
+ <Bus Name="the_hub_sync_uplink/wa_position">
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:8"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:9"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:10"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:11"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:12"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:13"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:14"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:15"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_pll_lol"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/tx_pcs_rst"/>
+ <Bus Name="sfp_los">
+ <Sig Type="SIG" Name="sfp_los:1"/>
+ <Sig Type="SIG" Name="sfp_los:2"/>
+ <Sig Type="SIG" Name="sfp_los:3"/>
+ <Sig Type="SIG" Name="sfp_los:4"/>
+ <Sig Type="SIG" Name="sfp_los:5"/>
+ <Sig Type="SIG" Name="sfp_los:6"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/rst_n"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/rx_cdr_lol_ch_s"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/rx_los_low_ch_s"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/rx_pcs_rst_ch_c"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/rx_serdes_rst_ch_c"/>
+ <Bus Name="the_hub_sync_uplink/the_rx_fsm/state_out">
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/state_out:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/state_out:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/state_out:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/state_out:3"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/tx_pll_lol_qd_s"/>
+ <Bus Name="the_hub_sync_uplink/the_rx_fsm/wa_position">
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/wa_position:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/wa_position:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/wa_position:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/wa_position:3"/>
+ </Bus>
+ <Bus Name="the_hub_sync_uplink/the_rx_fsm/cs">
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/cs:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/cs:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/cs:2"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/the_rx_fsm/timer2"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/clear"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/internal_make_link_reset_out"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/sd_los_i"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/watchdog_trigger"/>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="a_soda_hub/start_of_superburst_s,"/>
<TU Serialbits="0" Type="0" ID="2" Sig="a_soda_hub/soda_cmd_valid_s,"/>
<TU Serialbits="0" Type="0" ID="3" Sig="the_hub_sync_uplink/watchdog_trigger,"/>
- <TU Serialbits="0" Type="0" ID="4" Sig="med_stat_op:13,"/>
- <TU Serialbits="0" Type="0" ID="5" Sig="the_hub_sync_uplink/the_tx/send_link_reset_in,"/>
- <TU Serialbits="0" Type="0" ID="6" Sig="the_hub_sync_downlink/\generated_logic(0)\/the_tx/send_link_reset_in,"/>
+ <TU Serialbits="0" Type="0" ID="4" Sig="the_hub_sync_uplink/the_rx_fsm/reset_timer2,"/>
+ <TU Serialbits="0" Type="0" ID="5" Sig="(BUS)the_hub_sync_uplink/the_rx_fsm/state_out[3:0],"/>
<TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="5" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="6" Resource="0"/>
</Trigger>
</Dataset>
</Core>
<Source name="code/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="code/soda_start_of_burst_control.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_clockscaler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="code/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="code/med_ecp3_sfp_sync_down.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="code/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
<Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="code/trb3_periph_sodasource.vhd" type="VHDL" type_short="VHDL">
<Options top_module="trb3_periph_sodasource"/>
</Source>
- <Source name="code/soda_clockscaler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
<Source name="code/soda_source_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC">
<Options/>
</Source>
-rvl_alias "clk_raw_internal" "clk_raw_internal";
+rvl_alias "clk_100_osc" "clk_100_osc";
RVL_ALIAS "clk_raw_internal" "clk_raw_internal";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
BLOCK RD_DURING_WR_PATHS ;
#################################################################
-# Basic Settings
-#################################################################
-# SYSCONFIG MCCLK_FREQ = 2.5;
-# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
-# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
-#################################################################
# Clock I/O
#################################################################
LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
DEFINE PORT GROUP "CLK_group" "*CLK*" ;
IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
#################################################################
-# Trigger I/O
-#################################################################
-#Trigger from fan-out
-#LOCATE COMP "TRIGGER_LEFT" SITE "V3";
-#LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
-#IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
-#IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
-#################################################################
# To central FPGA
#################################################################
LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;
# Basic Settings
#################################################################
SYSCONFIG MCCLK_FREQ=20 ;
-# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
-# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
-#################################################################
-# Reset Nets
-#################################################################
-#GSR_NET NET "GSR_N";
#################################################################
# Locate Serdes and media interfaces
#################################################################
REGION "SPI_REGION" "R10C150D" 15 16 DEVSIZE;
LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "SPI_REGION" ;
LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "SPI_REGION" ;
-
#LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK_REGION" ;
#LOCATE UGROUP "THE_SYNC_LINK/media_downlink_group" REGION "MEDIA_DOWNLINK_REGION" ;
#USE SECONDARY NET "THE_MEDIA_UPLINK/rx_clock_half_c" "MEDIA_DOWNLINK_REGION" ;
MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 25.000000 ns ;
MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ;
+MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
BLOCK JTAGPATHS ;
## IOBUF ALLPORTS ;
#USE PRIMARY PURE NET "CLK_PCLK_LEFT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
#USE PRIMARY PURE NET "CLK_GPLL_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
-#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" 200.000000 MHz ;
-#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" 100.000000 MHz ;
-#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.tx_full_clk_ch0" 200.000000 MHz ;
-#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.tx_half_clk_ch0" 100.000000 MHz ;
-#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.tx_full_clk_ch0" ;
-#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.tx_half_clk_ch0" ;
-#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" ;
-#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" ;
-USE PRIMARY NET "THE_SYNC_LINK/CLK_RX_FULL_OUT_c" ;
-USE PRIMARY NET "clk_sys_internal_c" ;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
+FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
+FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_source_probe.rvl" Date="2015-02-10">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_source_probe.rvl" Date="2015-03-03">
<IP Version="1_5_062609"/>
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_source"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2090132937" Name="trb3_periph_sodasource_LA0" ID="0">
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2093419085" Name="trb3_periph_sodasource_LA0" ID="0">
<Setting>
- <Clock SampleClk="clk_200_osc" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
+ <Clock SampleClk="clk_100_osc" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="128"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
</Setting>
<Dataset Name="Base">
<Trace>
- <Bus Name="the_soda_source/soda_cmd_word_s">
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:0"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:1"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:2"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:3"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:4"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:5"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:6"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:7"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:8"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:9"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:10"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:11"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:12"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:13"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:14"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:15"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:16"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:17"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:18"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:19"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:20"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:21"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:22"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:23"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:24"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:25"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:26"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:27"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:28"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:29"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:30"/>
+ <Bus Name="the_media_uplink/the_sfp_lsm/current_state">
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/current_state:0"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/current_state:1"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/current_state:2"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/current_state:3"/>
</Bus>
- <Bus Name="the_soda_source/super_burst_nr_s">
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:0"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:1"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:2"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:3"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:4"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:5"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:6"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:7"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:8"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:9"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:10"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:11"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:12"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:13"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:14"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:15"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:16"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:17"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:18"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:19"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:20"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:21"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:22"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:23"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:24"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:25"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:26"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:27"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:28"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:29"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:30"/>
+ <Bus Name="the_media_uplink/the_sfp_lsm/next_state">
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/next_state:0"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/next_state:1"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/next_state:2"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/next_state:3"/>
</Bus>
- <Bus Name="the_sync_link/rx_data">
- <Sig Type="SIG" Name="the_sync_link/rx_data:0"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:1"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:2"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:3"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:4"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:5"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:6"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:7"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/next_rx_allow"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/rx_allow_out"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/next_tx_allow"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/tx_allow_out"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/next_lane_rst"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/lane_reset_out"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/next_rst_tctr"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/rst_tctr"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/next_rst_cctr"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/rst_cctr"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/sfp_los_in"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/sfp_missing_in"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/link_status_led"/>
+ <Bus Name="the_media_uplink/the_sfp_lsm/stat_op">
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/stat_op:0"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/stat_op:1"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/stat_op:2"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/stat_op:3"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/stat_op:4"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/stat_op:5"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/stat_op:6"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/stat_op:7"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/stat_op:8"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/stat_op:9"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/stat_op:10"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/stat_op:11"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/stat_op:12"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/stat_op:13"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/stat_op:14"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/stat_op:15"/>
</Bus>
- <Sig Type="SIG" Name="the_sync_link/rx_k"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm"/>
- <Bus Name="the_sync_link/rx_dlm_word">
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:0"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:1"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:2"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:3"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:4"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:5"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:6"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:7"/>
+ <Bus Name="the_media_uplink/the_sfp_lsm/state_bits">
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/state_bits:0"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/state_bits:1"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/state_bits:2"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/state_bits:3"/>
</Bus>
- <Bus Name="the_sync_link/tx_data">
- <Sig Type="SIG" Name="the_sync_link/tx_data:0"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:1"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:2"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:3"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:4"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:5"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:6"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:7"/>
+ <Sig Type="SIG" Name="the_media_uplink/the_sfp_lsm/swap_bytes_out"/>
+ <Bus Name="the_media_uplink/link_error">
+ <Sig Type="SIG" Name="the_media_uplink/link_error:0"/>
+ <Sig Type="SIG" Name="the_media_uplink/link_error:1"/>
+ <Sig Type="SIG" Name="the_media_uplink/link_error:2"/>
+ <Sig Type="SIG" Name="the_media_uplink/link_error:3"/>
+ <Sig Type="SIG" Name="the_media_uplink/link_error:4"/>
+ <Sig Type="SIG" Name="the_media_uplink/link_error:5"/>
+ <Sig Type="SIG" Name="the_media_uplink/link_error:6"/>
+ <Sig Type="SIG" Name="the_media_uplink/link_error:7"/>
+ <Sig Type="SIG" Name="the_media_uplink/link_error:8"/>
</Bus>
- <Sig Type="SIG" Name="the_sync_link/tx_k"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm"/>
- <Bus Name="the_sync_link/tx_dlm_word">
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:0"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:1"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:2"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:3"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:4"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:5"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:6"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:7"/>
+ <Bus Name="the_media_uplink/link_ok">
+ <Sig Type="SIG" Name="the_media_uplink/link_ok:0"/>
</Bus>
- <Bus Name="the_soda_source/src_reply_handler/expected_reply_in">
- <Sig Type="SIG" Name="the_soda_source/src_reply_handler/expected_reply_in:0"/>
- <Sig Type="SIG" Name="the_soda_source/src_reply_handler/expected_reply_in:1"/>
- <Sig Type="SIG" Name="the_soda_source/src_reply_handler/expected_reply_in:2"/>
- <Sig Type="SIG" Name="the_soda_source/src_reply_handler/expected_reply_in:3"/>
- <Sig Type="SIG" Name="the_soda_source/src_reply_handler/expected_reply_in:4"/>
- <Sig Type="SIG" Name="the_soda_source/src_reply_handler/expected_reply_in:5"/>
- <Sig Type="SIG" Name="the_soda_source/src_reply_handler/expected_reply_in:6"/>
- <Sig Type="SIG" Name="the_soda_source/src_reply_handler/expected_reply_in:7"/>
+ <Sig Type="SIG" Name="the_media_uplink/pwr_up"/>
+ <Sig Type="SIG" Name="the_media_uplink/quad_rst"/>
+ <Sig Type="SIG" Name="the_media_uplink/reset"/>
+ <Bus Name="the_media_uplink/rx_k">
+ <Sig Type="SIG" Name="the_media_uplink/rx_k:0"/>
+ <Sig Type="SIG" Name="the_media_uplink/rx_k:1"/>
</Bus>
- <Sig Type="SIG" Name="the_soda_source/src_reply_handler/reply_ok_out"/>
- <Sig Type="SIG" Name="the_soda_source/src_reply_handler/reply_valid_out"/>
+ <Bus Name="the_media_uplink/rx_data">
+ <Sig Type="SIG" Name="the_media_uplink/rx_data:0"/>
+ <Sig Type="SIG" Name="the_media_uplink/rx_data:1"/>
+ <Sig Type="SIG" Name="the_media_uplink/rx_data:2"/>
+ <Sig Type="SIG" Name="the_media_uplink/rx_data:3"/>
+ <Sig Type="SIG" Name="the_media_uplink/rx_data:4"/>
+ <Sig Type="SIG" Name="the_media_uplink/rx_data:5"/>
+ <Sig Type="SIG" Name="the_media_uplink/rx_data:6"/>
+ <Sig Type="SIG" Name="the_media_uplink/rx_data:7"/>
+ <Sig Type="SIG" Name="the_media_uplink/rx_data:8"/>
+ <Sig Type="SIG" Name="the_media_uplink/rx_data:9"/>
+ <Sig Type="SIG" Name="the_media_uplink/rx_data:10"/>
+ <Sig Type="SIG" Name="the_media_uplink/rx_data:11"/>
+ <Sig Type="SIG" Name="the_media_uplink/rx_data:12"/>
+ <Sig Type="SIG" Name="the_media_uplink/rx_data:13"/>
+ <Sig Type="SIG" Name="the_media_uplink/rx_data:14"/>
+ <Sig Type="SIG" Name="the_media_uplink/rx_data:15"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_media_uplink/rx_led"/>
+ <Bus Name="the_media_uplink/tx_k">
+ <Sig Type="SIG" Name="the_media_uplink/tx_k:0"/>
+ <Sig Type="SIG" Name="the_media_uplink/tx_k:1"/>
+ </Bus>
+ <Bus Name="the_media_uplink/tx_data">
+ <Sig Type="SIG" Name="the_media_uplink/tx_data:0"/>
+ <Sig Type="SIG" Name="the_media_uplink/tx_data:1"/>
+ <Sig Type="SIG" Name="the_media_uplink/tx_data:2"/>
+ <Sig Type="SIG" Name="the_media_uplink/tx_data:3"/>
+ <Sig Type="SIG" Name="the_media_uplink/tx_data:4"/>
+ <Sig Type="SIG" Name="the_media_uplink/tx_data:5"/>
+ <Sig Type="SIG" Name="the_media_uplink/tx_data:6"/>
+ <Sig Type="SIG" Name="the_media_uplink/tx_data:7"/>
+ <Sig Type="SIG" Name="the_media_uplink/tx_data:8"/>
+ <Sig Type="SIG" Name="the_media_uplink/tx_data:9"/>
+ <Sig Type="SIG" Name="the_media_uplink/tx_data:10"/>
+ <Sig Type="SIG" Name="the_media_uplink/tx_data:11"/>
+ <Sig Type="SIG" Name="the_media_uplink/tx_data:12"/>
+ <Sig Type="SIG" Name="the_media_uplink/tx_data:13"/>
+ <Sig Type="SIG" Name="the_media_uplink/tx_data:14"/>
+ <Sig Type="SIG" Name="the_media_uplink/tx_data:15"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_media_uplink/tx_led"/>
</Trace>
<Trigger>
- <TU Serialbits="0" Type="0" ID="1" Sig="the_soda_source/soda_cmd_strobe_s,"/>
- <TU Serialbits="0" Type="0" ID="2" Sig="the_soda_source/start_of_superburst_s,"/>
- <TU Serialbits="0" Type="0" ID="3" Sig="the_soda_source/start_calibration_s,"/>
- <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
+ <TU Serialbits="0" Type="0" ID="1" Sig="(BUS)the_media_uplink/link_ok[0:0],"/>
+ <TU Serialbits="0" Type="0" ID="2" Sig="(BUS)the_media_uplink/the_sfp_lsm/state_bits[3:0],"/>
+ <TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
</Trigger>
</Dataset>
</Core>
<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
-<ispXCF version="3.3.0">
+<ispXCF version="3.4.0">
<Comment></Comment>
<Chain>
<Comm>JTAG</Comm>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodahub_20150120.bit</File>
- <FileTime>01/20/15 10:28:57</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodahub_20150304.bit</File>
+ <FileTime>03/04/15 14:53:50</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
</Option>
</Device>
<Device>
- <SelectedProg value="TRUE"/>
+ <SelectedProg value="FALSE"/>
<Pos>4</Pos>
<Vendor>Lattice</Vendor>
<Family>LatticeECP3</Family>
</Bypass>
<File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20150113.bit</File>
<FileTime>01/13/15 10:01:17</FileTime>
+ <JedecChecksum>N/A</JedecChecksum>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
</Option>
</Device>
<Device>
- <SelectedProg value="TRUE"/>
+ <SelectedProg value="FALSE"/>
<Pos>5</Pos>
<Vendor>Lattice</Vendor>
<Family>LatticeECP3</Family>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20141126.bit</File>
- <FileTime>11/25/14 14:12:00</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20150303.bit</File>
+ <FileTime>03/03/15 17:13:40</FileTime>
+ <JedecChecksum>N/A</JedecChecksum>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
</Option>
</Device>
<Device>
- <SelectedProg value="TRUE"/>
+ <SelectedProg value="FALSE"/>
<Pos>6</Pos>
<Vendor>Lattice</Vendor>
<Family>ispCLOCK</Family>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
+ <File>/local/lemmens/lattice/trb3/base/clockmanager/CM2.jed</File>
+ <FileTime>04/10/13 09:35:41</FileTime>
+ <JedecChecksum>0x18FB</JedecChecksum>
<Operation>Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
+ <PreloadLength>32</PreloadLength>
+ <IOVectorData>0x00000000</IOVectorData>
<OverideUES value="TRUE"/>
<TCKFrequency>1.000000 MHz</TCKFrequency>
<SVFProcessor>ispVM</SVFProcessor>
+ <Usercode>0xFFFFFFFF</Usercode>
<AccessMode>JTAG</AccessMode>
</Option>
</Device>
jspc29 / soda.git / commitdiff