set Trbnet Bridge Port to stream port. Reorder data in xilinx fifo wrapper to match...

diff --git a/src/DCA_cores/xcku/fifo_2kx34x17_wcnt.vhd b/src/DCA_cores/xcku/fifo_2kx34x17_wcnt.vhd
index a3388e2778263df835490d046177039987956c68..66e819e86c8f260265a525ec06ac179d271051c5 100644 (file)
--- a/src/DCA_cores/xcku/fifo_2kx34x17_wcnt.vhd
+++ b/src/DCA_cores/xcku/fifo_2kx34x17_wcnt.vhd
@@ -36,13 +36,14 @@ architecture structural of fifo_2kx34x17_wcnt is
     end component;
 
     signal full_i : std_logic;
+    signal din_sort : std_logic_vector(33 downto 0);
 begin
     fifo : fifo_2kx34x17_wcnt_xcku
     port map (
         rst           => Reset,
         wr_clk        => WrClock,
         rd_clk        => RdClock,
-        din           => Data,
+        din           => din_sort,
         wr_en         => WrEn,
         rd_en         => RdEn,
         dout          => Q,
@@ -55,4 +56,5 @@ begin
 
     WCNT(11) <= full_i;
     Full <= full_i;
+    din_sort <= Data(16 downto 0) & Data(33 downto 17);
 end architecture structural;

diff --git a/src/DCA_cores/xcku/fifo_4kx16x32_wcnt.vhd b/src/DCA_cores/xcku/fifo_4kx16x32_wcnt.vhd
index 460b31842a6b15216a5302b1ca0c00827de263f2..e1dec08268fa81d721b166372cd41790b67bda52 100644 (file)
--- a/src/DCA_cores/xcku/fifo_4kx16x32_wcnt.vhd
+++ b/src/DCA_cores/xcku/fifo_4kx16x32_wcnt.vhd
@@ -39,18 +39,19 @@ architecture structural of fifo_4kx16x32_wcnt is
 begin
     fifo : fifo_4kx16x32_wcnt_xcku
     port map (
-        rst           => Reset,
-        wr_clk        => WrClock,
-        rd_clk        => RdClock,
-        din           => Data,
-        wr_en         => WrEn,
-        rd_en         => RdEn,
-        dout          => Q,
-        full          => full_i,
-        empty         => Empty,
-        wr_data_count => WCNT(10 downto 0),
-        wr_rst_busy   => open,
-        rd_rst_busy   => open
+        rst                => Reset,
+        wr_clk             => WrClock,
+        rd_clk             => RdClock,
+        din                => Data,
+        wr_en              => WrEn,
+        rd_en              => RdEn,
+        dout(15 downto  0) => Q(31 downto 16),
+        dout(31 downto 16) => Q(15 downto  0),
+        full               => full_i,
+        empty              => Empty,
+        wr_data_count      => WCNT(10 downto 0),
+        wr_rst_busy        => open,
+        rd_rst_busy        => open
     );
 
     WCNT(11) <= full_i;

diff --git a/src/DCA_cores/xcku/fifo_64kx16x32_wcnt.vhd b/src/DCA_cores/xcku/fifo_64kx16x32_wcnt.vhd
index e07874d75e3bdf2b7c30b3dd5d943ab34f4a7dff..e0bdb9eeee93a60c660aa68004d8a36df64bb5d9 100644 (file)
--- a/src/DCA_cores/xcku/fifo_64kx16x32_wcnt.vhd
+++ b/src/DCA_cores/xcku/fifo_64kx16x32_wcnt.vhd
@@ -39,18 +39,19 @@ architecture structural of fifo_64kx16x32_wcnt is
 begin
     fifo : fifo_64kx16x32_wcnt_xcku
     port map (
-        rst           => Reset,
-        wr_clk        => WrClock,
-        rd_clk        => RdClock,
-        din           => Data,
-        wr_en         => WrEn,
-        rd_en         => RdEn,
-        dout          => Q,
-        full          => full_i,
-        empty         => Empty,
-        wr_data_count => WCNT(14 downto 0),
-        wr_rst_busy   => open,
-        rd_rst_busy   => open
+        rst                => Reset,
+        wr_clk             => WrClock,
+        rd_clk             => RdClock,
+        din                => Data,
+        wr_en              => WrEn,
+        rd_en              => RdEn,
+        dout(15 downto  0) => Q(31 downto 16),
+        dout(31 downto 16) => Q(15 downto  0),
+        full               => full_i,
+        empty              => Empty,
+        wr_data_count      => WCNT(14 downto 0),
+        wr_rst_busy        => open,
+        rd_rst_busy        => open
     );
 
     WCNT(15) <= full_i;

diff --git a/src/hub/trb_net16_cri_hub.vhd b/src/hub/trb_net16_cri_hub.vhd
index 0003ddfbb2b0e436c70f122d4729684d2cf099c7..e4f0081d18ffc59343b990f0aaf5e17c6da17682 100644 (file)
--- a/src/hub/trb_net16_cri_hub.vhd
+++ b/src/hub/trb_net16_cri_hub.vhd
@@ -303,7 +303,8 @@ begin
       HUB_STAT_GEN                    => buf_HUB_STAT_GEN,
       
       MPLEX_CTRL                      => (others => '0'),
-      CTRL_DEBUG                      => (others => '0'),
+      CTRL_DEBUG( 2 downto 0)         => "111",
+      CTRL_DEBUG(31 downto 3)         => (others => '0'),
       STAT_DEBUG                      => open,
       
       BUS_HUB_DBG_RX                  => bus_hub_dbg_0_rx,