--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
+-- Module Version: 5.3
+--/d/jspc29/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -n oddr -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode out -io_type LVDS25 -width 1 -freq_in 200 -gear 1 -clk sclk -aligned -e
+
+-- Thu Mar 14 19:42:41 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity oddr is
+ port (
+ clk: in std_logic;
+ clkout: out std_logic;
+ da: in std_logic_vector(0 downto 0);
+ db: in std_logic_vector(0 downto 0);
+ q: out std_logic_vector(0 downto 0));
+ attribute dont_touch : boolean;
+ attribute dont_touch of oddr : entity is true;
+end oddr;
+
+architecture Structure of oddr is
+
+ -- internal signal declarations
+ signal buf_clkout: std_logic;
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+ signal clkos: std_logic;
+ signal clkop: std_logic;
+ signal buf_qo0: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component OB
+ port (I: in std_logic; O: out std_logic);
+ end component;
+ component ODDRXD1
+ port (DA: in std_logic; DB: in std_logic; SCLK: in std_logic;
+ Q: out std_logic);
+ end component;
+ attribute ODDRAPPS : string;
+ attribute IO_TYPE : string;
+ attribute IO_TYPE of Inst3_OB : label is "LVDS25";
+ attribute ODDRAPPS of Inst_ODDRXD1_0_0 : label is "SCLK_ALIGNED";
+ attribute ODDRAPPS of Inst2_ODDRXD1 : label is "SCLK_ALIGNED";
+ attribute IO_TYPE of Inst1_OB0 : label is "LVDS25";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+
+begin
+ -- component instantiation statements
+ Inst3_OB: OB
+ port map (I=>buf_clkout, O=>clkout);
+
+ Inst_ODDRXD1_0_0: ODDRXD1
+ port map (DA=>da(0), DB=>db(0), SCLK=>clkop, Q=>buf_qo0);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ Inst2_ODDRXD1: ODDRXD1
+ port map (DA=>scuba_vhi, DB=>scuba_vlo, SCLK=>clkos,
+ Q=>buf_clkout);
+
+ Inst1_OB0: OB
+ port map (I=>buf_qo0, O=>q(0));
+
+ clkos <= clk;
+ clkop <= clk;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of oddr is
+ for Structure
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:OB use entity ecp3.OB(V); end for;
+ for all:ODDRXD1 use entity ecp3.ODDRXD1(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
+-- Module Version: 5.3
+--/d/jspc29/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -n pll_in100_out80 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 80 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e
+
+-- Thu Mar 14 20:17:20 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_in100_out80 is
+ port (
+ CLK: in std_logic;
+ CLKOP: out std_logic;
+ LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_in100_out80 : entity is true;
+end pll_in100_out80;
+
+architecture Structure of pll_in100_out80 is
+
+ -- internal signal declarations
+ signal CLKOP_t: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component EHXPLLF
+ generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
+ DELAY_PWD : in String; DELAY_VAL : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ PHASE_DELAY_CNTL : in String; DUTY : in Integer;
+ PHASEADJ : in String; CLKOK_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; FIN : in String);
+ port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
+ RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
+ DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
+ FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
+ LOCK: out std_logic; CLKINTFB: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "80.000000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLF
+ generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
+ CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 2, CLKI_DIV=> 5,
+ FIN=> "200.000000")
+ port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
+ RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
+ FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
+ CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
+ CLKINTFB=>open);
+
+ CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_in100_out80 is
+ for Structure
+ for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
jspc29 / trb3.git / commitdiff