added LCD to pulser design

diff --git a/pulser/padiwa_pulser.prj b/pulser/padiwa_pulser.prj
index 1a067692158956d97da2dbe1cccb74248c94e6d7..dbb7ab156dceacdcefb88ed2b9fd3e5ae0348ed0 100644 (file)
--- a/pulser/padiwa_pulser.prj
+++ b/pulser/padiwa_pulser.prj
@@ -1,28 +1,31 @@
 
 #project files
-add_file -vhdl -lib work "/d/jspc29/lattice/diamond/2.2_x64/cae_library/synthesis/vhdl/machxo2.vhd"
+add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.0_x64/cae_library/synthesis/vhdl/machxo2.vhd"
 
+add_file -vhdl -lib work "version.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib work "../source/spi_slave.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "../source/pwm.vhd"
-add_file -vhdl -lib work "../cores/pll_shifted_clocks.vhd"
-add_file -vhdl -lib work "../cores/fifo_1kx8.vhd"
-add_file -vhdl -lib work "../source/ffarray.vhd"
+
+#add_file -vhdl -lib work "../source/spi_slave.vhd"
+#add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+#add_file -vhdl -lib work "../source/pwm.vhd"
+#add_file -vhdl -lib work "../cores/pll_shifted_clocks.vhd"
+#add_file -vhdl -lib work "../cores/fifo_1kx8.vhd"
+#add_file -vhdl -lib work "../source/ffarray.vhd"
+
 add_file -vhdl -lib work "../source/uart_rec.vhd"
 add_file -vhdl -lib work "../source/uart_trans.vhd"
 add_file -vhdl -lib work "../source/uart_sctrl.vhd"
 
+add_file -vhdl -lib work "../source/lcd.vhd"
 
-
-add_file -vhdl -lib work "../cores/oddr16.vhd"
-add_file -vhdl -lib work "../cores/flash.vhd"
-add_file -vhdl -lib work "../cores/flashram.vhd"
 add_file -vhdl -lib work "../cores/pll.vhd"
-add_file -verilog -lib work "../cores/efb_define_def.v"
-add_file -verilog -lib work "../cores/UFM_WB.v"
+
+#add_file -vhdl -lib work "../cores/oddr16.vhd"
+#add_file -vhdl -lib work "../cores/flash.vhd"
+#add_file -vhdl -lib work "../cores/flashram.vhd"
+#add_file -verilog -lib work "../cores/efb_define_def.v"
+#add_file -verilog -lib work "../cores/UFM_WB.v"
 
 
 add_file -vhdl -lib work "padiwa_pulser.vhd"

diff --git a/pulser/padiwa_pulser.vhd b/pulser/padiwa_pulser.vhd
index fd17b8982a83d3c7debbdc217fa24733f1e997fc..4c9a78012016170afb8c1a222f99fe0bcb1894ed 100644 (file)
--- a/pulser/padiwa_pulser.vhd
+++ b/pulser/padiwa_pulser.vhd
@@ -38,9 +38,14 @@ end component;
 
 attribute NOM_FREQ : string;
 attribute NOM_FREQ of clk_source : label is "133.00";
-signal clk_i  : std_logic;
+signal clk_i   : std_logic;
+signal clk_osc : std_logic;
+signal clk_26  : std_logic;
 
-signal led    : std_logic_vector(3 downto 0) := "1010";
+signal led     : std_logic_vector(3 downto 0) := "1010";
+signal input_i : std_logic_vector(255 downto 0) := (others => '0');
+
+signal uart_rx_data : std_logic_vector(31 downto 0);
 
 begin
 
@@ -53,10 +58,17 @@ clk_source: OSCH
 -- synthesis translate_on
   port map (
     STDBY    => '0',
-    OSC      => clk_i,
+    OSC      => clk_osc,
     SEDSTDBY => open
   );
 
+THE_PLL : entity work.pll
+    port map(
+        CLKI   => clk_osc,
+        CLKOP  => clk_26, --33
+        CLKOS  => clk_i, --133
+        LOCK   => open  --no lock available!
+        );
   
 ---------------------------------------------------------------------------
 -- UART
@@ -68,7 +80,7 @@ THE_UART : entity work.uart_sctrl
     UART_RX => SPARE_LINE(0),
     UART_TX => SPARE_LINE(2),
     
-    DATA_OUT  => open,
+    DATA_OUT  => uart_rx_data,
     DATA_IN   => x"00000000",
     WRITE_OUT => open,
     READ_OUT  => open,
@@ -78,6 +90,30 @@ THE_UART : entity work.uart_sctrl
     );
 
 
+---------------------------------------------------------------------------
+-- LCD
+---------------------------------------------------------------------------    
+THE_LCD : entity work.lcd 
+  port map(
+    CLK   => clk_26,
+    RESET => '0',
+    
+    MOSI  => TEST_LINE(9),
+    SCK   => TEST_LINE(8),
+    DC    => TEST_LINE(10),
+    CS    => TEST_LINE(12),
+    RST   => TEST_LINE(11),
+    
+    INPUT => input_i,
+    LED   => open
+    
+    );    
+TEST_LINE(7 downto 0)   <= x"00";
+TEST_LINE(15 downto 13) <= (others => '0');
+    
+input_i(31 downto 0)     <= uart_rx_data;
+    
+
     
 ---------------------------------------------------------------------------
 -- Other I/O
@@ -85,7 +121,6 @@ THE_UART : entity work.uart_sctrl
 SPARE_LINE(1) <= 'Z'; --C1 spare
 SPARE_LINE(3) <= 'Z'; --C2 spare
 
-
 LED_GREEN  <= led(0);
 LED_ORANGE <= led(1);
 LED_RED    <= led(2);

diff --git a/source/uart_sctrl.vhd b/source/uart_sctrl.vhd
index e6a968adbe8583519e3a1a79c2511f5abdb34873..b3d4fa385fa5e4778501c8409f5e2d7e591e7868 100644 (file)
--- a/source/uart_sctrl.vhd
+++ b/source/uart_sctrl.vhd
@@ -65,5 +65,7 @@ THE_TX : entity work.uart_trans
     
 tx_data <= rx_data;
 tx_send <= rx_ready;
-    
+
+DATA_OUT(7 downto 0) <= rx_data;
+
 end architecture;
\ No newline at end of file