*** empty log message ***

diff --git a/cts.tex b/cts.tex
index e581e9394b3c34dd8b584809f0e7eadfa4f596da..69c2fd1c81dcc9573311c603c7b97818314302b5 100644 (file)
--- a/cts.tex
+++ b/cts.tex
@@ -6,8 +6,8 @@
 %\subsection{Memory Map}
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
-Register addresses from 0xA000 to 0xA0ef is SCM FPGA (1) \nw 
-Register addresses from 0xA0f0 to 0xA0ff is ECP2M FPGA (2) \nw
+Register addresses from 0xA000 to 0xA0ef is SCM FPGA (1) \\
+Register addresses from 0xA0f0 to 0xA0ff is ECP2M FPGA (2) \\
 Register addresses from 0xA100 to 0xA100 + 26*500 (500 is number of samples per beam structure), the histograms are created in the SCM FPGA (1) see fig. \ref{ctsbeam}. First 8 is START next 8 is also START but perpendicular stripes. Next 8 is Veto and for the last two the source is selected by 0xA0C2 register.
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@@ -217,6 +217,7 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
  \item[0xA02B -- 0xA008 ] Input scalers
  \item[0xA03E -- 0xA02C ] Scalers after downscaling
  \item[0xA051 -- 0xA03F ] Scalers after trigger accepted
+ \item[0xA062 -- 0xA052] Scalers after coincidence
 
 % \item[0xA046] Rate markers for start detector
 % \begin{description}