LOCATE COMP "RES" SITE "P4";
IOBUF PORT "RES" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
LOCATE COMP "TACK" SITE "P14";
+ IOBUF PORT "TACK" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
# LOCATE COMP "TADS_0" SITE "N9";
# LOCATE COMP "TADS_1" SITE "P10";
LOCATE COMP "TAOD" SITE "T5";
+ IOBUF PORT "TAOD" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
# LOCATE COMP "TCDE_0" SITE "R13";
# LOCATE COMP "TDRA" SITE "N10";
# LOCATE COMP "TDRB" SITE "T14";
# LOCATE COMP "TDRE" SITE "R11";
LOCATE COMP "TDST" SITE "R16";
+ IOBUF PORT "TDST" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
# LOCATE COMP "TENB" SITE "T11";
# LOCATE COMP "TENR" SITE "T13";
LOCATE COMP "TOK" SITE "P2";
entity adc_ltc2308_readout is
generic(
CLOCK_FREQUENCY : integer := 100; --MHz
- PRESET_RANGES_CH0 : std_logic_vector(23 downto 0) := x"C10_A28" ; --5V/2 - 2.4-2.6
+ PRESET_RANGES_CH0 : std_logic_vector(23 downto 0) := x"C10_A28" ; --5V/2 - 2.4-3.1
PRESET_RANGES_CH1 : std_logic_vector(23 downto 0) := x"A00_940" ; --5V/2 - 2.4-2.6
PRESET_RANGES_CH2 : std_logic_vector(23 downto 0) := x"F00_D50" ; --3.5 - 3.4-3.8
- PRESET_RANGES_CH3 : std_logic_vector(23 downto 0) := x"D48_C80" ; --3.3 - 3.2-3.4
- PRESET_RANGES_CH4 : std_logic_vector(23 downto 0) := x"6A0_510" ; --1.4 - 1.3-1.7
+ PRESET_RANGES_CH3 : std_logic_vector(23 downto 0) := x"D80_C80" ; --3.3 - 3.2-3.4
+ PRESET_RANGES_CH4 : std_logic_vector(23 downto 0) := x"770_510" ; --1.4 - 1.3-1.9
PRESET_RANGES_CH5 : std_logic_vector(23 downto 0) := x"4E0_480" ; --1.2 - 1.15-1.25
PRESET_RANGES_CH6 : std_logic_vector(23 downto 0) := x"C10_B50" ; --3.0 - 2.9-3.1
- PRESET_RANGES_CH7 : std_logic_vector(23 downto 0) := x"C10_B50" ---3.0 - ???-???
+ PRESET_RANGES_CH7 : std_logic_vector(23 downto 0) := x"C10_B50" ---3.0 - 2.9-3.1
);
port(
CLK : in std_logic;
--1c2 wr Errorbits sender_error 32bit used
--1c3 w sender data fifo sender_data 16bit used
--1c4 r sender fifo status (9..0 datacount, 16 full, 17 empty)
+--1c5 wr Extended Trigger Information sender_trigger_information 16bit
--1cF r status (0)transfer running sender_status 1bit used
+
--received data
--2c3 r receiver data fifo, (20..18)type receiver_data 16bit used
--2c4 r receiver fifo status (9..0 datacount, 16 full, 17 empty)
signal apl_to_buf_INIT_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0);
signal apl_to_buf_INIT_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);
+ signal tmp_apl_to_buf_INIT_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);
signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0);
signal apl_to_buf_INIT_READ : std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0);
signal RESET_CNT : std_logic_vector(1 downto 0);
signal counter : std_logic_vector(12 downto 0);
signal buf_MED_DATAREADY_OUT : std_logic;
+
+ signal reg_extended_trigger_information : std_logic_vector(15 downto 0);
+
begin
CLK_EN <= '1';
APL_MY_ADDRESS_IN <= x"F00C";
gen_iobufs : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate
gen_used_channel : if USE_CHANNELS(i) = c_YES generate
IOBUF: trb_net16_iobuf
+ generic map (
+ USE_CHECKSUM => cfg_USE_CHECKSUM(i)
+ )
port map (
-- Misc
CLK => CLK ,
APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i+1)*8),
-- Internal direction port
INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
- INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_MASTER_DATA_OUT => tmp_apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i),
INT_MASTER_DATAREADY_IN => '0',
end generate;
end generate;
+--Add additional word for trigger information
+ apl_to_buf_INIT_DATA(apl_to_buf_INIT_DATA'left downto 16) <= tmp_apl_to_buf_INIT_DATA(apl_to_buf_INIT_DATA'left downto 16);
+
+ proc_add_trigger_info : process(tmp_apl_to_buf_INIT_DATA, apl_to_buf_INIT_PACKET_NUM,reg_extended_trigger_information)
+ begin
+ if apl_to_buf_INIT_PACKET_NUM(2 downto 0) = c_F0 then
+ apl_to_buf_INIT_DATA(15 downto 0) <= reg_extended_trigger_information;
+ else
+ apl_to_buf_INIT_DATA(15 downto 0) <= tmp_apl_to_buf_INIT_DATA(15 downto 0);
+ end if;
+ end process;
+
+ proc_save_trigger_info : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if CPU_ADDRESS = x"0115" and CPU_WRITE = '1' then
+ reg_extended_trigger_information <= CPU_DATA_IN(15 downto 0);
+ end if;
+ end if;
+ end process;
+
+
APL : trb_net_bridge_etrax_apl
port map(
CLK => CLK,
TRG_SEND_IN : in std_logic;
TRG_TYPE_IN : in std_logic_vector (3 downto 0);
TRG_NUMBER_IN : in std_logic_vector (15 downto 0);
- TRG_INFORMATION_IN : in std_logic_vector (7 downto 0);
+ TRG_INFORMATION_IN : in std_logic_vector (23 downto 0);
TRG_RND_CODE_IN : in std_logic_vector (7 downto 0);
TRG_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
TRG_BUSY_OUT : out std_logic;
architecture trb_net16_endpoint_hades_cts_arch of trb_net16_endpoint_hades_cts is
-signal apl_to_buf_INIT_DATAREADY: std_logic_vector(3 downto 0);
-signal apl_to_buf_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-signal apl_to_buf_INIT_READ : std_logic_vector(3 downto 0);
+signal apl_to_buf_INIT_DATAREADY : std_logic_vector (3 downto 0);
+signal apl_to_buf_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+signal tmp_apl_to_buf_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+signal apl_to_buf_INIT_PACKET_NUM : std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
+signal apl_to_buf_INIT_READ : std_logic_vector (3 downto 0);
-signal buf_to_apl_INIT_DATAREADY: std_logic_vector(3 downto 0);
-signal buf_to_apl_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-signal buf_to_apl_INIT_READ : std_logic_vector(3 downto 0);
+signal buf_to_apl_INIT_DATAREADY : std_logic_vector (3 downto 0);
+signal buf_to_apl_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+signal buf_to_apl_INIT_PACKET_NUM : std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
+signal buf_to_apl_INIT_READ : std_logic_vector (3 downto 0);
-signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(3 downto 0);
-signal apl_to_buf_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-signal apl_to_buf_REPLY_READ : std_logic_vector(3 downto 0);
+signal apl_to_buf_REPLY_DATAREADY : std_logic_vector (3 downto 0);
+signal apl_to_buf_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+signal apl_to_buf_REPLY_PACKET_NUM: std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
+signal apl_to_buf_REPLY_READ : std_logic_vector (3 downto 0);
-signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(3 downto 0);
-signal buf_to_apl_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-signal buf_to_apl_REPLY_READ : std_logic_vector(3 downto 0);
+signal buf_to_apl_REPLY_DATAREADY : std_logic_vector (3 downto 0);
+signal buf_to_apl_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+signal buf_to_apl_REPLY_PACKET_NUM: std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
+signal buf_to_apl_REPLY_READ : std_logic_vector (3 downto 0);
-- for the connection to the multiplexer
-- for the connection to the multiplexer
signal buf_APL_SEQNR_OUT : std_logic_vector(4*8-1 downto 0);
signal buf_APL_LENGTH_IN : std_logic_vector(16*4-1 downto 0);
+signal reg_extended_trigger_information : std_logic_vector(15 downto 0);
signal buf_TRG_STATUS_BITS_OUT : std_logic_vector(31 downto 0);
signal buf_IPU_STATUS_BITS_OUT : std_logic_vector(31 downto 0);
signal buf_IPU_DATA_OUT : std_logic_vector(31 downto 0);
APL_LENGTH_IN => buf_APL_LENGTH_IN((j+1)*16-1 downto j*16),
-- Internal direction port
INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
- INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_MASTER_DATA_OUT => tmp_apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i),
INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
INT_MASTER_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ(i),
INT_SLAVE_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
- INT_SLAVE_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_SLAVE_DATA_OUT => tmp_apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
INT_SLAVE_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
INT_SLAVE_READ_IN => apl_to_buf_INIT_READ(i),
INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
apl_to_buf_INIT_READ(i) <= '0';
apl_to_buf_INIT_DATAREADY(i) <= '0';
- apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+ tmp_apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
apl_to_buf_REPLY_DATAREADY(i) <= '0';
apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
buf_APL_DTYPE_IN(3 downto 0) <= TRG_TYPE_IN;
buf_APL_ERROR_PATTERN_IN(15 downto 0) <= TRG_NUMBER_IN;
buf_APL_ERROR_PATTERN_IN(23 downto 16) <= TRG_RND_CODE_IN;
- buf_APL_ERROR_PATTERN_IN(31 downto 24) <= TRG_INFORMATION_IN;
+ buf_APL_ERROR_PATTERN_IN(31 downto 24) <= TRG_INFORMATION_IN(7 downto 0);
TRG_BUSY_OUT <= buf_APL_RUN_OUT(0);
TRG_STATUS_BITS_OUT <= buf_TRG_STATUS_BITS_OUT;
end if;
end process;
+--Add additional word for trigger information
+ apl_to_buf_INIT_DATA(apl_to_buf_INIT_DATA'left downto 16) <= tmp_apl_to_buf_INIT_DATA(apl_to_buf_INIT_DATA'left downto 16);
+ proc_add_trigger_info : process(tmp_apl_to_buf_INIT_DATA, apl_to_buf_INIT_PACKET_NUM,reg_extended_trigger_information)
+ begin
+ if apl_to_buf_INIT_PACKET_NUM(2 downto 0) = c_F0 then
+ apl_to_buf_INIT_DATA(15 downto 0) <= reg_extended_trigger_information;
+ else
+ apl_to_buf_INIT_DATA(15 downto 0) <= tmp_apl_to_buf_INIT_DATA(15 downto 0);
+ end if;
+ end process;
+
+ proc_save_trigger_info : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if TRG_SEND_IN = '1' then
+ reg_extended_trigger_information <= TRG_INFORMATION_IN(23 downto 8);
+ end if;
+ end if;
+ end process;
-------------------------------------------------------------------------------
LVL1_TRG_RECEIVED_OUT : out std_logic;
LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);
- LVL1_TRG_INFORMATION_OUT : out std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);
LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000";
LVL1_TRG_RELEASE_IN : in std_logic := '0';
LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
signal buf_LVL1_TRG_RECEIVED_OUT : std_logic;
signal buf_LVL1_TRG_NUMBER_OUT : std_logic_vector(15 downto 0);
signal buf_LVL1_TRG_CODE_OUT : std_logic_vector(7 downto 0);
- signal buf_LVL1_TRG_INFORMATION_OUT : std_logic_vector(7 downto 0);
+ signal buf_LVL1_TRG_INFORMATION_OUT : std_logic_vector(23 downto 0);
signal last_LVL1_TRG_RECEIVED_OUT : std_logic;
signal LVL1_TRG_RECEIVED_OUT_rising : std_logic;
signal LVL1_TRG_RECEIVED_OUT_falling: std_logic;
--hub control
HUB_CTRL_CHANNELNUM : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL;
HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;
+ HUB_CTRL_ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";
+ HUB_CTRL_BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FE";
HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES);
USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES);
USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
generic map(
API_TYPE => 0,
FIFO_TO_INT_DEPTH => HUB_CTRL_DEPTH,
- FIFO_TO_APL_DEPTH => HUB_CTRL_DEPTH
+ FIFO_TO_APL_DEPTH => HUB_CTRL_DEPTH,
+ ADDRESS_MASK => HUB_CTRL_ADDRESS_MASK,
+ BROADCAST_BITMASK => HUB_CTRL_BROADCAST_BITMASK
)
port map(
-- Misc
--Status Registers
buf_HC_STAT_REGS(4*32-1 downto 0) <= buf_STAT_POINTS_locked;
buf_HC_STAT_REGS(5*32-1 downto 4*32) <= HUB_MED_CONNECTED;
- buf_HC_STAT_REGS(5*32+15 downto 5*32) <= stat_ipu_fsm;
- buf_HC_STAT_REGS(8*32-1 downto 5*32+16) <= (others => '0'); --unused regs
+ buf_HC_STAT_REGS(5*32+31 downto 5*32+17) <= (others => '0');
+ buf_HC_STAT_REGS(6*32+31 downto 6*32+17) <= (others => '0');
buf_HC_STAT_REGS(16*32-1 downto 12*32) <= (others => '0'); --unused regs
+ loop_links : for i in 0 to 16 generate
+ buf_HC_STAT_REGS(5*32+i) <= '1' when i < MII_NUMBER and MII_IS_UPLINK(i) = 1 else '0';
+ buf_HC_STAT_REGS(6*32+i) <= '1' when i < MII_NUMBER and MII_IS_DOWNLINK(i) = 1 else '0';
+ end generate;
+
PROC_TIMEOUT : process(CLK)
begin
if rising_edge(CLK) then
signal REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0);
signal next_REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0);
signal current_REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0);
- signal reading_trmF0, reading_trmF1 : std_logic_vector(POINT_NUMBER-1 downto 0);
- signal reading_trmF2, reading_trmF3 : std_logic_vector(POINT_NUMBER-1 downto 0);
- signal REPLY_combined_trm_F1 : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal REPLY_combined_trm_F2, REPLY_combined_trm_F3 : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal REPLY_MUX_real_reading : std_logic;
- signal real_activepoints : std_logic_vector(POINT_NUMBER-1 downto 0);
+ signal reading_trmF0 : std_logic_vector(POINT_NUMBER-1 downto 0);
+ signal reading_trmF1 : std_logic_vector(POINT_NUMBER-1 downto 0);
+ signal reading_trmF2 : std_logic_vector(POINT_NUMBER-1 downto 0);
+ signal reading_trmF3 : std_logic_vector(POINT_NUMBER-1 downto 0);
+ signal REPLY_combined_trm_F0 : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal REPLY_combined_trm_F1 : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal REPLY_combined_trm_F2 : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal REPLY_combined_trm_F3 : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal REPLY_MUX_real_reading : std_logic;
+ signal real_activepoints : std_logic_vector(POINT_NUMBER-1 downto 0);
--general signals
signal locked, next_locked : std_logic;
gen_combining_trm : for j in 0 to c_DATA_WIDTH-1 generate
process(CLK)
- variable tmpF1, tmpF2, tmpF3 : std_logic;
+ variable tmpF0,tmpF1, tmpF2, tmpF3 : std_logic;
begin
if rising_edge(CLK) then
if reset_i = '1' or locked = '0' then
+ REPLY_combined_trm_F0(j) <= '0';
REPLY_combined_trm_F1(j) <= '0';
REPLY_combined_trm_F2(j) <= '0';
REPLY_combined_trm_F3(j) <= '0';
else
+ tmpF0 := '0';
tmpF1 := '0';
tmpF2 := '0';
tmpF3 := '0';
for i in 0 to POINT_NUMBER-1 loop
+ tmpF0 := tmpF0 or (reply_data_in_i(i*c_DATA_WIDTH+j) and reading_trmF0(i));
tmpF1 := tmpF1 or (reply_data_in_i(i*c_DATA_WIDTH+j) and reading_trmF1(i));
tmpF2 := tmpF2 or (reply_data_in_i(i*c_DATA_WIDTH+j) and reading_trmF2(i));
tmpF3 := tmpF3 or (reply_data_in_i(i*c_DATA_WIDTH+j) and reading_trmF3(i));
end loop;
+ REPLY_combined_trm_F0(j) <= REPLY_combined_trm_F0(j) or tmpF0;
REPLY_combined_trm_F1(j) <= REPLY_combined_trm_F1(j) or tmpF1;
if j = 6 then
reply_combined_trm_F2(j) <= reply_combined_trm_F2(j) or tmpF2 or timeout_found;
----------------------------------
--REPLY POOL state machine
----------------------------------
- reply_state_machine : process(REPLY_POOL_next_READ, current_state, packet_counter,
+ reply_state_machine : process(REPLY_POOL_next_READ, current_state, packet_counter, REPLY_combined_trm_F0,
send_reply_trm, REPLY_combined_trm_F1, REPLY_combined_trm_F2,
comb_REPLY_muxed_DATAREADY, comb_REPLY_muxed_DATA, init_locked,
comb_REPLY_muxed_PACKET_NUM, waiting_for_init_finish, REPLY_combined_trm_F3)
end if;
case packet_counter is
when c_F0 =>
- comb_REPLY_POOL_DATA <= x"0000";
+ comb_REPLY_POOL_DATA <=REPLY_combined_trm_F0;
when c_F1 =>
comb_REPLY_POOL_DATA <= REPLY_combined_trm_F1;
when c_F2 =>
max_DATA_COUNT_minus_one <= (others => '0');
end generate;
- GENERATE_WORDS : process (transfer_counter)
--- , SEND_BUFFER_SIZE_IN, int_data_in_i,
--- CURRENT_DATA_COUNT, CRC, saved_packet_type,buffer_number, CTRL_BUFFER)
+ GENERATE_WORDS : process (transfer_counter, saved_packet_type, int_data_in_i, CRC, buffer_number, CTRL_BUFFER)
begin
current_NOP_word <= (others => '0');
current_ACK_word <= (others => '0');
TRG_TYPE_OUT : out std_logic_vector (3 downto 0);
TRG_NUMBER_OUT : out std_logic_vector (15 downto 0);
TRG_CODE_OUT : out std_logic_vector (7 downto 0);
- TRG_INFORMATION_OUT : out std_logic_vector (7 downto 0);
+ TRG_INFORMATION_OUT : out std_logic_vector (23 downto 0);
TRG_RECEIVED_OUT : out std_logic;
TRG_RELEASE_IN : in std_logic;
TRG_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0)
signal next_TRG_TYPE_OUT, reg_TRG_TYPE_OUT: std_logic_vector(3 downto 0);
signal next_TRG_NUMBER_OUT, reg_TRG_NUMBER_OUT: std_logic_vector(15 downto 0);
signal next_TRG_CODE_OUT, reg_TRG_CODE_OUT: std_logic_vector(7 downto 0);
- signal next_TRG_INFORMATION_OUT, reg_TRG_INFORMATION_OUT: std_logic_vector(7 downto 0);
+ signal next_TRG_INFORMATION_OUT, reg_TRG_INFORMATION_OUT: std_logic_vector(23 downto 0);
signal next_TRG_RECEIVED_OUT, reg_TRG_RECEIVED_OUT: std_logic;
signal buf_TRG_ERROR_PATTERN_IN: std_logic_vector(31 downto 0);
next_TRG_RECEIVED_OUT <= reg_TRG_RECEIVED_OUT;
next_seqnr <= seqnr;
if saved_packet_type = TYPE_TRM and INT_DATAREADY_IN = '1' then
- if INT_PACKET_NUM_IN = c_F1 then
- next_TRG_INFORMATION_OUT <= INT_DATA_IN(15 downto 8);
+ if INT_PACKET_NUM_IN = c_F0 then
+ next_TRG_INFORMATION_OUT(23 downto 8) <= INT_DATA_IN(15 downto 0);
+ elsif INT_PACKET_NUM_IN = c_F1 then
+ next_TRG_INFORMATION_OUT(7 downto 0) <= INT_DATA_IN(15 downto 8);
next_TRG_CODE_OUT <= INT_DATA_IN(7 downto 0);
elsif INT_PACKET_NUM_IN = c_F2 then
next_TRG_NUMBER_OUT <= INT_DATA_IN(15 downto 0);
TRG_TYPE_OUT : out std_logic_vector (3 downto 0);
TRG_NUMBER_OUT : out std_logic_vector (15 downto 0);
TRG_CODE_OUT : out std_logic_vector (7 downto 0);
- TRG_INFORMATION_OUT : out std_logic_vector (7 downto 0);
+ TRG_INFORMATION_OUT : out std_logic_vector (23 downto 0);
TRG_RECEIVED_OUT : out std_logic;
TRG_RELEASE_IN : in std_logic;
TRG_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0)