*** empty log message ***

diff --git a/trb_net_sbuf5.vhd b/trb_net_sbuf5.vhd
index b157aa991e871bb015b6e75da13a12eae65b1a2b..805f3b3366e9128d31e58962e75c4792a8b9be09 100644 (file)
--- a/trb_net_sbuf5.vhd
+++ b/trb_net_sbuf5.vhd
@@ -73,20 +73,22 @@ signal fifo_almostfull       : std_logic;
 \r
 signal debug_x               : std_logic_vector(15 downto 0);\r
 \r
+attribute syn_preserve : boolean;\r
+attribute syn_keep     : boolean;\r
+attribute syn_preserve of syn_data        : signal is true;\r
+attribute syn_keep of syn_data            : signal is true;\r
+attribute syn_preserve of syn_dataready   : signal is true;\r
+attribute syn_keep of syn_dataready       : signal is true;\r
+attribute syn_preserve of syn_dataready_x : signal is true;\r
+attribute syn_keep of syn_dataready_x     : signal is true;\r
 \r
+attribute syn_preserve of fifo_wcnt       : signal is true; \r
+attribute syn_keep of fifo_wcnt           : signal is true; \r
+attribute syn_preserve of bsm             : signal is true; \r
+attribute syn_keep of bsm                 : signal is true; \r
 \r
-  attribute syn_preserve : boolean;\r
-  attribute syn_keep : boolean;\r
-  attribute syn_preserve of syn_data : signal is true;\r
-  attribute syn_keep of syn_data : signal is true;\r
-  attribute syn_preserve of syn_dataready : signal is true;\r
-  attribute syn_keep of syn_dataready : signal is true;\r
-  attribute syn_preserve of syn_dataready_x : signal is true;\r
-  attribute syn_keep of syn_dataready_x : signal is true;\r
-\r
-  attribute syn_hier : string;\r
-  attribute syn_hier of trb_net_sbuf5_arch : architecture is "flatten, firm";\r
-\r
+attribute syn_hier : string;\r
+attribute syn_hier of trb_net_sbuf5_arch : architecture is "flatten, firm";\r
 \r
 begin\r
 \r
@@ -140,10 +142,12 @@ begin
                        CURRENT_STATE <= IDLE;\r
                        syn_dataready <= '0';\r
                        update        <= '0';\r
+                       bsm           <= x"0";\r
                else\r
                        CURRENT_STATE <= NEXT_STATE;\r
                        syn_dataready <= syn_dataready_x;\r
                        update        <= update_x;\r
+                       bsm           <= bsm_x;\r
                end if;\r
        end if;\r
 end process STATE_MEM;\r
@@ -156,23 +160,20 @@ begin
        syn_dataready_x <= '0';\r
        update_x        <= '0';\r
        case CURRENT_STATE is\r
-               when IDLE   =>  bsm_x <= x"0";\r
-                                               if( p_wait_x = '1' ) then\r
+               when IDLE   =>  if( p_wait_x = '1' ) then\r
                                                        NEXT_STATE   <= RD1;\r
                                                        fifo_rd_en_x <= '1';\r
                                                        update_x     <= '1';\r
                                                else\r
                                                        NEXT_STATE   <= IDLE;\r
                                                end if;\r
-               when RD1    =>  bsm_x <= x"1";\r
-                                               if( p_wait_x = '1' ) then\r
+               when RD1    =>  if( p_wait_x = '1' ) then\r
                                                        NEXT_STATE   <= RD2;\r
                                                        fifo_rd_en_x <= '1';\r
                                                else\r
                                                        NEXT_STATE   <= RD1;\r
                                                end if;\r
-               when RD2    =>  bsm_x <= x"2";\r
-                                               if   ( (p_avail_x = '1') and (SYN_READ_IN = '1') and (syn_dataready = '1') ) then\r
+               when RD2    =>  if   ( (p_avail_x = '1') and (SYN_READ_IN = '1') and (syn_dataready = '1') ) then\r
                                                        NEXT_STATE      <= RD3;\r
                                                        syn_dataready_x <= '1';\r
                                                        fifo_rd_en_x    <= '1';\r
@@ -183,8 +184,7 @@ begin
                                                        NEXT_STATE      <= RD2;\r
                                                        syn_dataready_x <= p_avail_x;\r
                                                end if;\r
-               when DEL        =>  bsm_x <= x"8";\r
-                                               if( SYN_READ_IN = '1' ) then\r
+               when DEL        =>  if( SYN_READ_IN = '1' ) then\r
                                                        NEXT_STATE      <= RD3;\r
                                                        fifo_rd_en_x    <= '1';\r
                                                        syn_dataready_x <= '1';\r
@@ -192,8 +192,7 @@ begin
                                                        NEXT_STATE <= DEL;\r
                                                        syn_dataready_x <= '1';\r
                                                end if;\r
-               when RD3    =>  bsm_x <= x"3";\r
-                                               if( SYN_READ_IN = '1' ) then\r
+               when RD3    =>  if( SYN_READ_IN = '1' ) then\r
                                                        NEXT_STATE      <= RD4;\r
                                                        syn_dataready_x <= '1';\r
                                                        fifo_rd_en_x    <= '1';\r
@@ -201,8 +200,7 @@ begin
                                                        NEXT_STATE      <= RD3;\r
                                                        syn_dataready_x <= '1';\r
                                                end if;\r
-               when RD4    =>  bsm_x <= x"4";\r
-                                               if( SYN_READ_IN = '1' ) then\r
+               when RD4    =>  if( SYN_READ_IN = '1' ) then\r
                                                        NEXT_STATE      <= RD5;\r
                                                        syn_dataready_x <= '1';\r
                                                        fifo_rd_en_x    <= '1';\r
@@ -210,8 +208,7 @@ begin
                                                        NEXT_STATE      <= RD4;\r
                                                        syn_dataready_x <= '1';\r
                                                end if;\r
-               when RD5    =>  bsm_x <= x"5";\r
-                                               syn_dataready_x <= '1';\r
+               when RD5    =>  syn_dataready_x <= '1';\r
                                                if   ( (SYN_READ_IN = '1') and (p_avail_x = '1') ) then\r
                                                        NEXT_STATE      <= WR5;\r
                                                        fifo_rd_en_x    <= '1';\r
@@ -220,26 +217,40 @@ begin
                                                else\r
                                                        NEXT_STATE      <= RD5;\r
                                                end if;\r
-               when WT5    =>  bsm_x <= x"6";\r
-                                               if( SYN_READ_IN = '1' ) then\r
+               when WT5    =>  if( SYN_READ_IN = '1' ) then\r
                                                        NEXT_STATE <= IDLE;\r
                                                else\r
                                                        NEXT_STATE <= WT5;\r
                                                        syn_dataready_x <= '1';\r
                                                end if;\r
-               when WR5    =>  bsm_x <= x"7";\r
---                                             syn_dataready_x <= '1';\r
-                                               if( (SYN_READ_IN = '1') and (p_avail_x = '1') ) then\r
+               when WR5    =>  if( (SYN_READ_IN = '1') and (p_avail_x = '1') ) then\r
                                                        NEXT_STATE      <= RD2;\r
                                                        fifo_rd_en_x    <= '1';\r
                                                        syn_dataready_x <= '1';\r
                                                else\r
                                                        NEXT_STATE      <= WR5;\r
                                                end if;\r
-               when others =>  bsm_x <= x"f";\r
+               when others =>  NEXT_STATE <= IDLE;\r
        end case;\r
 end process STATE_TRANSFORM;\r
 \r
+THE_DECODE_PROC: process( NEXT_STATE )\r
+begin\r
+       case NEXT_STATE is\r
+               when IDLE   => bsm_x <= x"0";\r
+               when RD1    => bsm_x <= x"1";\r
+               when RD2    => bsm_x <= x"2";\r
+               when RD3    => bsm_x <= x"3";\r
+               when RD4    => bsm_x <= x"4";\r
+               when RD5    => bsm_x <= x"5";\r
+               when WT5    => bsm_x <= x"6";\r
+               when WR5    => bsm_x <= x"7";\r
+               when WD5    => bsm_x <= x"8";\r
+               when DEL    => bsm_x <= x"9";\r
+               when others => bsm_x <= x"f";\r
+       end case;\r
+end process THE_DECODE_PROC;\r
+\r
 THE_SYNC_PROC: process( CLK )\r
 begin\r
        if( rising_edge(CLK) ) then\r