S1 : out std_logic);
end component;
component FD1P3DX
- port (D : in std_logic;
- SP : in std_logic;
- CK : in std_logic;
- CD : in std_logic;
- Q : out std_logic);
+ port (D : in std_logic;
+ SP : in std_logic;
+ CK : in std_logic;
+ CD : in std_logic;
+ Q : out std_logic);
end component;
component VLO
- port (Z : out std_logic);
+ port (Z : out std_logic);
end component;
attribute GSR : string;
FF_100 : FD1P3DX
port map (D => tsum(100), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(100));
- FF_99 : FD1P3DX
+ FF_99 : FD1P3DX
port map (D => tsum(99), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(99));
- FF_98 : FD1P3DX
+ FF_98 : FD1P3DX
port map (D => tsum(98), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(98));
- FF_97 : FD1P3DX
+ FF_97 : FD1P3DX
port map (D => tsum(97), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(97));
- FF_96 : FD1P3DX
+ FF_96 : FD1P3DX
port map (D => tsum(96), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(96));
- FF_95 : FD1P3DX
+ FF_95 : FD1P3DX
port map (D => tsum(95), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(95));
- FF_94 : FD1P3DX
+ FF_94 : FD1P3DX
port map (D => tsum(94), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(94));
- FF_93 : FD1P3DX
+ FF_93 : FD1P3DX
port map (D => tsum(93), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(93));
- FF_92 : FD1P3DX
+ FF_92 : FD1P3DX
port map (D => tsum(92), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(92));
- FF_91 : FD1P3DX
+ FF_91 : FD1P3DX
port map (D => tsum(91), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(91));
- FF_90 : FD1P3DX
+ FF_90 : FD1P3DX
port map (D => tsum(90), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(90));
- FF_89 : FD1P3DX
+ FF_89 : FD1P3DX
port map (D => tsum(89), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(89));
- FF_88 : FD1P3DX
+ FF_88 : FD1P3DX
port map (D => tsum(88), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(88));
- FF_87 : FD1P3DX
+ FF_87 : FD1P3DX
port map (D => tsum(87), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(87));
- FF_86 : FD1P3DX
+ FF_86 : FD1P3DX
port map (D => tsum(86), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(86));
- FF_85 : FD1P3DX
+ FF_85 : FD1P3DX
port map (D => tsum(85), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(85));
- FF_84 : FD1P3DX
+ FF_84 : FD1P3DX
port map (D => tsum(84), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(84));
- FF_83 : FD1P3DX
+ FF_83 : FD1P3DX
port map (D => tsum(83), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(83));
- FF_82 : FD1P3DX
+ FF_82 : FD1P3DX
port map (D => tsum(82), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(82));
- FF_81 : FD1P3DX
+ FF_81 : FD1P3DX
port map (D => tsum(81), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(81));
- FF_80 : FD1P3DX
+ FF_80 : FD1P3DX
port map (D => tsum(80), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(80));
- FF_79 : FD1P3DX
+ FF_79 : FD1P3DX
port map (D => tsum(79), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(79));
- FF_78 : FD1P3DX
+ FF_78 : FD1P3DX
port map (D => tsum(78), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(78));
- FF_77 : FD1P3DX
+ FF_77 : FD1P3DX
port map (D => tsum(77), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(77));
- FF_76 : FD1P3DX
+ FF_76 : FD1P3DX
port map (D => tsum(76), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(76));
- FF_75 : FD1P3DX
+ FF_75 : FD1P3DX
port map (D => tsum(75), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(75));
- FF_74 : FD1P3DX
+ FF_74 : FD1P3DX
port map (D => tsum(74), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(74));
- FF_73 : FD1P3DX
+ FF_73 : FD1P3DX
port map (D => tsum(73), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(73));
- FF_72 : FD1P3DX
+ FF_72 : FD1P3DX
port map (D => tsum(72), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(72));
- FF_71 : FD1P3DX
+ FF_71 : FD1P3DX
port map (D => tsum(71), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(71));
- FF_70 : FD1P3DX
+ FF_70 : FD1P3DX
port map (D => tsum(70), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(70));
- FF_69 : FD1P3DX
+ FF_69 : FD1P3DX
port map (D => tsum(69), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(69));
- FF_68 : FD1P3DX
+ FF_68 : FD1P3DX
port map (D => tsum(68), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(68));
- FF_67 : FD1P3DX
+ FF_67 : FD1P3DX
port map (D => tsum(67), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(67));
- FF_66 : FD1P3DX
+ FF_66 : FD1P3DX
port map (D => tsum(66), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(66));
- FF_65 : FD1P3DX
+ FF_65 : FD1P3DX
port map (D => tsum(65), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(65));
- FF_64 : FD1P3DX
+ FF_64 : FD1P3DX
port map (D => tsum(64), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(64));
- FF_63 : FD1P3DX
+ FF_63 : FD1P3DX
port map (D => tsum(63), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(63));
- FF_62 : FD1P3DX
+ FF_62 : FD1P3DX
port map (D => tsum(62), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(62));
- FF_61 : FD1P3DX
+ FF_61 : FD1P3DX
port map (D => tsum(61), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(61));
- FF_60 : FD1P3DX
+ FF_60 : FD1P3DX
port map (D => tsum(60), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(60));
- FF_59 : FD1P3DX
+ FF_59 : FD1P3DX
port map (D => tsum(59), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(59));
- FF_58 : FD1P3DX
+ FF_58 : FD1P3DX
port map (D => tsum(58), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(58));
- FF_57 : FD1P3DX
+ FF_57 : FD1P3DX
port map (D => tsum(57), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(57));
- FF_56 : FD1P3DX
+ FF_56 : FD1P3DX
port map (D => tsum(56), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(56));
- FF_55 : FD1P3DX
+ FF_55 : FD1P3DX
port map (D => tsum(55), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(55));
- FF_54 : FD1P3DX
+ FF_54 : FD1P3DX
port map (D => tsum(54), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(54));
- FF_53 : FD1P3DX
+ FF_53 : FD1P3DX
port map (D => tsum(53), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(53));
- FF_52 : FD1P3DX
+ FF_52 : FD1P3DX
port map (D => tsum(52), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(52));
- FF_51 : FD1P3DX
+ FF_51 : FD1P3DX
port map (D => tsum(51), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(51));
- FF_50 : FD1P3DX
+ FF_50 : FD1P3DX
port map (D => tsum(50), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(50));
- FF_49 : FD1P3DX
+ FF_49 : FD1P3DX
port map (D => tsum(49), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(49));
- FF_48 : FD1P3DX
+ FF_48 : FD1P3DX
port map (D => tsum(48), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(48));
- FF_47 : FD1P3DX
+ FF_47 : FD1P3DX
port map (D => tsum(47), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(47));
- FF_46 : FD1P3DX
+ FF_46 : FD1P3DX
port map (D => tsum(46), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(46));
- FF_45 : FD1P3DX
+ FF_45 : FD1P3DX
port map (D => tsum(45), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(45));
- FF_44 : FD1P3DX
+ FF_44 : FD1P3DX
port map (D => tsum(44), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(44));
- FF_43 : FD1P3DX
+ FF_43 : FD1P3DX
port map (D => tsum(43), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(43));
- FF_42 : FD1P3DX
+ FF_42 : FD1P3DX
port map (D => tsum(42), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(42));
- FF_41 : FD1P3DX
+ FF_41 : FD1P3DX
port map (D => tsum(41), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(41));
- FF_40 : FD1P3DX
+ FF_40 : FD1P3DX
port map (D => tsum(40), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(40));
- FF_39 : FD1P3DX
+ FF_39 : FD1P3DX
port map (D => tsum(39), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(39));
- FF_38 : FD1P3DX
+ FF_38 : FD1P3DX
port map (D => tsum(38), SP => CLKEn, CK => CLK, CD => Reset,
Q => r0_sum(38));
FF_37 : FD1P3DX
S0 => tsum(0),
S1 => tsum(1));
- GEN : for i in 1 to 151 generate
+ GEN : for i in 1 to 151 generate
ADD : FADD2B
port map (A0 => DataA(2*i),
A1 => DataA(2*i+1),
generic (
CHANNEL_ID : integer range 1 to 64);
port (
- RESET_WR : in std_logic;
- RESET_RD : in std_logic;
- CLK_WR : in std_logic;
- CLK_RD : in std_logic;
+ RESET_200 : in std_logic;
+ RESET_100 : in std_logic;
+ CLK_200 : in std_logic;
+ CLK_100 : in std_logic;
--
HIT_IN : in std_logic;
READ_EN_IN : in std_logic;
-------------------------------------------------------------------------------
-- Debug Signals
-------------------------------------------------------------------------------
+
signal hit_detect_cntr : std_logic_vector(23 downto 0);
signal hit_detect_cntr_reg : std_logic_vector(23 downto 0);
signal encoder_start_cntr : std_logic_vector(23 downto 0);
--purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition
FC : Adder_304
port map (
- CLK => CLK_WR,
- RESET => RESET_WR,
+ CLK => CLK_200,
+ RESET => RESET_200,
DataA => data_a_i,
DataB => data_b_i,
- ClkEn => '1', --ff_array_en_i,
+ ClkEn => '1', --ff_array_en_i,
Result => result_i);
data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF";
data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(hit_buf) & x"000000" & "00" & hit_buf;
--purpose: Registers the hit detection bit
- Hit_Register : process (CLK_WR, RESET_WR)
+ Hit_Detect_Register : process (CLK_200, RESET_200)
begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
+ if rising_edge(CLK_200) then
+ if RESET_200 = '1' then
result_2_reg <= '0';
hit_detect_reg <= '0';
hit_detect_2reg <= '0';
hit_detect_2reg <= hit_detect_reg;
end if;
end if;
- end process Hit_Register;
+ end process Hit_Detect_Register;
--purpose: Detects the hit
Hit_Detect : process (result_2_reg, result_i)
end process Hit_Detect;
--purpose: Double Synchroniser
- Double_Syncroniser : process (CLK_WR)
+ Double_Syncroniser : process (CLK_200)
begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
+ if rising_edge(CLK_200) then
+ if RESET_200 = '1' then
result_reg <= (others => '1');
elsif hit_detect_i = '1' then
result_reg <= result_i;
end process Double_Syncroniser;
--purpose: Start Encoder and captures the time stamp of the hit
- Start_Encoder : process (CLK_WR)
+ Start_Encoder : process (CLK_200)
begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
+ if rising_edge(CLK_200) then
+ if RESET_200 = '1' then
encoder_start_i <= '0';
hit_time_stamp_i <= (others => '0');
elsif hit_detect_reg = '1' then
encoder_start_i <= '1';
- hit_time_stamp_i <= coarse_cntr_i-2;
+ hit_time_stamp_i <= coarse_cntr_i;
else
encoder_start_i <= '0';
end if;
--purpose: Encoder
Encoder : Encoder_304_Bit
port map (
- RESET => RESET_WR,
- CLK => CLK_WR,
+ RESET => RESET_200,
+ CLK => CLK_200,
START_IN => encoder_start_i,
- THERMOCODE_IN => result_reg, --result_i,
+ THERMOCODE_IN => result_reg, --result_i,
FINISHED_OUT => fifo_wr_en_i,
BINARY_CODE_OUT => fine_counter_i,
ENCODER_DEBUG => encoder_debug_i);
FIFO : FIFO_32x32_OutReg
port map (
Data => fifo_data_in_i,
- WrClock => CLK_WR,
- RdClock => CLK_RD,
+ WrClock => CLK_200,
+ RdClock => CLK_100,
WrEn => fifo_wr_en_i,
RdEn => fifo_rd_en_i,
- Reset => RESET_RD,
- RPReset => RESET_RD,
+ Reset => RESET_100,
+ RPReset => RESET_100,
Q => fifo_data_out_i,
Empty => fifo_empty_i,
Full => fifo_full_i,
AlmostFull => fifo_almost_full_i);
fifo_data_in_i(31) <= '1'; -- data marker
- fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits
+ fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits
fifo_data_in_i(28 downto 22) <= conv_std_logic_vector(CHANNEL_ID, 7); -- channel number
fifo_data_in_i(21 downto 12) <= fine_counter_i; -- fine time from the encoder
fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge
fifo_data_in_i(10 downto 0) <= hit_time_stamp_i; -- hit time stamp
- Register_Outputs : process (CLK_RD, RESET_RD)
+ Register_Outputs : process (CLK_100, RESET_100)
begin
- if rising_edge(CLK_RD) then
- if RESET_RD = '1' then
+ if rising_edge(CLK_100) then
+ if RESET_100 = '1' then
FIFO_DATA_OUT <= (others => '1');
FIFO_EMPTY_OUT <= '0';
FIFO_FULL_OUT <= '0';
-------------------------------------------------------------------------------
--purpose: Hit Signal Synchroniser
GEN_flipflops : for i in 1 to 3 generate
- Hit_Sync : process (CLK_WR)
+ Hit_Sync : process (CLK_200)
begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
+ if rising_edge(CLK_200) then
+ if RESET_200 = '1' then
sync_q(i) <= '0';
else
sync_q(i) <= sync_q(i-1);
--purpose: Creates a pulse out of the synchronised hit signal
Edge_To_Pulse_Hit : edge_to_pulse
port map (
- clock => CLK_WR,
+ clock => CLK_200,
en_clk => '1',
signal_in => sync_q(3),
pulse => hit_pulse);
--purpose: Counts the detected but unwritten hits
- Lost_Hit_Counter : process (CLK_WR)
+ Lost_Hit_Counter : process (CLK_200)
begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
+ if rising_edge(CLK_200) then
+ if RESET_200 = '1' then
lost_hit_cntr <= (others => '0');
elsif hit_pulse = '1' then
lost_hit_cntr <= lost_hit_cntr + 1;
WIDTH => 24,
DEPTH => 3)
port map (
- RESET => RESET_RD,
- CLK0 => CLK_WR,
- CLK1 => CLK_RD,
+ RESET => RESET_100,
+ CLK0 => CLK_200,
+ CLK1 => CLK_100,
D_IN => lost_hit_cntr,
D_OUT => lost_hit_number_reg);
-- DEBUG
-------------------------------------------------------------------------------
--purpose: Counts the detected hits
- Hit_Detect_Counter : process (CLK_WR)
+ Hit_Detect_Counter : process (CLK_200)
begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
+ if rising_edge(CLK_200) then
+ if RESET_200 = '1' then
hit_detect_cntr <= (others => '0');
elsif hit_pulse = '1' then
hit_detect_cntr <= hit_detect_cntr + 1;
WIDTH => 24,
DEPTH => 3)
port map (
- RESET => RESET_RD,
- CLK0 => CLK_WR,
- CLK1 => CLK_RD,
+ RESET => RESET_100,
+ CLK0 => CLK_200,
+ CLK1 => CLK_100,
D_IN => hit_detect_cntr,
D_OUT => hit_detect_cntr_reg);
HIT_DETECT_NUMBER <= hit_detect_cntr_reg;
--purpose: Counts the encoder start times
- Encoder_Start_Counter : process (CLK_WR)
+ Encoder_Start_Counter : process (CLK_200)
begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
+ if rising_edge(CLK_200) then
+ if RESET_200 = '1' then
encoder_start_cntr <= (others => '0');
elsif encoder_start_i = '1' then
encoder_start_cntr <= encoder_start_cntr + 1;
WIDTH => 24,
DEPTH => 3)
port map (
- RESET => RESET_RD,
- CLK0 => CLK_WR,
- CLK1 => CLK_RD,
+ RESET => RESET_100,
+ CLK0 => CLK_200,
+ CLK1 => CLK_100,
D_IN => encoder_start_cntr,
D_OUT => encoder_start_cntr_reg);
ENCODER_START_NUMBER <= encoder_start_cntr_reg;
--purpose: Counts the written hits
- FIFO_WR_Counter : process (CLK_WR)
+ FIFO_WR_Counter : process (CLK_200)
begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
+ if rising_edge(CLK_200) then
+ if RESET_200 = '1' then
fifo_wr_cntr <= (others => '0');
elsif fifo_wr_en_i = '1' then
fifo_wr_cntr <= fifo_wr_cntr + 1;
WIDTH => 24,
DEPTH => 3)
port map (
- RESET => RESET_RD,
- CLK0 => CLK_WR,
- CLK1 => CLK_RD,
+ RESET => RESET_100,
+ CLK0 => CLK_200,
+ CLK1 => CLK_100,
D_IN => fifo_wr_cntr,
D_OUT => fifo_wr_cntr_reg);
FIFO_WR_NUMBER <= fifo_wr_cntr_reg;
Channel_DEBUG(0) <= HIT_IN;
- Channel_DEBUG(1) <= result_2_reg;
- Channel_DEBUG(2) <= hit_detect_i;
- Channel_DEBUG(3) <= hit_detect_reg;
+ Channel_DEBUG(1) <= result_2_reg when rising_edge(CLK_200);
+ Channel_DEBUG(2) <= hit_detect_i when rising_edge(CLK_200);
+ Channel_DEBUG(3) <= hit_detect_reg when rising_edge(CLK_200);
Channel_DEBUG(4) <= '0';
- Channel_DEBUG(5) <= ff_array_en_i;
- Channel_DEBUG(6) <= encoder_start_i;
- Channel_DEBUG(7) <= fifo_wr_en_i;
- Channel_DEBUG(15 downto 8) <= result_i(7 downto 0);
+ Channel_DEBUG(5) <= ff_array_en_i when rising_edge(CLK_200);
+ Channel_DEBUG(6) <= encoder_start_i when rising_edge(CLK_200);
+ Channel_DEBUG(7) <= fifo_wr_en_i when rising_edge(CLK_200);
+ Channel_DEBUG(15 downto 8) <= result_i(7 downto 0) when rising_edge(CLK_200);
Channel_DEBUG(31 downto 16) <= (others => '0');
-------------------------------------------------------------------------------
-- File : Encoder_304_Bit.vhd
-- Author : Cahit Ugur
-- Created : 2011-11-28
--- Last update: 2012-07-23
+-- Last update: 2012-08-10
-------------------------------------------------------------------------------
-- Description: Encoder for 304 bits
-------------------------------------------------------------------------------
-- synopsys translate_on
entity FIFO_32x32_OutReg is
- port (
- Data: in std_logic_vector(31 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(31 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostFull: out std_logic);
+ port (
+ Data : in std_logic_vector(31 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostFull : out std_logic);
end FIFO_32x32_OutReg;
architecture Structure of FIFO_32x32_OutReg is
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co2: std_logic;
- signal wcount_5: std_logic;
- signal co1: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co2_1: std_logic;
- signal rcount_5: std_logic;
- signal co1_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_4: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal cmp_ci_1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_4: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vhi: std_logic;
- signal iaf_setcount_0: std_logic;
- signal iaf_setcount_1: std_logic;
- signal af_set_ctr_ci: std_logic;
- signal iaf_setcount_2: std_logic;
- signal iaf_setcount_3: std_logic;
- signal co0_4: std_logic;
- signal iaf_setcount_4: std_logic;
- signal iaf_setcount_5: std_logic;
- signal co2_2: std_logic;
- signal af_setcount_5: std_logic;
- signal co1_4: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_2: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal af_setcount_0: std_logic;
- signal af_setcount_1: std_logic;
- signal co0_5: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w3: std_logic;
- signal af_setcount_2: std_logic;
- signal af_setcount_3: std_logic;
- signal co1_5: std_logic;
- signal rcount_w4: std_logic;
- signal af_set_cmp_clr: std_logic;
- signal af_setcount_4: std_logic;
- signal af_set_cmp_set: std_logic;
- signal af_set: std_logic;
- signal af_set_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_32x32_OutReg.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
- attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
+ -- internal signal declarations
+ signal invout_1 : std_logic;
+ signal invout_0 : std_logic;
+ signal w_gdata_0 : std_logic;
+ signal w_gdata_1 : std_logic;
+ signal w_gdata_2 : std_logic;
+ signal w_gdata_3 : std_logic;
+ signal w_gdata_4 : std_logic;
+ signal wptr_0 : std_logic;
+ signal wptr_1 : std_logic;
+ signal wptr_2 : std_logic;
+ signal wptr_3 : std_logic;
+ signal wptr_4 : std_logic;
+ signal wptr_5 : std_logic;
+ signal r_gdata_0 : std_logic;
+ signal r_gdata_1 : std_logic;
+ signal r_gdata_2 : std_logic;
+ signal r_gdata_3 : std_logic;
+ signal r_gdata_4 : std_logic;
+ signal rptr_0 : std_logic;
+ signal rptr_1 : std_logic;
+ signal rptr_2 : std_logic;
+ signal rptr_3 : std_logic;
+ signal rptr_4 : std_logic;
+ signal rptr_5 : std_logic;
+ signal w_gcount_0 : std_logic;
+ signal w_gcount_1 : std_logic;
+ signal w_gcount_2 : std_logic;
+ signal w_gcount_3 : std_logic;
+ signal w_gcount_4 : std_logic;
+ signal w_gcount_5 : std_logic;
+ signal r_gcount_0 : std_logic;
+ signal r_gcount_1 : std_logic;
+ signal r_gcount_2 : std_logic;
+ signal r_gcount_3 : std_logic;
+ signal r_gcount_4 : std_logic;
+ signal r_gcount_5 : std_logic;
+ signal w_gcount_r20 : std_logic;
+ signal w_gcount_r0 : std_logic;
+ signal w_gcount_r21 : std_logic;
+ signal w_gcount_r1 : std_logic;
+ signal w_gcount_r22 : std_logic;
+ signal w_gcount_r2 : std_logic;
+ signal w_gcount_r23 : std_logic;
+ signal w_gcount_r3 : std_logic;
+ signal w_gcount_r24 : std_logic;
+ signal w_gcount_r4 : std_logic;
+ signal w_gcount_r25 : std_logic;
+ signal w_gcount_r5 : std_logic;
+ signal r_gcount_w20 : std_logic;
+ signal r_gcount_w0 : std_logic;
+ signal r_gcount_w21 : std_logic;
+ signal r_gcount_w1 : std_logic;
+ signal r_gcount_w22 : std_logic;
+ signal r_gcount_w2 : std_logic;
+ signal r_gcount_w23 : std_logic;
+ signal r_gcount_w3 : std_logic;
+ signal r_gcount_w24 : std_logic;
+ signal r_gcount_w4 : std_logic;
+ signal r_gcount_w25 : std_logic;
+ signal r_gcount_w5 : std_logic;
+ signal empty_i : std_logic;
+ signal rRst : std_logic;
+ signal full_i : std_logic;
+ signal iwcount_0 : std_logic;
+ signal iwcount_1 : std_logic;
+ signal w_gctr_ci : std_logic;
+ signal iwcount_2 : std_logic;
+ signal iwcount_3 : std_logic;
+ signal co0 : std_logic;
+ signal iwcount_4 : std_logic;
+ signal iwcount_5 : std_logic;
+ signal co2 : std_logic;
+ signal wcount_5 : std_logic;
+ signal co1 : std_logic;
+ signal ircount_0 : std_logic;
+ signal ircount_1 : std_logic;
+ signal r_gctr_ci : std_logic;
+ signal ircount_2 : std_logic;
+ signal ircount_3 : std_logic;
+ signal co0_1 : std_logic;
+ signal ircount_4 : std_logic;
+ signal ircount_5 : std_logic;
+ signal co2_1 : std_logic;
+ signal rcount_5 : std_logic;
+ signal co1_1 : std_logic;
+ signal rden_i : std_logic;
+ signal cmp_ci : std_logic;
+ signal wcount_r0 : std_logic;
+ signal wcount_r1 : std_logic;
+ signal rcount_0 : std_logic;
+ signal rcount_1 : std_logic;
+ signal co0_2 : std_logic;
+ signal w_g2b_xor_cluster_0 : std_logic;
+ signal wcount_r3 : std_logic;
+ signal rcount_2 : std_logic;
+ signal rcount_3 : std_logic;
+ signal co1_2 : std_logic;
+ signal wcount_r4 : std_logic;
+ signal empty_cmp_clr : std_logic;
+ signal rcount_4 : std_logic;
+ signal empty_cmp_set : std_logic;
+ signal empty_d : std_logic;
+ signal empty_d_c : std_logic;
+ signal cmp_ci_1 : std_logic;
+ signal wcount_0 : std_logic;
+ signal wcount_1 : std_logic;
+ signal co0_3 : std_logic;
+ signal wcount_2 : std_logic;
+ signal wcount_3 : std_logic;
+ signal co1_3 : std_logic;
+ signal full_cmp_clr : std_logic;
+ signal wcount_4 : std_logic;
+ signal full_cmp_set : std_logic;
+ signal full_d : std_logic;
+ signal full_d_c : std_logic;
+ signal scuba_vhi : std_logic;
+ signal iaf_setcount_0 : std_logic;
+ signal iaf_setcount_1 : std_logic;
+ signal af_set_ctr_ci : std_logic;
+ signal iaf_setcount_2 : std_logic;
+ signal iaf_setcount_3 : std_logic;
+ signal co0_4 : std_logic;
+ signal iaf_setcount_4 : std_logic;
+ signal iaf_setcount_5 : std_logic;
+ signal co2_2 : std_logic;
+ signal af_setcount_5 : std_logic;
+ signal co1_4 : std_logic;
+ signal wren_i : std_logic;
+ signal cmp_ci_2 : std_logic;
+ signal rcount_w0 : std_logic;
+ signal rcount_w1 : std_logic;
+ signal af_setcount_0 : std_logic;
+ signal af_setcount_1 : std_logic;
+ signal co0_5 : std_logic;
+ signal r_g2b_xor_cluster_0 : std_logic;
+ signal rcount_w3 : std_logic;
+ signal af_setcount_2 : std_logic;
+ signal af_setcount_3 : std_logic;
+ signal co1_5 : std_logic;
+ signal rcount_w4 : std_logic;
+ signal af_set_cmp_clr : std_logic;
+ signal af_setcount_4 : std_logic;
+ signal af_set_cmp_set : std_logic;
+ signal af_set : std_logic;
+ signal af_set_c : std_logic;
+ signal scuba_vlo : std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic;
+ B1 : in std_logic; CI : in std_logic; GE : out std_logic);
+ end component;
+ component AND2
+ port (A : in std_logic; B : in std_logic; Z : out std_logic);
+ end component;
+ component CU2
+ port (CI : in std_logic; PC0 : in std_logic; PC1 : in std_logic;
+ CO : out std_logic; NC0 : out std_logic; NC1 : out std_logic);
+ end component;
+ component FADD2B
+ port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic;
+ B1 : in std_logic; CI : in std_logic; COUT : out std_logic;
+ S0 : out std_logic; S1 : out std_logic);
+ end component;
+ component FD1P3BX
+ port (D : in std_logic; SP : in std_logic; CK : in std_logic;
+ PD : in std_logic; Q : out std_logic);
+ end component;
+ component FD1P3DX
+ port (D : in std_logic; SP : in std_logic; CK : in std_logic;
+ CD : in std_logic; Q : out std_logic);
+ end component;
+ component FD1S3BX
+ port (D : in std_logic; CK : in std_logic; PD : in std_logic;
+ Q : out std_logic);
+ end component;
+ component FD1S3DX
+ port (D : in std_logic; CK : in std_logic; CD : in std_logic;
+ Q : out std_logic);
+ end component;
+ component INV
+ port (A : in std_logic; Z : out std_logic);
+ end component;
+ component OR2
+ port (A : in std_logic; B : in std_logic; Z : out std_logic);
+ end component;
+ component ROM16X1A
+ generic (INITVAL : in std_logic_vector(15 downto 0));
+ port (AD3 : in std_logic; AD2 : in std_logic; AD1 : in std_logic;
+ AD0 : in std_logic; DO0 : out std_logic);
+ end component;
+ component VHI
+ port (Z : out std_logic);
+ end component;
+ component VLO
+ port (Z : out std_logic);
+ end component;
+ component XOR2
+ port (A : in std_logic; B : in std_logic; Z : out std_logic);
+ end component;
+ component PDPW16KC
+ generic (GSR : in string; CSDECODE_R : in string;
+ CSDECODE_W : in string; REGMODE : in string;
+ DATA_WIDTH_R : in integer; DATA_WIDTH_W : in integer);
+ port (DI0 : in std_logic; DI1 : in std_logic; DI2 : in std_logic;
+ DI3 : in std_logic; DI4 : in std_logic; DI5 : in std_logic;
+ DI6 : in std_logic; DI7 : in std_logic; DI8 : in std_logic;
+ DI9 : in std_logic; DI10 : in std_logic; DI11 : in std_logic;
+ DI12 : in std_logic; DI13 : in std_logic;
+ DI14 : in std_logic; DI15 : in std_logic;
+ DI16 : in std_logic; DI17 : in std_logic;
+ DI18 : in std_logic; DI19 : in std_logic;
+ DI20 : in std_logic; DI21 : in std_logic;
+ DI22 : in std_logic; DI23 : in std_logic;
+ DI24 : in std_logic; DI25 : in std_logic;
+ DI26 : in std_logic; DI27 : in std_logic;
+ DI28 : in std_logic; DI29 : in std_logic;
+ DI30 : in std_logic; DI31 : in std_logic;
+ DI32 : in std_logic; DI33 : in std_logic;
+ DI34 : in std_logic; DI35 : in std_logic;
+ ADW0 : in std_logic; ADW1 : in std_logic;
+ ADW2 : in std_logic; ADW3 : in std_logic;
+ ADW4 : in std_logic; ADW5 : in std_logic;
+ ADW6 : in std_logic; ADW7 : in std_logic;
+ ADW8 : in std_logic; BE0 : in std_logic; BE1 : in std_logic;
+ BE2 : in std_logic; BE3 : in std_logic; CEW : in std_logic;
+ CLKW : in std_logic; CSW0 : in std_logic;
+ CSW1 : in std_logic; CSW2 : in std_logic;
+ ADR0 : in std_logic; ADR1 : in std_logic;
+ ADR2 : in std_logic; ADR3 : in std_logic;
+ ADR4 : in std_logic; ADR5 : in std_logic;
+ ADR6 : in std_logic; ADR7 : in std_logic;
+ ADR8 : in std_logic; ADR9 : in std_logic;
+ ADR10 : in std_logic; ADR11 : in std_logic;
+ ADR12 : in std_logic; ADR13 : in std_logic;
+ CER : in std_logic; CLKR : in std_logic; CSR0 : in std_logic;
+ CSR1 : in std_logic; CSR2 : in std_logic; RST : in std_logic;
+ DO0 : out std_logic; DO1 : out std_logic;
+ DO2 : out std_logic; DO3 : out std_logic;
+ DO4 : out std_logic; DO5 : out std_logic;
+ DO6 : out std_logic; DO7 : out std_logic;
+ DO8 : out std_logic; DO9 : out std_logic;
+ DO10 : out std_logic; DO11 : out std_logic;
+ DO12 : out std_logic; DO13 : out std_logic;
+ DO14 : out std_logic; DO15 : out std_logic;
+ DO16 : out std_logic; DO17 : out std_logic;
+ DO18 : out std_logic; DO19 : out std_logic;
+ DO20 : out std_logic; DO21 : out std_logic;
+ DO22 : out std_logic; DO23 : out std_logic;
+ DO24 : out std_logic; DO25 : out std_logic;
+ DO26 : out std_logic; DO27 : out std_logic;
+ DO28 : out std_logic; DO29 : out std_logic;
+ DO30 : out std_logic; DO31 : out std_logic;
+ DO32 : out std_logic; DO33 : out std_logic;
+ DO34 : out std_logic; DO35 : out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_32x32_OutReg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
begin
- -- component instantiation statements
- AND2_t12: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+ -- component instantiation statements
+ AND2_t12 : AND2
+ port map (A => WrEn, B => invout_1, Z => wren_i);
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
+ INV_1 : INV
+ port map (A => full_i, Z => invout_1);
- AND2_t11: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+ AND2_t11 : AND2
+ port map (A => RdEn, B => invout_0, Z => rden_i);
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
+ INV_0 : INV
+ port map (A => empty_i, Z => invout_0);
- OR2_t10: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t9: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+ OR2_t10 : OR2
+ port map (A => Reset, B => RPReset, Z => rRst);
+
+ XOR2_t9 : XOR2
+ port map (A => wcount_0, B => wcount_1, Z => w_gdata_0);
- XOR2_t8: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t7: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t6: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t5: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t4: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t3: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t2: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t1: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t0: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>w_gcount_r25,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>scuba_vlo, DO0=>wcount_r3);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>wcount_r4, DO0=>wcount_r1);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>r_gcount_w25,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
- AD1=>r_gcount_w25, AD0=>scuba_vlo, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>rcount_w4, DO0=>rcount_w1);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_5, AD2=>rcount_5, AD1=>w_gcount_r25,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_5, AD2=>rcount_5, AD1=>w_gcount_r25,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_5, AD2=>wcount_5, AD1=>r_gcount_w25,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_5, AD2=>wcount_5, AD1=>r_gcount_w25,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"4c32")
- port map (AD3=>af_setcount_5, AD2=>wcount_5, AD1=>r_gcount_w25,
- AD0=>wptr_5, DO0=>af_set_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"8001")
- port map (AD3=>af_setcount_5, AD2=>wcount_5, AD1=>r_gcount_w25,
- AD0=>wptr_5, DO0=>af_set_cmp_clr);
-
- pdp_ram_0_0_0: PDPW16KC
- generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo,
- DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
- ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3,
- ADW4=>wptr_4, ADW5=>scuba_vlo, ADW6=>scuba_vlo,
- ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi,
- BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i,
- CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo,
- CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
- ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
- ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3,
- ADR9=>rptr_4, ADR10=>scuba_vlo, ADR11=>scuba_vlo,
- ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>scuba_vhi,
- CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19),
- DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24),
- DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29),
- DO12=>Q(30), DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open,
- DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3),
- DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8),
- DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12),
- DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16),
- DO35=>Q(17));
-
- FF_68: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_67: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_66: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_65: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_64: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_63: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_62: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_61: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_60: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_59: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_58: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_57: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_56: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_55: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_54: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_53: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_52: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_51: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_50: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_49: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_48: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
+ XOR2_t8 : XOR2
+ port map (A => wcount_1, B => wcount_2, Z => w_gdata_1);
+
+ XOR2_t7 : XOR2
+ port map (A => wcount_2, B => wcount_3, Z => w_gdata_2);
+
+ XOR2_t6 : XOR2
+ port map (A => wcount_3, B => wcount_4, Z => w_gdata_3);
+
+ XOR2_t5 : XOR2
+ port map (A => wcount_4, B => wcount_5, Z => w_gdata_4);
+
+ XOR2_t4 : XOR2
+ port map (A => rcount_0, B => rcount_1, Z => r_gdata_0);
+
+ XOR2_t3 : XOR2
+ port map (A => rcount_1, B => rcount_2, Z => r_gdata_1);
+
+ XOR2_t2 : XOR2
+ port map (A => rcount_2, B => rcount_3, Z => r_gdata_2);
+
+ XOR2_t1 : XOR2
+ port map (A => rcount_3, B => rcount_4, Z => r_gdata_3);
+
+ XOR2_t0 : XOR2
+ port map (A => rcount_4, B => rcount_5, Z => r_gdata_4);
+
+ LUT4_15 : ROM16X1A
+ generic map (initval => X"6996")
+ port map (AD3 => w_gcount_r22, AD2 => w_gcount_r23,
+ AD1 => w_gcount_r24, AD0 => w_gcount_r25,
+ DO0 => w_g2b_xor_cluster_0);
+
+ LUT4_14 : ROM16X1A
+ generic map (initval => X"6996")
+ port map (AD3 => w_gcount_r24, AD2 => w_gcount_r25, AD1 => scuba_vlo,
+ AD0 => scuba_vlo, DO0 => wcount_r4);
+
+ LUT4_13 : ROM16X1A
+ generic map (initval => X"6996")
+ port map (AD3 => w_gcount_r23, AD2 => w_gcount_r24,
+ AD1 => w_gcount_r25, AD0 => scuba_vlo, DO0 => wcount_r3);
+
+ LUT4_12 : ROM16X1A
+ generic map (initval => X"6996")
+ port map (AD3 => w_gcount_r21, AD2 => w_gcount_r22,
+ AD1 => w_gcount_r23, AD0 => wcount_r4, DO0 => wcount_r1);
+
+ LUT4_11 : ROM16X1A
+ generic map (initval => X"6996")
+ port map (AD3 => w_gcount_r20, AD2 => w_gcount_r21,
+ AD1 => w_gcount_r22, AD0 => wcount_r3, DO0 => wcount_r0);
+
+ LUT4_10 : ROM16X1A
+ generic map (initval => X"6996")
+ port map (AD3 => r_gcount_w22, AD2 => r_gcount_w23,
+ AD1 => r_gcount_w24, AD0 => r_gcount_w25,
+ DO0 => r_g2b_xor_cluster_0);
+
+ LUT4_9 : ROM16X1A
+ generic map (initval => X"6996")
+ port map (AD3 => r_gcount_w24, AD2 => r_gcount_w25, AD1 => scuba_vlo,
+ AD0 => scuba_vlo, DO0 => rcount_w4);
+
+ LUT4_8 : ROM16X1A
+ generic map (initval => X"6996")
+ port map (AD3 => r_gcount_w23, AD2 => r_gcount_w24,
+ AD1 => r_gcount_w25, AD0 => scuba_vlo, DO0 => rcount_w3);
+
+ LUT4_7 : ROM16X1A
+ generic map (initval => X"6996")
+ port map (AD3 => r_gcount_w21, AD2 => r_gcount_w22,
+ AD1 => r_gcount_w23, AD0 => rcount_w4, DO0 => rcount_w1);
+
+ LUT4_6 : ROM16X1A
+ generic map (initval => X"6996")
+ port map (AD3 => r_gcount_w20, AD2 => r_gcount_w21,
+ AD1 => r_gcount_w22, AD0 => rcount_w3, DO0 => rcount_w0);
+
+ LUT4_5 : ROM16X1A
+ generic map (initval => X"0410")
+ port map (AD3 => rptr_5, AD2 => rcount_5, AD1 => w_gcount_r25,
+ AD0 => scuba_vlo, DO0 => empty_cmp_set);
+
+ LUT4_4 : ROM16X1A
+ generic map (initval => X"1004")
+ port map (AD3 => rptr_5, AD2 => rcount_5, AD1 => w_gcount_r25,
+ AD0 => scuba_vlo, DO0 => empty_cmp_clr);
+
+ LUT4_3 : ROM16X1A
+ generic map (initval => X"0140")
+ port map (AD3 => wptr_5, AD2 => wcount_5, AD1 => r_gcount_w25,
+ AD0 => scuba_vlo, DO0 => full_cmp_set);
+
+ LUT4_2 : ROM16X1A
+ generic map (initval => X"4001")
+ port map (AD3 => wptr_5, AD2 => wcount_5, AD1 => r_gcount_w25,
+ AD0 => scuba_vlo, DO0 => full_cmp_clr);
+
+ LUT4_1 : ROM16X1A
+ generic map (initval => X"4c32")
+ port map (AD3 => af_setcount_5, AD2 => wcount_5, AD1 => r_gcount_w25,
+ AD0 => wptr_5, DO0 => af_set_cmp_set);
+
+ LUT4_0 : ROM16X1A
+ generic map (initval => X"8001")
+ port map (AD3 => af_setcount_5, AD2 => wcount_5, AD1 => r_gcount_w25,
+ AD0 => wptr_5, DO0 => af_set_cmp_clr);
+
+ pdp_ram_0_0_0 : PDPW16KC
+ generic map (CSDECODE_R => "0b001", CSDECODE_W => "0b001", GSR => "DISABLED",
+ REGMODE => "OUTREG", DATA_WIDTH_R => 36, DATA_WIDTH_W => 36)
+ port map (DI0 => Data(0), DI1 => Data(1), DI2 => Data(2), DI3 => Data(3),
+ DI4 => Data(4), DI5 => Data(5), DI6 => Data(6), DI7 => Data(7),
+ DI8 => Data(8), DI9 => Data(9), DI10 => Data(10), DI11 => Data(11),
+ DI12 => Data(12), DI13 => Data(13), DI14 => Data(14),
+ DI15 => Data(15), DI16 => Data(16), DI17 => Data(17),
+ DI18 => Data(18), DI19 => Data(19), DI20 => Data(20),
+ DI21 => Data(21), DI22 => Data(22), DI23 => Data(23),
+ DI24 => Data(24), DI25 => Data(25), DI26 => Data(26),
+ DI27 => Data(27), DI28 => Data(28), DI29 => Data(29),
+ DI30 => Data(30), DI31 => Data(31), DI32 => scuba_vlo,
+ DI33 => scuba_vlo, DI34 => scuba_vlo, DI35 => scuba_vlo,
+ ADW0 => wptr_0, ADW1 => wptr_1, ADW2 => wptr_2, ADW3 => wptr_3,
+ ADW4 => wptr_4, ADW5 => scuba_vlo, ADW6 => scuba_vlo,
+ ADW7 => scuba_vlo, ADW8 => scuba_vlo, BE0 => scuba_vhi,
+ BE1 => scuba_vhi, BE2 => scuba_vhi, BE3 => scuba_vhi, CEW => wren_i,
+ CLKW => WrClock, CSW0 => scuba_vhi, CSW1 => scuba_vlo,
+ CSW2 => scuba_vlo, ADR0 => scuba_vlo, ADR1 => scuba_vlo,
+ ADR2 => scuba_vlo, ADR3 => scuba_vlo, ADR4 => scuba_vlo,
+ ADR5 => rptr_0, ADR6 => rptr_1, ADR7 => rptr_2, ADR8 => rptr_3,
+ ADR9 => rptr_4, ADR10 => scuba_vlo, ADR11 => scuba_vlo,
+ ADR12 => scuba_vlo, ADR13 => scuba_vlo, CER => scuba_vhi,
+ CLKR => RdClock, CSR0 => rden_i, CSR1 => scuba_vlo,
+ CSR2 => scuba_vlo, RST => Reset, DO0 => Q(18), DO1 => Q(19),
+ DO2 => Q(20), DO3 => Q(21), DO4 => Q(22), DO5 => Q(23), DO6 => Q(24),
+ DO7 => Q(25), DO8 => Q(26), DO9 => Q(27), DO10 => Q(28), DO11 => Q(29),
+ DO12 => Q(30), DO13 => Q(31), DO14 => open, DO15 => open, DO16 => open,
+ DO17 => open, DO18 => Q(0), DO19 => Q(1), DO20 => Q(2), DO21 => Q(3),
+ DO22 => Q(4), DO23 => Q(5), DO24 => Q(6), DO25 => Q(7), DO26 => Q(8),
+ DO27 => Q(9), DO28 => Q(10), DO29 => Q(11), DO30 => Q(12),
+ DO31 => Q(13), DO32 => Q(14), DO33 => Q(15), DO34 => Q(16),
+ DO35 => Q(17));
+
+ FF_68 : FD1P3BX
+ port map (D => iwcount_0, SP => wren_i, CK => WrClock, PD => Reset,
+ Q => wcount_0);
+
+ FF_67 : FD1P3DX
+ port map (D => iwcount_1, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => wcount_1);
+
+ FF_66 : FD1P3DX
+ port map (D => iwcount_2, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => wcount_2);
+
+ FF_65 : FD1P3DX
+ port map (D => iwcount_3, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => wcount_3);
+
+ FF_64 : FD1P3DX
+ port map (D => iwcount_4, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => wcount_4);
+
+ FF_63 : FD1P3DX
+ port map (D => iwcount_5, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => wcount_5);
+
+ FF_62 : FD1P3DX
+ port map (D => w_gdata_0, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => w_gcount_0);
+
+ FF_61 : FD1P3DX
+ port map (D => w_gdata_1, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => w_gcount_1);
+
+ FF_60 : FD1P3DX
+ port map (D => w_gdata_2, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => w_gcount_2);
+
+ FF_59 : FD1P3DX
+ port map (D => w_gdata_3, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => w_gcount_3);
+
+ FF_58 : FD1P3DX
+ port map (D => w_gdata_4, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => w_gcount_4);
+
+ FF_57 : FD1P3DX
+ port map (D => wcount_5, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => w_gcount_5);
+
+ FF_56 : FD1P3DX
+ port map (D => wcount_0, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => wptr_0);
+
+ FF_55 : FD1P3DX
+ port map (D => wcount_1, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => wptr_1);
+
+ FF_54 : FD1P3DX
+ port map (D => wcount_2, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => wptr_2);
+
+ FF_53 : FD1P3DX
+ port map (D => wcount_3, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => wptr_3);
+
+ FF_52 : FD1P3DX
+ port map (D => wcount_4, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => wptr_4);
+
+ FF_51 : FD1P3DX
+ port map (D => wcount_5, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => wptr_5);
+
+ FF_50 : FD1P3BX
+ port map (D => ircount_0, SP => rden_i, CK => RdClock, PD => rRst,
+ Q => rcount_0);
+
+ FF_49 : FD1P3DX
+ port map (D => ircount_1, SP => rden_i, CK => RdClock, CD => rRst,
+ Q => rcount_1);
+
+ FF_48 : FD1P3DX
+ port map (D => ircount_2, SP => rden_i, CK => RdClock, CD => rRst,
+ Q => rcount_2);
- FF_47: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
+ FF_47 : FD1P3DX
+ port map (D => ircount_3, SP => rden_i, CK => RdClock, CD => rRst,
+ Q => rcount_3);
- FF_46: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
+ FF_46 : FD1P3DX
+ port map (D => ircount_4, SP => rden_i, CK => RdClock, CD => rRst,
+ Q => rcount_4);
- FF_45: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
+ FF_45 : FD1P3DX
+ port map (D => ircount_5, SP => rden_i, CK => RdClock, CD => rRst,
+ Q => rcount_5);
- FF_44: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
+ FF_44 : FD1P3DX
+ port map (D => r_gdata_0, SP => rden_i, CK => RdClock, CD => rRst,
+ Q => r_gcount_0);
- FF_43: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
+ FF_43 : FD1P3DX
+ port map (D => r_gdata_1, SP => rden_i, CK => RdClock, CD => rRst,
+ Q => r_gcount_1);
- FF_42: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
+ FF_42 : FD1P3DX
+ port map (D => r_gdata_2, SP => rden_i, CK => RdClock, CD => rRst,
+ Q => r_gcount_2);
- FF_41: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
+ FF_41 : FD1P3DX
+ port map (D => r_gdata_3, SP => rden_i, CK => RdClock, CD => rRst,
+ Q => r_gcount_3);
- FF_40: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
+ FF_40 : FD1P3DX
+ port map (D => r_gdata_4, SP => rden_i, CK => RdClock, CD => rRst,
+ Q => r_gcount_4);
- FF_39: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
+ FF_39 : FD1P3DX
+ port map (D => rcount_5, SP => rden_i, CK => RdClock, CD => rRst,
+ Q => r_gcount_5);
- FF_38: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
+ FF_38 : FD1P3DX
+ port map (D => rcount_0, SP => rden_i, CK => RdClock, CD => rRst,
+ Q => rptr_0);
- FF_37: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
+ FF_37 : FD1P3DX
+ port map (D => rcount_1, SP => rden_i, CK => RdClock, CD => rRst,
+ Q => rptr_1);
- FF_36: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
+ FF_36 : FD1P3DX
+ port map (D => rcount_2, SP => rden_i, CK => RdClock, CD => rRst,
+ Q => rptr_2);
- FF_35: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
+ FF_35 : FD1P3DX
+ port map (D => rcount_3, SP => rden_i, CK => RdClock, CD => rRst,
+ Q => rptr_3);
- FF_34: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
+ FF_34 : FD1P3DX
+ port map (D => rcount_4, SP => rden_i, CK => RdClock, CD => rRst,
+ Q => rptr_4);
- FF_33: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
+ FF_33 : FD1P3DX
+ port map (D => rcount_5, SP => rden_i, CK => RdClock, CD => rRst,
+ Q => rptr_5);
- FF_32: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+ FF_32 : FD1S3DX
+ port map (D => w_gcount_0, CK => RdClock, CD => Reset, Q => w_gcount_r0);
- FF_31: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+ FF_31 : FD1S3DX
+ port map (D => w_gcount_1, CK => RdClock, CD => Reset, Q => w_gcount_r1);
- FF_30: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+ FF_30 : FD1S3DX
+ port map (D => w_gcount_2, CK => RdClock, CD => Reset, Q => w_gcount_r2);
- FF_29: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+ FF_29 : FD1S3DX
+ port map (D => w_gcount_3, CK => RdClock, CD => Reset, Q => w_gcount_r3);
- FF_28: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+ FF_28 : FD1S3DX
+ port map (D => w_gcount_4, CK => RdClock, CD => Reset, Q => w_gcount_r4);
- FF_27: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+ FF_27 : FD1S3DX
+ port map (D => w_gcount_5, CK => RdClock, CD => Reset, Q => w_gcount_r5);
- FF_26: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+ FF_26 : FD1S3DX
+ port map (D => r_gcount_0, CK => WrClock, CD => rRst, Q => r_gcount_w0);
- FF_25: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+ FF_25 : FD1S3DX
+ port map (D => r_gcount_1, CK => WrClock, CD => rRst, Q => r_gcount_w1);
- FF_24: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+ FF_24 : FD1S3DX
+ port map (D => r_gcount_2, CK => WrClock, CD => rRst, Q => r_gcount_w2);
- FF_23: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+ FF_23 : FD1S3DX
+ port map (D => r_gcount_3, CK => WrClock, CD => rRst, Q => r_gcount_w3);
- FF_22: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+ FF_22 : FD1S3DX
+ port map (D => r_gcount_4, CK => WrClock, CD => rRst, Q => r_gcount_w4);
- FF_21: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+ FF_21 : FD1S3DX
+ port map (D => r_gcount_5, CK => WrClock, CD => rRst, Q => r_gcount_w5);
- FF_20: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
+ FF_20 : FD1S3DX
+ port map (D => w_gcount_r0, CK => RdClock, CD => Reset,
+ Q => w_gcount_r20);
- FF_19: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
+ FF_19 : FD1S3DX
+ port map (D => w_gcount_r1, CK => RdClock, CD => Reset,
+ Q => w_gcount_r21);
- FF_18: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
+ FF_18 : FD1S3DX
+ port map (D => w_gcount_r2, CK => RdClock, CD => Reset,
+ Q => w_gcount_r22);
- FF_17: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
+ FF_17 : FD1S3DX
+ port map (D => w_gcount_r3, CK => RdClock, CD => Reset,
+ Q => w_gcount_r23);
- FF_16: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
+ FF_16 : FD1S3DX
+ port map (D => w_gcount_r4, CK => RdClock, CD => Reset,
+ Q => w_gcount_r24);
- FF_15: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
+ FF_15 : FD1S3DX
+ port map (D => w_gcount_r5, CK => RdClock, CD => Reset,
+ Q => w_gcount_r25);
- FF_14: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+ FF_14 : FD1S3DX
+ port map (D => r_gcount_w0, CK => WrClock, CD => rRst, Q => r_gcount_w20);
- FF_13: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+ FF_13 : FD1S3DX
+ port map (D => r_gcount_w1, CK => WrClock, CD => rRst, Q => r_gcount_w21);
- FF_12: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+ FF_12 : FD1S3DX
+ port map (D => r_gcount_w2, CK => WrClock, CD => rRst, Q => r_gcount_w22);
- FF_11: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+ FF_11 : FD1S3DX
+ port map (D => r_gcount_w3, CK => WrClock, CD => rRst, Q => r_gcount_w23);
- FF_10: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+ FF_10 : FD1S3DX
+ port map (D => r_gcount_w4, CK => WrClock, CD => rRst, Q => r_gcount_w24);
- FF_9: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+ FF_9 : FD1S3DX
+ port map (D => r_gcount_w5, CK => WrClock, CD => rRst, Q => r_gcount_w25);
- FF_8: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+ FF_8 : FD1S3BX
+ port map (D => empty_d, CK => RdClock, PD => rRst, Q => empty_i);
- FF_7: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+ FF_7 : FD1S3DX
+ port map (D => full_d, CK => WrClock, CD => Reset, Q => full_i);
- FF_6: FD1P3BX
- port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_setcount_0);
+ FF_6 : FD1P3BX
+ port map (D => iaf_setcount_0, SP => wren_i, CK => WrClock, PD => Reset,
+ Q => af_setcount_0);
- FF_5: FD1P3DX
- port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_1);
+ FF_5 : FD1P3DX
+ port map (D => iaf_setcount_1, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => af_setcount_1);
- FF_4: FD1P3BX
- port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>af_setcount_2);
+ FF_4 : FD1P3BX
+ port map (D => iaf_setcount_2, SP => wren_i, CK => WrClock, PD => Reset,
+ Q => af_setcount_2);
- FF_3: FD1P3DX
- port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_3);
+ FF_3 : FD1P3DX
+ port map (D => iaf_setcount_3, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => af_setcount_3);
- FF_2: FD1P3DX
- port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_4);
+ FF_2 : FD1P3DX
+ port map (D => iaf_setcount_4, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => af_setcount_4);
- FF_1: FD1P3DX
- port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>af_setcount_5);
+ FF_1 : FD1P3DX
+ port map (D => iaf_setcount_5, SP => wren_i, CK => WrClock, CD => Reset,
+ Q => af_setcount_5);
- FF_0: FD1S3DX
- port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
+ FF_0 : FD1S3DX
+ port map (D => af_set, CK => WrClock, CD => Reset, Q => AlmostFull);
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
+ w_gctr_cia : FADD2B
+ port map (A0 => scuba_vlo, A1 => scuba_vhi, B0 => scuba_vlo,
+ B1 => scuba_vhi, CI => scuba_vlo, COUT => w_gctr_ci, S0 => open,
+ S1 => open);
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
+ w_gctr_0 : CU2
+ port map (CI => w_gctr_ci, PC0 => wcount_0, PC1 => wcount_1, CO => co0,
+ NC0 => iwcount_0, NC1 => iwcount_1);
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
+ w_gctr_1 : CU2
+ port map (CI => co0, PC0 => wcount_2, PC1 => wcount_3, CO => co1,
+ NC0 => iwcount_2, NC1 => iwcount_3);
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
+ w_gctr_2 : CU2
+ port map (CI => co1, PC0 => wcount_4, PC1 => wcount_5, CO => co2,
+ NC0 => iwcount_4, NC1 => iwcount_5);
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
+ r_gctr_cia : FADD2B
+ port map (A0 => scuba_vlo, A1 => scuba_vhi, B0 => scuba_vlo,
+ B1 => scuba_vhi, CI => scuba_vlo, COUT => r_gctr_ci, S0 => open,
+ S1 => open);
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
+ r_gctr_0 : CU2
+ port map (CI => r_gctr_ci, PC0 => rcount_0, PC1 => rcount_1, CO => co0_1,
+ NC0 => ircount_0, NC1 => ircount_1);
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
+ r_gctr_1 : CU2
+ port map (CI => co0_1, PC0 => rcount_2, PC1 => rcount_3, CO => co1_1,
+ NC0 => ircount_2, NC1 => ircount_3);
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
+ r_gctr_2 : CU2
+ port map (CI => co1_1, PC0 => rcount_4, PC1 => rcount_5, CO => co2_1,
+ NC0 => ircount_4, NC1 => ircount_5);
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+ empty_cmp_ci_a : FADD2B
+ port map (A0 => scuba_vlo, A1 => rden_i, B0 => scuba_vlo, B1 => rden_i,
+ CI => scuba_vlo, COUT => cmp_ci, S0 => open, S1 => open);
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
+ empty_cmp_0 : AGEB2
+ port map (A0 => rcount_0, A1 => rcount_1, B0 => wcount_r0,
+ B1 => wcount_r1, CI => cmp_ci, GE => co0_2);
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
+ empty_cmp_1 : AGEB2
+ port map (A0 => rcount_2, A1 => rcount_3, B0 => w_g2b_xor_cluster_0,
+ B1 => wcount_r3, CI => co0_2, GE => co1_2);
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>empty_cmp_set, B0=>wcount_r4,
- B1=>empty_cmp_clr, CI=>co1_2, GE=>empty_d_c);
+ empty_cmp_2 : AGEB2
+ port map (A0 => rcount_4, A1 => empty_cmp_set, B0 => wcount_r4,
+ B1 => empty_cmp_clr, CI => co1_2, GE => empty_d_c);
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
+ a0 : FADD2B
+ port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo,
+ B1 => scuba_vlo, CI => empty_d_c, COUT => open, S0 => empty_d,
+ S1 => open);
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+ full_cmp_ci_a : FADD2B
+ port map (A0 => scuba_vlo, A1 => wren_i, B0 => scuba_vlo, B1 => wren_i,
+ CI => scuba_vlo, COUT => cmp_ci_1, S0 => open, S1 => open);
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
+ full_cmp_0 : AGEB2
+ port map (A0 => wcount_0, A1 => wcount_1, B0 => rcount_w0,
+ B1 => rcount_w1, CI => cmp_ci_1, GE => co0_3);
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
+ full_cmp_1 : AGEB2
+ port map (A0 => wcount_2, A1 => wcount_3, B0 => r_g2b_xor_cluster_0,
+ B1 => rcount_w3, CI => co0_3, GE => co1_3);
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>full_cmp_set, B0=>rcount_w4,
- B1=>full_cmp_clr, CI=>co1_3, GE=>full_d_c);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- af_set_ctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open,
- S1=>open);
-
- af_set_ctr_0: CU2
- port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0,
- PC1=>af_setcount_1, CO=>co0_4, NC0=>iaf_setcount_0,
- NC1=>iaf_setcount_1);
+ full_cmp_2 : AGEB2
+ port map (A0 => wcount_4, A1 => full_cmp_set, B0 => rcount_w4,
+ B1 => full_cmp_clr, CI => co1_3, GE => full_d_c);
+
+ a1 : FADD2B
+ port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo,
+ B1 => scuba_vlo, CI => full_d_c, COUT => open, S0 => full_d,
+ S1 => open);
+
+ scuba_vhi_inst : VHI
+ port map (Z => scuba_vhi);
+
+ af_set_ctr_cia : FADD2B
+ port map (A0 => scuba_vlo, A1 => scuba_vhi, B0 => scuba_vlo,
+ B1 => scuba_vhi, CI => scuba_vlo, COUT => af_set_ctr_ci, S0 => open,
+ S1 => open);
+
+ af_set_ctr_0 : CU2
+ port map (CI => af_set_ctr_ci, PC0 => af_setcount_0,
+ PC1 => af_setcount_1, CO => co0_4, NC0 => iaf_setcount_0,
+ NC1 => iaf_setcount_1);
- af_set_ctr_1: CU2
- port map (CI=>co0_4, PC0=>af_setcount_2, PC1=>af_setcount_3,
- CO=>co1_4, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3);
+ af_set_ctr_1 : CU2
+ port map (CI => co0_4, PC0 => af_setcount_2, PC1 => af_setcount_3,
+ CO => co1_4, NC0 => iaf_setcount_2, NC1 => iaf_setcount_3);
- af_set_ctr_2: CU2
- port map (CI=>co1_4, PC0=>af_setcount_4, PC1=>af_setcount_5,
- CO=>co2_2, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5);
+ af_set_ctr_2 : CU2
+ port map (CI => co1_4, PC0 => af_setcount_4, PC1 => af_setcount_5,
+ CO => co2_2, NC0 => iaf_setcount_4, NC1 => iaf_setcount_5);
- af_set_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
-
- af_set_cmp_0: AGEB2
- port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_2, GE=>co0_5);
+ af_set_cmp_ci_a : FADD2B
+ port map (A0 => scuba_vlo, A1 => wren_i, B0 => scuba_vlo, B1 => wren_i,
+ CI => scuba_vlo, COUT => cmp_ci_2, S0 => open, S1 => open);
+
+ af_set_cmp_0 : AGEB2
+ port map (A0 => af_setcount_0, A1 => af_setcount_1, B0 => rcount_w0,
+ B1 => rcount_w1, CI => cmp_ci_2, GE => co0_5);
- af_set_cmp_1: AGEB2
- port map (A0=>af_setcount_2, A1=>af_setcount_3,
- B0=>r_g2b_xor_cluster_0, B1=>rcount_w3, CI=>co0_5, GE=>co1_5);
+ af_set_cmp_1 : AGEB2
+ port map (A0 => af_setcount_2, A1 => af_setcount_3,
+ B0 => r_g2b_xor_cluster_0, B1 => rcount_w3, CI => co0_5, GE => co1_5);
- af_set_cmp_2: AGEB2
- port map (A0=>af_setcount_4, A1=>af_set_cmp_set, B0=>rcount_w4,
- B1=>af_set_cmp_clr, CI=>co1_5, GE=>af_set_c);
+ af_set_cmp_2 : AGEB2
+ port map (A0 => af_setcount_4, A1 => af_set_cmp_set, B0 => rcount_w4,
+ B1 => af_set_cmp_clr, CI => co1_5, GE => af_set_c);
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a2: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
- S1=>open);
+ scuba_vlo_inst : VLO
+ port map (Z => scuba_vlo);
+
+ a2 : FADD2B
+ port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo,
+ B1 => scuba_vlo, CI => af_set_c, COUT => open, S0 => af_set,
+ S1 => open);
- Empty <= empty_i;
- Full <= full_i;
+ Empty <= empty_i;
+ Full <= full_i;
end Structure;
-- synopsys translate_off
library ecp3;
configuration Structure_CON of FIFO_32x32_OutReg is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
+ for Structure
+ for all : AGEB2 use entity ecp3.AGEB2(V); end for;
+ for all : AND2 use entity ecp3.AND2(V); end for;
+ for all : CU2 use entity ecp3.CU2(V); end for;
+ for all : FADD2B use entity ecp3.FADD2B(V); end for;
+ for all : FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+ for all : FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+ for all : FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+ for all : FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+ for all : INV use entity ecp3.INV(V); end for;
+ for all : OR2 use entity ecp3.OR2(V); end for;
+ for all : ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+ for all : VHI use entity ecp3.VHI(V); end for;
+ for all : VLO use entity ecp3.VLO(V); end for;
+ for all : XOR2 use entity ecp3.XOR2(V); end for;
+ for all : PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+ end for;
end Structure_CON;
-- synopsys translate_on
-- synopsys translate_on
entity ROM_FIFO is
- port (
- Address: in std_logic_vector(7 downto 0);
- OutClock: in std_logic;
- OutClockEn: in std_logic;
- Reset: in std_logic;
- Q: out std_logic_vector(3 downto 0));
+ port (
+ Address : in std_logic_vector(7 downto 0);
+ OutClock : in std_logic;
+ OutClockEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(3 downto 0));
end ROM_FIFO;
architecture Structure of ROM_FIFO is
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
+ -- internal signal declarations
+ signal scuba_vhi : std_logic;
+ signal scuba_vlo : std_logic;
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component DP16KC
- generic (INITVAL_3F : in String; INITVAL_3E : in String;
- INITVAL_3D : in String; INITVAL_3C : in String;
- INITVAL_3B : in String; INITVAL_3A : in String;
- INITVAL_39 : in String; INITVAL_38 : in String;
- INITVAL_37 : in String; INITVAL_36 : in String;
- INITVAL_35 : in String; INITVAL_34 : in String;
- INITVAL_33 : in String; INITVAL_32 : in String;
- INITVAL_31 : in String; INITVAL_30 : in String;
- INITVAL_2F : in String; INITVAL_2E : in String;
- INITVAL_2D : in String; INITVAL_2C : in String;
- INITVAL_2B : in String; INITVAL_2A : in String;
- INITVAL_29 : in String; INITVAL_28 : in String;
- INITVAL_27 : in String; INITVAL_26 : in String;
- INITVAL_25 : in String; INITVAL_24 : in String;
- INITVAL_23 : in String; INITVAL_22 : in String;
- INITVAL_21 : in String; INITVAL_20 : in String;
- INITVAL_1F : in String; INITVAL_1E : in String;
- INITVAL_1D : in String; INITVAL_1C : in String;
- INITVAL_1B : in String; INITVAL_1A : in String;
- INITVAL_19 : in String; INITVAL_18 : in String;
- INITVAL_17 : in String; INITVAL_16 : in String;
- INITVAL_15 : in String; INITVAL_14 : in String;
- INITVAL_13 : in String; INITVAL_12 : in String;
- INITVAL_11 : in String; INITVAL_10 : in String;
- INITVAL_0F : in String; INITVAL_0E : in String;
- INITVAL_0D : in String; INITVAL_0C : in String;
- INITVAL_0B : in String; INITVAL_0A : in String;
- INITVAL_09 : in String; INITVAL_08 : in String;
- INITVAL_07 : in String; INITVAL_06 : in String;
- INITVAL_05 : in String; INITVAL_04 : in String;
- INITVAL_03 : in String; INITVAL_02 : in String;
- INITVAL_01 : in String; INITVAL_00 : in String;
- GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute MEM_LPC_FILE of ROM_FIFO_0_0_0 : label is "ROM_FIFO.lpc";
- attribute MEM_INIT_FILE of ROM_FIFO_0_0_0 : label is "rom0_mem_file.mem";
- attribute RESETMODE of ROM_FIFO_0_0_0 : label is "SYNC";
+ -- local component declarations
+ component VHI
+ port (Z : out std_logic);
+ end component;
+ component VLO
+ port (Z : out std_logic);
+ end component;
+ component DP16KC
+ generic (INITVAL_3F : in string; INITVAL_3E : in string;
+ INITVAL_3D : in string; INITVAL_3C : in string;
+ INITVAL_3B : in string; INITVAL_3A : in string;
+ INITVAL_39 : in string; INITVAL_38 : in string;
+ INITVAL_37 : in string; INITVAL_36 : in string;
+ INITVAL_35 : in string; INITVAL_34 : in string;
+ INITVAL_33 : in string; INITVAL_32 : in string;
+ INITVAL_31 : in string; INITVAL_30 : in string;
+ INITVAL_2F : in string; INITVAL_2E : in string;
+ INITVAL_2D : in string; INITVAL_2C : in string;
+ INITVAL_2B : in string; INITVAL_2A : in string;
+ INITVAL_29 : in string; INITVAL_28 : in string;
+ INITVAL_27 : in string; INITVAL_26 : in string;
+ INITVAL_25 : in string; INITVAL_24 : in string;
+ INITVAL_23 : in string; INITVAL_22 : in string;
+ INITVAL_21 : in string; INITVAL_20 : in string;
+ INITVAL_1F : in string; INITVAL_1E : in string;
+ INITVAL_1D : in string; INITVAL_1C : in string;
+ INITVAL_1B : in string; INITVAL_1A : in string;
+ INITVAL_19 : in string; INITVAL_18 : in string;
+ INITVAL_17 : in string; INITVAL_16 : in string;
+ INITVAL_15 : in string; INITVAL_14 : in string;
+ INITVAL_13 : in string; INITVAL_12 : in string;
+ INITVAL_11 : in string; INITVAL_10 : in string;
+ INITVAL_0F : in string; INITVAL_0E : in string;
+ INITVAL_0D : in string; INITVAL_0C : in string;
+ INITVAL_0B : in string; INITVAL_0A : in string;
+ INITVAL_09 : in string; INITVAL_08 : in string;
+ INITVAL_07 : in string; INITVAL_06 : in string;
+ INITVAL_05 : in string; INITVAL_04 : in string;
+ INITVAL_03 : in string; INITVAL_02 : in string;
+ INITVAL_01 : in string; INITVAL_00 : in string;
+ GSR : in string; WRITEMODE_B : in string;
+ WRITEMODE_A : in string; CSDECODE_B : in string;
+ CSDECODE_A : in string; REGMODE_B : in string;
+ REGMODE_A : in string; DATA_WIDTH_B : in integer;
+ DATA_WIDTH_A : in integer);
+ port (DIA0 : in std_logic; DIA1 : in std_logic;
+ DIA2 : in std_logic; DIA3 : in std_logic;
+ DIA4 : in std_logic; DIA5 : in std_logic;
+ DIA6 : in std_logic; DIA7 : in std_logic;
+ DIA8 : in std_logic; DIA9 : in std_logic;
+ DIA10 : in std_logic; DIA11 : in std_logic;
+ DIA12 : in std_logic; DIA13 : in std_logic;
+ DIA14 : in std_logic; DIA15 : in std_logic;
+ DIA16 : in std_logic; DIA17 : in std_logic;
+ ADA0 : in std_logic; ADA1 : in std_logic;
+ ADA2 : in std_logic; ADA3 : in std_logic;
+ ADA4 : in std_logic; ADA5 : in std_logic;
+ ADA6 : in std_logic; ADA7 : in std_logic;
+ ADA8 : in std_logic; ADA9 : in std_logic;
+ ADA10 : in std_logic; ADA11 : in std_logic;
+ ADA12 : in std_logic; ADA13 : in std_logic;
+ CEA : in std_logic; CLKA : in std_logic; OCEA : in std_logic;
+ WEA : in std_logic; CSA0 : in std_logic; CSA1 : in std_logic;
+ CSA2 : in std_logic; RSTA : in std_logic;
+ DIB0 : in std_logic; DIB1 : in std_logic;
+ DIB2 : in std_logic; DIB3 : in std_logic;
+ DIB4 : in std_logic; DIB5 : in std_logic;
+ DIB6 : in std_logic; DIB7 : in std_logic;
+ DIB8 : in std_logic; DIB9 : in std_logic;
+ DIB10 : in std_logic; DIB11 : in std_logic;
+ DIB12 : in std_logic; DIB13 : in std_logic;
+ DIB14 : in std_logic; DIB15 : in std_logic;
+ DIB16 : in std_logic; DIB17 : in std_logic;
+ ADB0 : in std_logic; ADB1 : in std_logic;
+ ADB2 : in std_logic; ADB3 : in std_logic;
+ ADB4 : in std_logic; ADB5 : in std_logic;
+ ADB6 : in std_logic; ADB7 : in std_logic;
+ ADB8 : in std_logic; ADB9 : in std_logic;
+ ADB10 : in std_logic; ADB11 : in std_logic;
+ ADB12 : in std_logic; ADB13 : in std_logic;
+ CEB : in std_logic; CLKB : in std_logic; OCEB : in std_logic;
+ WEB : in std_logic; CSB0 : in std_logic; CSB1 : in std_logic;
+ CSB2 : in std_logic; RSTB : in std_logic;
+ DOA0 : out std_logic; DOA1 : out std_logic;
+ DOA2 : out std_logic; DOA3 : out std_logic;
+ DOA4 : out std_logic; DOA5 : out std_logic;
+ DOA6 : out std_logic; DOA7 : out std_logic;
+ DOA8 : out std_logic; DOA9 : out std_logic;
+ DOA10 : out std_logic; DOA11 : out std_logic;
+ DOA12 : out std_logic; DOA13 : out std_logic;
+ DOA14 : out std_logic; DOA15 : out std_logic;
+ DOA16 : out std_logic; DOA17 : out std_logic;
+ DOB0 : out std_logic; DOB1 : out std_logic;
+ DOB2 : out std_logic; DOB3 : out std_logic;
+ DOB4 : out std_logic; DOB5 : out std_logic;
+ DOB6 : out std_logic; DOB7 : out std_logic;
+ DOB8 : out std_logic; DOB9 : out std_logic;
+ DOB10 : out std_logic; DOB11 : out std_logic;
+ DOB12 : out std_logic; DOB13 : out std_logic;
+ DOB14 : out std_logic; DOB15 : out std_logic;
+ DOB16 : out std_logic; DOB17 : out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute MEM_LPC_FILE of ROM_FIFO_0_0_0 : label is "ROM_FIFO.lpc";
+ attribute MEM_INIT_FILE of ROM_FIFO_0_0_0 : label is "rom0_mem_file.mem";
+ attribute RESETMODE of ROM_FIFO_0_0_0 : label is "SYNC";
begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
+ -- component instantiation statements
+ scuba_vhi_inst : VHI
+ port map (Z => scuba_vhi);
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
+ scuba_vlo_inst : VLO
+ port map (Z => scuba_vlo);
- ROM_FIFO_0_0_0: DP16KC
- generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_03=> "0x10010040100601004010080100401006010040100A01004010060100401008010040100601004010",
- INITVAL_02=> "0x0C010040100601004010080100401006010040100A01004010060100401008010040100601004010",
- INITVAL_01=> "0x0E010040100601004010080100401006010040100A01004010060100401008010040100601004010",
- INITVAL_00=> "0x0C010040100601004010080100401006010040100A01004010060100401008010040100601004010",
- CSDECODE_B=> "0b111", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG",
- REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, DATA_WIDTH_A=> 4)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>Address(0),
- ADA3=>Address(1), ADA4=>Address(2), ADA5=>Address(3),
- ADA6=>Address(4), ADA7=>Address(5), ADA8=>Address(6),
- ADA9=>Address(7), ADA10=>scuba_vlo, ADA11=>scuba_vlo,
- ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>OutClockEn,
- CLKA=>OutClock, OCEA=>OutClockEn, WEA=>scuba_vlo,
- CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>scuba_vlo,
- ADB5=>scuba_vlo, ADB6=>scuba_vlo, ADB7=>scuba_vlo,
- ADB8=>scuba_vlo, ADB9=>scuba_vlo, ADB10=>scuba_vlo,
- ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo,
- CEB=>scuba_vhi, CLKB=>scuba_vlo, OCEB=>scuba_vhi,
- WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>scuba_vlo, DOA0=>Q(0), DOA1=>Q(1),
- DOA2=>Q(2), DOA3=>Q(3), DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>open, DOB1=>open, DOB2=>open,
- DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
- DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
+ ROM_FIFO_0_0_0 : DP16KC
+ generic map (INITVAL_3F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_39 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_38 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_37 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_36 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_35 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_34 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_33 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_32 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_31 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_30 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_29 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_28 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_27 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_26 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_25 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_24 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_23 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_22 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_21 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_20 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_19 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_18 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_17 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_16 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_15 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_14 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_13 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_12 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_11 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_10 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_09 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_08 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_07 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_06 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_05 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_04 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_03 => "0x10010040100601004010080100401006010040100A01004010060100401008010040100601004010",
+ INITVAL_02 => "0x0C010040100601004010080100401006010040100A01004010060100401008010040100601004010",
+ INITVAL_01 => "0x0E010040100601004010080100401006010040100A01004010060100401008010040100601004010",
+ INITVAL_00 => "0x0C010040100601004010080100401006010040100A01004010060100401008010040100601004010",
+ CSDECODE_B => "0b111", CSDECODE_A => "0b000", WRITEMODE_B => "NORMAL",
+ WRITEMODE_A => "NORMAL", GSR => "DISABLED", REGMODE_B => "NOREG",
+ REGMODE_A => "NOREG", DATA_WIDTH_B => 4, DATA_WIDTH_A => 4)
+ port map (DIA0 => scuba_vlo, DIA1 => scuba_vlo, DIA2 => scuba_vlo,
+ DIA3 => scuba_vlo, DIA4 => scuba_vlo, DIA5 => scuba_vlo,
+ DIA6 => scuba_vlo, DIA7 => scuba_vlo, DIA8 => scuba_vlo,
+ DIA9 => scuba_vlo, DIA10 => scuba_vlo, DIA11 => scuba_vlo,
+ DIA12 => scuba_vlo, DIA13 => scuba_vlo, DIA14 => scuba_vlo,
+ DIA15 => scuba_vlo, DIA16 => scuba_vlo, DIA17 => scuba_vlo,
+ ADA0 => scuba_vlo, ADA1 => scuba_vlo, ADA2 => Address(0),
+ ADA3 => Address(1), ADA4 => Address(2), ADA5 => Address(3),
+ ADA6 => Address(4), ADA7 => Address(5), ADA8 => Address(6),
+ ADA9 => Address(7), ADA10 => scuba_vlo, ADA11 => scuba_vlo,
+ ADA12 => scuba_vlo, ADA13 => scuba_vlo, CEA => OutClockEn,
+ CLKA => OutClock, OCEA => OutClockEn, WEA => scuba_vlo,
+ CSA0 => scuba_vlo, CSA1 => scuba_vlo, CSA2 => scuba_vlo,
+ RSTA => Reset, DIB0 => scuba_vlo, DIB1 => scuba_vlo,
+ DIB2 => scuba_vlo, DIB3 => scuba_vlo, DIB4 => scuba_vlo,
+ DIB5 => scuba_vlo, DIB6 => scuba_vlo, DIB7 => scuba_vlo,
+ DIB8 => scuba_vlo, DIB9 => scuba_vlo, DIB10 => scuba_vlo,
+ DIB11 => scuba_vlo, DIB12 => scuba_vlo, DIB13 => scuba_vlo,
+ DIB14 => scuba_vlo, DIB15 => scuba_vlo, DIB16 => scuba_vlo,
+ DIB17 => scuba_vlo, ADB0 => scuba_vlo, ADB1 => scuba_vlo,
+ ADB2 => scuba_vlo, ADB3 => scuba_vlo, ADB4 => scuba_vlo,
+ ADB5 => scuba_vlo, ADB6 => scuba_vlo, ADB7 => scuba_vlo,
+ ADB8 => scuba_vlo, ADB9 => scuba_vlo, ADB10 => scuba_vlo,
+ ADB11 => scuba_vlo, ADB12 => scuba_vlo, ADB13 => scuba_vlo,
+ CEB => scuba_vhi, CLKB => scuba_vlo, OCEB => scuba_vhi,
+ WEB => scuba_vlo, CSB0 => scuba_vlo, CSB1 => scuba_vlo,
+ CSB2 => scuba_vlo, RSTB => scuba_vlo, DOA0 => Q(0), DOA1 => Q(1),
+ DOA2 => Q(2), DOA3 => Q(3), DOA4 => open, DOA5 => open, DOA6 => open,
+ DOA7 => open, DOA8 => open, DOA9 => open, DOA10 => open, DOA11 => open,
+ DOA12 => open, DOA13 => open, DOA14 => open, DOA15 => open,
+ DOA16 => open, DOA17 => open, DOB0 => open, DOB1 => open, DOB2 => open,
+ DOB3 => open, DOB4 => open, DOB5 => open, DOB6 => open, DOB7 => open,
+ DOB8 => open, DOB9 => open, DOB10 => open, DOB11 => open,
+ DOB12 => open, DOB13 => open, DOB14 => open, DOB15 => open,
+ DOB16 => open, DOB17 => open);
end Structure;
-- synopsys translate_off
library ecp3;
configuration Structure_CON of ROM_FIFO is
- for Structure
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
+ for Structure
+ for all : VHI use entity ecp3.VHI(V); end for;
+ for all : VLO use entity ecp3.VLO(V); end for;
+ for all : DP16KC use entity ecp3.DP16KC(V); end for;
+ end for;
end Structure_CON;
-- synopsys translate_on
-- synopsys translate_on
entity ROM_Encoder is
- port (
- Address: in std_logic_vector(9 downto 0);
- OutClock: in std_logic;
- OutClockEn: in std_logic;
- Reset: in std_logic;
- Q: out std_logic_vector(7 downto 0));
+ port (
+ Address : in std_logic_vector(9 downto 0);
+ OutClock : in std_logic;
+ OutClockEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(7 downto 0));
end ROM_Encoder;
architecture Structure of ROM_Encoder is
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
+ -- internal signal declarations
+ signal scuba_vhi : std_logic;
+ signal scuba_vlo : std_logic;
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component DP16KC
- generic (INITVAL_3F : in String; INITVAL_3E : in String;
- INITVAL_3D : in String; INITVAL_3C : in String;
- INITVAL_3B : in String; INITVAL_3A : in String;
- INITVAL_39 : in String; INITVAL_38 : in String;
- INITVAL_37 : in String; INITVAL_36 : in String;
- INITVAL_35 : in String; INITVAL_34 : in String;
- INITVAL_33 : in String; INITVAL_32 : in String;
- INITVAL_31 : in String; INITVAL_30 : in String;
- INITVAL_2F : in String; INITVAL_2E : in String;
- INITVAL_2D : in String; INITVAL_2C : in String;
- INITVAL_2B : in String; INITVAL_2A : in String;
- INITVAL_29 : in String; INITVAL_28 : in String;
- INITVAL_27 : in String; INITVAL_26 : in String;
- INITVAL_25 : in String; INITVAL_24 : in String;
- INITVAL_23 : in String; INITVAL_22 : in String;
- INITVAL_21 : in String; INITVAL_20 : in String;
- INITVAL_1F : in String; INITVAL_1E : in String;
- INITVAL_1D : in String; INITVAL_1C : in String;
- INITVAL_1B : in String; INITVAL_1A : in String;
- INITVAL_19 : in String; INITVAL_18 : in String;
- INITVAL_17 : in String; INITVAL_16 : in String;
- INITVAL_15 : in String; INITVAL_14 : in String;
- INITVAL_13 : in String; INITVAL_12 : in String;
- INITVAL_11 : in String; INITVAL_10 : in String;
- INITVAL_0F : in String; INITVAL_0E : in String;
- INITVAL_0D : in String; INITVAL_0C : in String;
- INITVAL_0B : in String; INITVAL_0A : in String;
- INITVAL_09 : in String; INITVAL_08 : in String;
- INITVAL_07 : in String; INITVAL_06 : in String;
- INITVAL_05 : in String; INITVAL_04 : in String;
- INITVAL_03 : in String; INITVAL_02 : in String;
- INITVAL_01 : in String; INITVAL_00 : in String;
- GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute MEM_LPC_FILE of ROM_Encoder_0_0_0 : label is "ROM_Encoder.lpc";
- attribute MEM_INIT_FILE of ROM_Encoder_0_0_0 : label is "rom_encoder.mem";
- attribute RESETMODE of ROM_Encoder_0_0_0 : label is "SYNC";
+ -- local component declarations
+ component VHI
+ port (Z : out std_logic);
+ end component;
+ component VLO
+ port (Z : out std_logic);
+ end component;
+ component DP16KC
+ generic (INITVAL_3F : in string; INITVAL_3E : in string;
+ INITVAL_3D : in string; INITVAL_3C : in string;
+ INITVAL_3B : in string; INITVAL_3A : in string;
+ INITVAL_39 : in string; INITVAL_38 : in string;
+ INITVAL_37 : in string; INITVAL_36 : in string;
+ INITVAL_35 : in string; INITVAL_34 : in string;
+ INITVAL_33 : in string; INITVAL_32 : in string;
+ INITVAL_31 : in string; INITVAL_30 : in string;
+ INITVAL_2F : in string; INITVAL_2E : in string;
+ INITVAL_2D : in string; INITVAL_2C : in string;
+ INITVAL_2B : in string; INITVAL_2A : in string;
+ INITVAL_29 : in string; INITVAL_28 : in string;
+ INITVAL_27 : in string; INITVAL_26 : in string;
+ INITVAL_25 : in string; INITVAL_24 : in string;
+ INITVAL_23 : in string; INITVAL_22 : in string;
+ INITVAL_21 : in string; INITVAL_20 : in string;
+ INITVAL_1F : in string; INITVAL_1E : in string;
+ INITVAL_1D : in string; INITVAL_1C : in string;
+ INITVAL_1B : in string; INITVAL_1A : in string;
+ INITVAL_19 : in string; INITVAL_18 : in string;
+ INITVAL_17 : in string; INITVAL_16 : in string;
+ INITVAL_15 : in string; INITVAL_14 : in string;
+ INITVAL_13 : in string; INITVAL_12 : in string;
+ INITVAL_11 : in string; INITVAL_10 : in string;
+ INITVAL_0F : in string; INITVAL_0E : in string;
+ INITVAL_0D : in string; INITVAL_0C : in string;
+ INITVAL_0B : in string; INITVAL_0A : in string;
+ INITVAL_09 : in string; INITVAL_08 : in string;
+ INITVAL_07 : in string; INITVAL_06 : in string;
+ INITVAL_05 : in string; INITVAL_04 : in string;
+ INITVAL_03 : in string; INITVAL_02 : in string;
+ INITVAL_01 : in string; INITVAL_00 : in string;
+ GSR : in string; WRITEMODE_B : in string;
+ WRITEMODE_A : in string; CSDECODE_B : in string;
+ CSDECODE_A : in string; REGMODE_B : in string;
+ REGMODE_A : in string; DATA_WIDTH_B : in integer;
+ DATA_WIDTH_A : in integer);
+ port (DIA0 : in std_logic; DIA1 : in std_logic;
+ DIA2 : in std_logic; DIA3 : in std_logic;
+ DIA4 : in std_logic; DIA5 : in std_logic;
+ DIA6 : in std_logic; DIA7 : in std_logic;
+ DIA8 : in std_logic; DIA9 : in std_logic;
+ DIA10 : in std_logic; DIA11 : in std_logic;
+ DIA12 : in std_logic; DIA13 : in std_logic;
+ DIA14 : in std_logic; DIA15 : in std_logic;
+ DIA16 : in std_logic; DIA17 : in std_logic;
+ ADA0 : in std_logic; ADA1 : in std_logic;
+ ADA2 : in std_logic; ADA3 : in std_logic;
+ ADA4 : in std_logic; ADA5 : in std_logic;
+ ADA6 : in std_logic; ADA7 : in std_logic;
+ ADA8 : in std_logic; ADA9 : in std_logic;
+ ADA10 : in std_logic; ADA11 : in std_logic;
+ ADA12 : in std_logic; ADA13 : in std_logic;
+ CEA : in std_logic; CLKA : in std_logic; OCEA : in std_logic;
+ WEA : in std_logic; CSA0 : in std_logic; CSA1 : in std_logic;
+ CSA2 : in std_logic; RSTA : in std_logic;
+ DIB0 : in std_logic; DIB1 : in std_logic;
+ DIB2 : in std_logic; DIB3 : in std_logic;
+ DIB4 : in std_logic; DIB5 : in std_logic;
+ DIB6 : in std_logic; DIB7 : in std_logic;
+ DIB8 : in std_logic; DIB9 : in std_logic;
+ DIB10 : in std_logic; DIB11 : in std_logic;
+ DIB12 : in std_logic; DIB13 : in std_logic;
+ DIB14 : in std_logic; DIB15 : in std_logic;
+ DIB16 : in std_logic; DIB17 : in std_logic;
+ ADB0 : in std_logic; ADB1 : in std_logic;
+ ADB2 : in std_logic; ADB3 : in std_logic;
+ ADB4 : in std_logic; ADB5 : in std_logic;
+ ADB6 : in std_logic; ADB7 : in std_logic;
+ ADB8 : in std_logic; ADB9 : in std_logic;
+ ADB10 : in std_logic; ADB11 : in std_logic;
+ ADB12 : in std_logic; ADB13 : in std_logic;
+ CEB : in std_logic; CLKB : in std_logic; OCEB : in std_logic;
+ WEB : in std_logic; CSB0 : in std_logic; CSB1 : in std_logic;
+ CSB2 : in std_logic; RSTB : in std_logic;
+ DOA0 : out std_logic; DOA1 : out std_logic;
+ DOA2 : out std_logic; DOA3 : out std_logic;
+ DOA4 : out std_logic; DOA5 : out std_logic;
+ DOA6 : out std_logic; DOA7 : out std_logic;
+ DOA8 : out std_logic; DOA9 : out std_logic;
+ DOA10 : out std_logic; DOA11 : out std_logic;
+ DOA12 : out std_logic; DOA13 : out std_logic;
+ DOA14 : out std_logic; DOA15 : out std_logic;
+ DOA16 : out std_logic; DOA17 : out std_logic;
+ DOB0 : out std_logic; DOB1 : out std_logic;
+ DOB2 : out std_logic; DOB3 : out std_logic;
+ DOB4 : out std_logic; DOB5 : out std_logic;
+ DOB6 : out std_logic; DOB7 : out std_logic;
+ DOB8 : out std_logic; DOB9 : out std_logic;
+ DOB10 : out std_logic; DOB11 : out std_logic;
+ DOB12 : out std_logic; DOB13 : out std_logic;
+ DOB14 : out std_logic; DOB15 : out std_logic;
+ DOB16 : out std_logic; DOB17 : out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute MEM_LPC_FILE of ROM_Encoder_0_0_0 : label is "ROM_Encoder.lpc";
+ attribute MEM_INIT_FILE of ROM_Encoder_0_0_0 : label is "rom_encoder.mem";
+ attribute RESETMODE of ROM_Encoder_0_0_0 : label is "SYNC";
begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
+ -- component instantiation statements
+ scuba_vhi_inst : VHI
+ port map (Z => scuba_vhi);
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
+ scuba_vlo_inst : VLO
+ port map (Z => scuba_vlo);
- ROM_Encoder_0_0_0: DP16KC
- generic map (INITVAL_3F=> "0x00000000800008000081000000000000000000820000000081000820008200000000000008200083",
- INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000084",
- INITVAL_3D=> "0x00000000000000000000000000000000000000000000000083000830008300000000000008400084",
- INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000840008400000000000008500085",
- INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085",
- INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000008500000000000008600086",
- INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085",
- INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000008600000000000008600086",
- INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000086",
- INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000008700000000000008700087",
- INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_17=> "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_13=> "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_12=> "0x00084000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_10=> "0x00083000000000000000000000000000000000000008200000000000000000081000800000000000",
- INITVAL_0F=> "0x00087000000000000000000870000000000000000000000000000000000000000000000000000000",
- INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0B=> "0x00086000000000000000000860000000000000000000000000000000000000000000000000000000",
- INITVAL_0A=> "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_07=> "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_06=> "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_05=> "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_04=> "0x00084000000000000000000840000000000000000000000000000000000000083000830000000000",
- INITVAL_03=> "0x00085000000000000000000840000000000000000000000000000000000000000000000000000000",
- INITVAL_02=> "0x00084000000000000000000840008400000000000000000000000000000000000000000000000000",
- INITVAL_01=> "0x00084000000000000000000830000000000000000000000000000000000000082000820000000000",
- INITVAL_00=> "0x00083000000000000000000820008200081000000008200082000810000000081000800008000000",
- CSDECODE_B=> "0b111", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG",
- REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>scuba_vlo, ADA4=>Address(0), ADA5=>Address(1),
- ADA6=>Address(2), ADA7=>Address(3), ADA8=>Address(4),
- ADA9=>Address(5), ADA10=>Address(6), ADA11=>Address(7),
- ADA12=>Address(8), ADA13=>Address(9), CEA=>OutClockEn,
- CLKA=>OutClock, OCEA=>OutClockEn, WEA=>scuba_vlo,
- CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>scuba_vlo,
- ADB5=>scuba_vlo, ADB6=>scuba_vlo, ADB7=>scuba_vlo,
- ADB8=>scuba_vlo, ADB9=>scuba_vlo, ADB10=>scuba_vlo,
- ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo,
- CEB=>scuba_vhi, CLKB=>scuba_vlo, OCEB=>scuba_vhi,
- WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>scuba_vlo, DOA0=>Q(0), DOA1=>Q(1),
- DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6),
- DOA7=>Q(7), DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>open, DOB1=>open, DOB2=>open,
- DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
- DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
+ ROM_Encoder_0_0_0 : DP16KC
+ generic map (INITVAL_3F => "0x00000000800008000081000000000000000000820000000081000820008200000000000008200083",
+ INITVAL_3E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000084",
+ INITVAL_3D => "0x00000000000000000000000000000000000000000000000083000830008300000000000008400084",
+ INITVAL_3C => "0x00000000000000000000000000000000000000000000000000000840008400000000000008500085",
+ INITVAL_3B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_39 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085",
+ INITVAL_38 => "0x00000000000000000000000000000000000000000000000000000000008500000000000008600086",
+ INITVAL_37 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_36 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_35 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085",
+ INITVAL_34 => "0x00000000000000000000000000000000000000000000000000000000008600000000000008600086",
+ INITVAL_33 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_32 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_31 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000086",
+ INITVAL_30 => "0x00000000000000000000000000000000000000000000000000000000008700000000000008700087",
+ INITVAL_2F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_29 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_28 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_27 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_26 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_25 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_24 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_23 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_22 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_21 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_20 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_19 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_18 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_17 => "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_16 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_15 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_14 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_13 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_12 => "0x00084000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_11 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_10 => "0x00083000000000000000000000000000000000000008200000000000000000081000800000000000",
+ INITVAL_0F => "0x00087000000000000000000870000000000000000000000000000000000000000000000000000000",
+ INITVAL_0E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0B => "0x00086000000000000000000860000000000000000000000000000000000000000000000000000000",
+ INITVAL_0A => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_09 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_08 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_07 => "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_06 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_05 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_04 => "0x00084000000000000000000840000000000000000000000000000000000000083000830000000000",
+ INITVAL_03 => "0x00085000000000000000000840000000000000000000000000000000000000000000000000000000",
+ INITVAL_02 => "0x00084000000000000000000840008400000000000000000000000000000000000000000000000000",
+ INITVAL_01 => "0x00084000000000000000000830000000000000000000000000000000000000082000820000000000",
+ INITVAL_00 => "0x00083000000000000000000820008200081000000008200082000810000000081000800008000000",
+ CSDECODE_B => "0b111", CSDECODE_A => "0b000", WRITEMODE_B => "NORMAL",
+ WRITEMODE_A => "NORMAL", GSR => "DISABLED", REGMODE_B => "NOREG",
+ REGMODE_A => "OUTREG", DATA_WIDTH_B => 18, DATA_WIDTH_A => 18)
+ port map (DIA0 => scuba_vlo, DIA1 => scuba_vlo, DIA2 => scuba_vlo,
+ DIA3 => scuba_vlo, DIA4 => scuba_vlo, DIA5 => scuba_vlo,
+ DIA6 => scuba_vlo, DIA7 => scuba_vlo, DIA8 => scuba_vlo,
+ DIA9 => scuba_vlo, DIA10 => scuba_vlo, DIA11 => scuba_vlo,
+ DIA12 => scuba_vlo, DIA13 => scuba_vlo, DIA14 => scuba_vlo,
+ DIA15 => scuba_vlo, DIA16 => scuba_vlo, DIA17 => scuba_vlo,
+ ADA0 => scuba_vlo, ADA1 => scuba_vlo, ADA2 => scuba_vlo,
+ ADA3 => scuba_vlo, ADA4 => Address(0), ADA5 => Address(1),
+ ADA6 => Address(2), ADA7 => Address(3), ADA8 => Address(4),
+ ADA9 => Address(5), ADA10 => Address(6), ADA11 => Address(7),
+ ADA12 => Address(8), ADA13 => Address(9), CEA => OutClockEn,
+ CLKA => OutClock, OCEA => OutClockEn, WEA => scuba_vlo,
+ CSA0 => scuba_vlo, CSA1 => scuba_vlo, CSA2 => scuba_vlo,
+ RSTA => Reset, DIB0 => scuba_vlo, DIB1 => scuba_vlo,
+ DIB2 => scuba_vlo, DIB3 => scuba_vlo, DIB4 => scuba_vlo,
+ DIB5 => scuba_vlo, DIB6 => scuba_vlo, DIB7 => scuba_vlo,
+ DIB8 => scuba_vlo, DIB9 => scuba_vlo, DIB10 => scuba_vlo,
+ DIB11 => scuba_vlo, DIB12 => scuba_vlo, DIB13 => scuba_vlo,
+ DIB14 => scuba_vlo, DIB15 => scuba_vlo, DIB16 => scuba_vlo,
+ DIB17 => scuba_vlo, ADB0 => scuba_vlo, ADB1 => scuba_vlo,
+ ADB2 => scuba_vlo, ADB3 => scuba_vlo, ADB4 => scuba_vlo,
+ ADB5 => scuba_vlo, ADB6 => scuba_vlo, ADB7 => scuba_vlo,
+ ADB8 => scuba_vlo, ADB9 => scuba_vlo, ADB10 => scuba_vlo,
+ ADB11 => scuba_vlo, ADB12 => scuba_vlo, ADB13 => scuba_vlo,
+ CEB => scuba_vhi, CLKB => scuba_vlo, OCEB => scuba_vhi,
+ WEB => scuba_vlo, CSB0 => scuba_vlo, CSB1 => scuba_vlo,
+ CSB2 => scuba_vlo, RSTB => scuba_vlo, DOA0 => Q(0), DOA1 => Q(1),
+ DOA2 => Q(2), DOA3 => Q(3), DOA4 => Q(4), DOA5 => Q(5), DOA6 => Q(6),
+ DOA7 => Q(7), DOA8 => open, DOA9 => open, DOA10 => open, DOA11 => open,
+ DOA12 => open, DOA13 => open, DOA14 => open, DOA15 => open,
+ DOA16 => open, DOA17 => open, DOB0 => open, DOB1 => open, DOB2 => open,
+ DOB3 => open, DOB4 => open, DOB5 => open, DOB6 => open, DOB7 => open,
+ DOB8 => open, DOB9 => open, DOB10 => open, DOB11 => open,
+ DOB12 => open, DOB13 => open, DOB14 => open, DOB15 => open,
+ DOB16 => open, DOB17 => open);
end Structure;
-- synopsys translate_off
library ecp3;
configuration Structure_CON of ROM_Encoder is
- for Structure
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
+ for Structure
+ for all : VHI use entity ecp3.VHI(V); end for;
+ for all : VLO use entity ecp3.VLO(V); end for;
+ for all : DP16KC use entity ecp3.DP16KC(V); end for;
+ end for;
end Structure_CON;
-- synopsys translate_on
signal result_2_reg : std_logic;
signal coarse_cntr_i : std_logic_vector(10 downto 0);
signal hit_time_stamp_i : std_logic_vector(10 downto 0);
- signal hit_time_stamp_reg : std_logic_vector(10 downto 0);
- signal hit_time_stamp_reg2 : std_logic_vector(10 downto 0);
- signal hit_time_stamp_reg3 : std_logic_vector(10 downto 0);
signal fine_counter_i : std_logic_vector(9 downto 0);
signal fine_counter_reg : std_logic_vector(9 downto 0);
signal encoder_start_i : std_logic;
fifo_rd_en_i <= READ_EN_IN;
coarse_cntr_i <= COARSE_COUNTER_IN;
- hit_in_i <= HIT_IN;
+-- hit_in_i <= HIT_IN;
hit_buf <= not HIT_IN;
--purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition
RESET => RESET_WR,
DataA => data_a_i,
DataB => data_b_i,
- ClkEn => '1', --ff_array_en_i,
+ ClkEn => '1', --ff_array_en_i,
Result => result_i);
data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF";
data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(hit_buf) & x"000000" & "00" & hit_buf;
hit_time_stamp_i <= (others => '0');
elsif hit_detect_reg = '1' then
encoder_start_i <= '1';
- hit_time_stamp_i <= coarse_cntr_i-2;
+ hit_time_stamp_i <= coarse_cntr_i;
else
encoder_start_i <= '0';
end if;
REF_DEBUG_OUT(12) <= encoder_start_i;
REF_DEBUG_OUT(13) <= encoder_finished_i;
REF_DEBUG_OUT(14) <= fifo_wr_en_i;
-
- REF_DEBUG_OUT(15) <= CLK_WR;
+
+ REF_DEBUG_OUT(15) <= CLK_WR;
REF_DEBUG_OUT(31 downto 16) <= (others => '0');
end Reference_Channel;
signal ref_debug_i : std_logic_vector(31 downto 0);
type channel_debug_array is array (1 to CHANNEL_NUMBER-1) of std_logic_vector(31 downto 0);
signal channel_debug_i : channel_debug_array;
+
+ --attribute syn_preserve : boolean;
+ --attribute syn_preserve of reset_tdc : signal is true;
+ --attribute syn_keep : boolean;
+ --attribute syn_keep of reset_tdc : signal is true;
+ --attribute syn_maxfan : integer;
+ --attribute syn_maxfan of reset_tdc : signal is 100;
-------------------------------------------------------------------------------
begin
generic map (
CHANNEL_ID => i)
port map (
- RESET_WR => reset_tdc,
- RESET_RD => RESET,
- CLK_WR => CLK_TDC,
- CLK_RD => CLK_READOUT,
+ RESET_200 => reset_tdc,
+ RESET_100 => RESET,
+ CLK_200 => CLK_TDC,
+ CLK_100 => CLK_READOUT,
HIT_IN => hit_in_i(i),
READ_EN_IN => rd_en_i(i),
FIFO_DATA_OUT => channel_data_i(i),
when 10 => data_out_reg <= "010" & "01010" & wait_time;
stop_status_i <= '1';
when 11 => data_out_reg <= "010" & "01011" & total_empty_channel;
- i := -1;
+ i := -1;
when others => null;
end case;
data_wr_reg <= '1';
data_wr_reg <= '1';
stop_status_i <= '0';
else
- data_out_reg <= (others => '1');
+ data_out_reg <= (others => '1');
data_wr_reg <= '0';
stop_status_i <= '0';
end if;
RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register
CLK0 : in std_logic; --clock for first FF
CLK1 : in std_logic; --Clock for other FF
- D_IN : in std_logic; --Data input
- D_OUT : out std_logic --Data output
+ D_IN : in std_logic; --Data input
+ D_OUT : out std_logic --Data output
);
end entity;
BROADCAST_BITMASK => x"FF",
BROADCAST_SPECIAL_ADDR => x"45",
REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"91000080", -- regio_hardware_version_i,
+ REGIO_HARDWARE_VERSION => x"91000000", -- regio_hardware_version_i,
REGIO_INIT_ADDRESS => x"f305",
REGIO_USE_VAR_ENDPOINT_ID => c_YES,
CLOCK_FREQUENCY => 125,
TIMING_TRIGGER_RAW => c_YES,
--Configure data handler
DATA_INTERFACE_NUMBER => 1,
- DATA_BUFFER_DEPTH => 13, --13
+ DATA_BUFFER_DEPTH => 13, --13
DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024
+ DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024
TRG_RELEASE_AFTER_DATA => c_YES,
HEADER_BUFFER_DEPTH => 9,
HEADER_BUFFER_FULL_THRESH => 2**9-16
THE_TDC : TDC
generic map (
- CHANNEL_NUMBER => 5, -- Number of TDC channels
+ CHANNEL_NUMBER => 8, -- Number of TDC channels
STATUS_REG_NR => REGIO_NUM_STAT_REGS,
CONTROL_REG_NR => REGIO_NUM_CTRL_REGS)
port map (
CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement
CLK_READOUT => clk_100_i, -- Clock for the readout
REFERENCE_TIME => timing_trg_received_i, -- Reference time input
- HIT_IN => hit_in_i(4 downto 1), -- Channel start signals
+ HIT_IN => hit_in_i(7 downto 1), -- Channel start signals
TRG_WIN_PRE => ctrl_reg(42 downto 32), -- Pre-Trigger window width
TRG_WIN_POST => ctrl_reg(58 downto 48), -- Post-Trigger window width
--
--end generate Gen_Hit_In_Signals;
--regio_hardware_version_i <= x"9100" & addOn_type_i & edge_type_i & tdc_channel_no_i & x"0";
-
+
--addOn_type_i <= x"0"; -- x"0" - ADA AddOn version 1
-- -- x"1" - ADA AddOn version 2
-- -- x"2" - multi purpose test AddOn
library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
entity up_counter is
generic (
- NUMBER_OF_BITS : positive);
+ NUMBER_OF_BITS : positive);
port (
- CLK : in std_logic;
- RESET : in std_logic;
- COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
- UP_IN : in std_logic);
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic);
end up_counter;
architecture up_counter of up_counter is
-signal counter: std_logic_vector (NUMBER_OF_BITS-1 downto 0);
+ signal counter : std_logic_vector (NUMBER_OF_BITS-1 downto 0);
begin
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