removed bug in bram fifo, Jan

diff --git a/xilinx/trb_net16_bram_fifo.vhd b/xilinx/trb_net16_bram_fifo.vhd
index 638072140b67de627c706a70c271e41fbbb6f64d..072c41e7b01ad7ab817167807a14e71f9375efe9 100644 (file)
--- a/xilinx/trb_net16_bram_fifo.vhd
+++ b/xilinx/trb_net16_bram_fifo.vhd
@@ -137,24 +137,6 @@ bram1: RAMB16_S18_S18 port map (ADDRA => read_addr, ADDRB => write_addr,
 --                                                           --
 ---------------------------------------------------------------
  
--- proc1: process (clock, fifo_gsr)
--- begin
---    if (fifo_gsr = '1') then
---       read_allow <= '0';
---    elsif (clock'EVENT AND clock = '1') then
---       read_allow <= read_enable AND NOT emptyg;
---    end if;
--- end process proc1;
--- 
--- proc2: process (clock, fifo_gsr)
--- begin
---    if (fifo_gsr = '1') then
---       write_allow <= '0';
---    elsif (clock'EVENT AND clock = '1') then
---       write_allow <= write_enable AND NOT fullg;
---    end if;
--- end process proc2;
-
 write_allow <= write_enable AND NOT fullg;
 read_allow <= (read_enable or read_after_write) AND NOT empty;-- ;
 fcnt_allow <= write_allow XOR read_allow; -- and not read_after_write