-- time stamp
signal coarse_cntr_reg : std_logic_vector(10 downto 0);
+ signal trig_win_end_i : std_logic;
-- debug
signal sync_q : std_logic_vector(2 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of coarse_cntr_reg : signal is true;
attribute syn_preserve of hit_buf : signal is true;
+ attribute syn_preserve of trig_win_end_i : signal is true;
attribute nomerge : string;
attribute nomerge of hit_buf : signal is "true";
CLK_100 => CLK_100,
RESET_100 => RESET_100,
HIT_IN => hit_buf,
- TRIGGER_WIN_END_IN => TRIGGER_WIN_END_IN,
+ TRIGGER_WIN_END_IN => trig_win_end_i,
EPOCH_COUNTER_IN => EPOCH_COUNTER_IN,
-- DATA_FINISHED_IN => data_finished_i,
COARSE_COUNTER_IN => coarse_cntr_reg,
ENCODER_START_OUT => encoder_start_i,
ENCODER_FINISHED_OUT => encoder_finished_i);
+ trig_win_end_i <= TRIGGER_WIN_END_IN when rising_edge(CLK_200);
-- data_finished_i <= DATA_FINISHED_IN when rising_edge(CLK_100);
pulse_sync_encoder_start : pulse_sync
-- File : Readout.vhd
-- Author : cugur@gsi.de
-- Created : 2012-10-25
--- Last update: 2013-03-07
+-- Last update: 2013-03-20
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
begin
if rising_edge(CLK_200) then
if RESET_200 = '1' then
- trg_win_cnt <= '1' & trg_win_post_200;
+ trg_win_cnt <= '1' & trg_win_post_200;
elsif start_trg_win_cnt_200_p = '1' then
trg_win_end_200 <= '0';
trg_win_cnt <= "000000000001";
readout_fsm <= '1';
elsif VALID_NOTIMING_TRG_IN = '1' then
if TRG_TYPE_IN = x"E" then
- RD_NEXT <= SEND_STATUS;
+ wr_header_fsm <= '1';
+ RD_NEXT <= SEND_STATUS;
else
- RD_NEXT <= SEND_TRG_RELEASE_A;
+ data_finished_fsm <= '1';
+ RD_NEXT <= SEND_TRG_RELEASE_A;
end if;
- wr_header_fsm <= '1';
elsif INVALID_TRG_IN = '1' then
RD_NEXT <= SEND_TRG_RELEASE_A;
data_finished_fsm <= '1';