added info for Trigger Module and list of slow control address ranges

diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
index ba0514a0d0842e1cd3d43a08a283911d5de7fb13..9dfb13e5aeced17e2ac061ec178ae857c184231f 100644 (file)
--- a/trb3/Trb3GeneralRemarks.tex
+++ b/trb3/Trb3GeneralRemarks.tex
@@ -35,6 +35,7 @@ The first three digits of the SID is the serial number as written on the board,
 
 
 \subsection{Flash Programming}
+\label{flashprog}
 Typically only the first programming of a board is done with a JTAG cable, all later upgrades can be done directly via TrbNet to the Flash ROMs. The advantage is the increased speed (about a factor 10) and that no physical access to the board is necessary. The software needs some settings in the FPGA code to function properly:
 
 First, the name of the design has to contain a certain sub-string:

diff --git a/trb3/TriggerModule.tex b/trb3/TriggerModule.tex
index 63d53ae763a42e10ce20c47baa3cd4e6e8c3d681..eb8b9f01ce3362d19716c068e87939b335db4911 100644 (file)
--- a/trb3/TriggerModule.tex
+++ b/trb3/TriggerModule.tex
@@ -1,3 +1,4 @@
+\label{triggermodule}
 The trigger module can be used to forward any input of a peripheral FPGA via the central FPGA to 
 the CTS. E.g. any input to any TDC can be used to generate the trigger in the CTS.
 

diff --git a/trb3/main.tex b/trb3/main.tex
index a91230efbbd1901c277892f352cfacb8f48a7849..7d46341e167da9dcbb952f587f552ae162ff625e 100644 (file)
--- a/trb3/main.tex
+++ b/trb3/main.tex
@@ -139,6 +139,8 @@
 \part{General Information}
   \section{General Remarks}
     \input{Trb3GeneralRemarks}
+  \section{Slow Control Registers}
+    \input{sctrladdresses}
 \cleardoublepage
 \part{Hardware}
   \section{Measurements}
@@ -178,6 +180,7 @@
   \section{New VHDL Project}
   \input{VhdlProjectSetup}
   \section{TDC}
+    \label{TDC}
     \subsection{Building Blocks}
       \input{TdcBuildingBlocks}
     \subsection{Features}

diff --git a/trb3/sctrladdresses.tex b/trb3/sctrladdresses.tex
new file mode 100644 (file)
index 0000000..6a7a7e4
--- /dev/null
+++ b/trb3/sctrladdresses.tex
@@ -0,0 +1,27 @@
+
+\begin{table}[htbp]
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|c|C|}
+\hline
+\textbf{Address} & \textbf{Name} & \textbf{Description} \\
+\hline\hline
+
+4000 -- 40FF & Hub & Hub Config and status \\
+7000 -- 73FF & RDO & Readout status \\
+8000 -- 83FF & GbE & Ethernet registers \\
+A000 -- BFFF & FEE & Thresholds, Pedestals, Settings \\
+B000 -- B3FF & Serdes & Serializer status (on hubs) \\
+C000 -- CEFF & TDC & TDC Control and Status [\ref{TDC}] \\
+CF00 -- CF7F & Trg & Trigger signal generation [\ref{triggermodule}]\\
+CF80 -- CFFF & Inp & Input Monitoring [\ref{triggermodule}]\\
+D000 -- D13F & Flash & Control for SPI Flash of FPGA [\ref{flashprog}]\\
+D300         & TrgIn & Selection for trigger and clock input on CTS \\
+D400 -- D41F & SPI & SPI Interface for DAC and Padiwa \\
+D500 -- D5FF & SED & Soft Error Detection \\
+E000 -- FFFF & Debugging & Memories and Registers for Debugging \\
+\hline
+\end{tabularx}
+\caption{Register Map of the Slow Control Endpoint. Suggested usage of the address space.}
+\label{regioaddressmapsuggested}
+\end{center}
+\end{table}
\ No newline at end of file