};
#define DMA_BUFFER_NUM_PAGES ((8 * 1024 * 1024) / PAGE_SIZE)
-#define PEXOR_DMA_MAXPOLLS 6000000
+#define PEXOR_DMA_MAXPOLLS 10000000
#define PEXOR_DMA_POLLDELAY 0
#define PEXOR_MEMWRITE_SIZE 128
.remove = remove,
};
-
-
-
-//static DEVICE_ATTR(freebufs, S_IRUGO, pexor_sysfs_freebuffers_show, NULL);
-//static DEVICE_ATTR(usedbufs, S_IRUGO, pexor_sysfs_usedbuffers_show, NULL);
-//static DEVICE_ATTR(rcvbufs, S_IRUGO, pexor_sysfs_rcvbuffers_show, NULL);
static DEVICE_ATTR(codeversion, S_IRUGO, pexor_sysfs_codeversion_show, NULL);
-//static DEVICE_ATTR(dmaregs, S_IRUGO, pexor_sysfs_dmaregs_show, NULL);
#ifdef PEXOR_WITH_SFP
static DEVICE_ATTR(sfpregs, S_IRUGO, pexor_sysfs_sfpregs_show, NULL);
#ifdef PEXOR_WITH_SFP
device_remove_file(priv->class_dev, &dev_attr_sfpregs);
#endif
- //device_remove_file(priv->class_dev, &dev_attr_dmaregs);
device_remove_file(priv->class_dev, &dev_attr_codeversion);
- //device_remove_file(priv->class_dev, &dev_attr_rcvbufs);
- //device_remove_file(priv->class_dev, &dev_attr_usedbufs);
- //device_remove_file(priv->class_dev, &dev_attr_freebufs);
device_destroy(pexor_class, priv->devno);
priv->class_dev = 0;
}
} //for
set_pexor(&(privdata->pexor), privdata->iomem[0], privdata->bases[0]);
- //print_pexor(&(privdata->pexor));
-
sema_init(&(privdata->sem), 1);
spin_lock_init(&(privdata->dma_lock));
/* TODO may use rw semaphore instead? init_rwsem(struct
rw_semaphore *sem); */
-
////////////////// here chardev registering
privdata->devid = atomic_inc_return(&pexor_numdevs) - 1;
if (privdata->devid >= PEXOR_MAX_DEVS) {
channel);
pexor_msg(KERN_ERR "ERROR> last val: 0x%08x\n", val);
- /* to be done: flush FIFO here */
+ /* to be done: flush FIFO here, not libtrbnet takes care of this */
return -1;
}
((u32 *) priv->dma.buffer)[ctr] = val;
}
/* should not happen,out of buffers etc */
- /* to be done: flush FIFO here */
+ /* to be done: flush FIFO here, no libtrbnet takes care of this*/
return -1;
}
if (descriptor.dma != 0 && channel == 3) {
/* only channel 3 supports DMA */
- /* Credential debug */
+ /* Credential check */
u32 cred1;
u32 cred2;
cred1 = ioread32(priv->pexor.dma_debug2);
(unsigned int)dmastat);
/* reset DMA */
iowrite32(PEXOR_TRB_DMA_RESET, priv->pexor.dma_control_stat);
- /* do we need to flush the fifo-buffer? */
+ /* do we need to flush the fifo-buffer, no libtrbnet takes care */
status = -EFAULT;
goto OUT_IOCTL;
}
(unsigned int)dmastat);
/* reset DMA */
iowrite32(PEXOR_TRB_DMA_RESET, priv->pexor.dma_control_stat);
- /* do we need to flush the fifo-buffer? */
+ /* do we need to flush the fifo-buffer, no libtrbnet takes care */
status = -EFAULT;
goto OUT_IOCTL;
}
"ERROR> no more DMA buffers available, aborting DMA\n");
/* reset DMA */
iowrite32(PEXOR_TRB_DMA_RESET, priv->pexor.dma_control_stat);
- /* do we need to flush the fifo-buffer? */
+ /* do we need to flush the fifo-buffer, no libtrbnet takes care */
status = -EFAULT;
goto OUT_IOCTL;
}
/* Check dmaSize */
if ((dmaSize % 5) != 0) {
- if ((dmaSize % 5) == 1) {
- dmaSize--;
- pexor_msg(KERN_ERR "INFO> DMA padding\n");
- } else {
- pexor_msg(KERN_ERR
- "ERROR> Invalid DMA Size %d\n", dmaSize);
- status = -EFAULT;
- goto OUT_IOCTL;
- }
+ pexor_msg(KERN_ERR
+ "ERROR> Invalid DMA Size %d\n", dmaSize);
+ status = -EFAULT;
+ goto OUT_IOCTL;
}
status = dmaSize;
pexor_read_buffer_ctr = dmaSize * 4;
- /* Credential debug */
+ /* Check Credentials */
cred2 = ioread32(priv->pexor.dma_debug2);
if (cred2 != cred1) {
pexor_msg(KERN_ERR
"ERROR> Lost DMA Credentials: 0x%08x != 0x%08x Command: %d\n",
cred1, cred2, command);
+ status = -EFAULT;
+ goto OUT_IOCTL;
}
#ifdef PEXOR_TRB_DEBUG
/*
* pexor_trb.h
*
- * definitions and functions for pexor with
- * HADES trbnet protocol
+ * definitions and functions for pexor with
+ * HADES trbnet protocol
*/
#ifndef _PCI_PEXOR_TRB_H_
RAM position for fops io
functions? */
-#define PEXOR_DMA_BASE 0x00 /* base address of DMA engine */
+#define PEXOR_DMA_BASE 0x00 /* base address of DMA engine */
#define PEXOR_IRQ_CTRL PEXOR_DMA_BASE /* DUMMY TODO meaningful
register for trbnet */
#define PEXOR_TRB_SENDER_TRIGGER_INFO 0x0115
#define PEXOR_TRB_DMA_ADD 0x0700 /* DMA Start Address */
-#define PEXOR_TRB_DMA_LEN 0x0701 /* (rw) DMA Buffer length in 32 bit words */
-#define PEXOR_TRB_DMA_CTL 0x0702 /*(writing to register is sufficient, no need to clear it before writing)
- Bit 0: DMA start
- Bit 1: DMA reset - completely reset the full DMA handler
-
- (r):
- Bit 0: DMA active, goes low after TrbNet access has been completed and DMA is finished
- Bit 1: DMA Buffer full. Buffer provided by CPU is full, waiting for new buffer and DMA start
- Bit 31..8: DMA Size. Number of written data words to current dma buffer. Only valid when Bit 0 is low or Bit 1 is high */
-
-
-#define PEXOR_TRB_DMA_BST 0x0703 /* Bit 7-0: DMA Burst Length in 32 bit words. Default: 0x1F */
-#define PEXOR_TRB_DMA_STA 0x0704 /* Status Register: Various status bits of DMA engine (t.b.d.) */
-#define PEXOR_TRB_DMA_CRE 0x0705 /* Status Register: Available credits (t.b.d.) */
-#define PEXOR_TRB_DMA_CNT 0x0706 /* Status Register: Counter values (t.b.d.) */
+#define PEXOR_TRB_DMA_LEN 0x0701 /* (rw) DMA Buffer length
+ in 32 bit words */
+#define PEXOR_TRB_DMA_CTL 0x0702 /*(writing to register is
+ sufficient, no need to clear
+ it before writing)
+ Bit 0: DMA start
+ Bit 1: DMA reset - completely
+ reset the full DMA handler
+
+ (r):
+ Bit 0: DMA active, goes low
+ after TrbNet access has been
+ completed and DMA is finished
+ Bit 1: DMA Buffer full.
+ Buffer provided by CPU is
+ full, waiting for new buffer
+ and DMA start
+ Bit 31..8: DMA Size. Number
+ of written data words to
+ current dma buffer. Only
+ valid when Bit 0 is low or
+ Bit 1 is high */
+
+
+#define PEXOR_TRB_DMA_BST 0x0703 /* Bit 7-0: DMA Burst Length
+ in 32 bit words.
+ Default: 0x1F */
+#define PEXOR_TRB_DMA_STA 0x0704 /* Status Register: Various
+ status bits of DMA engine
+ (t.b.d.) */
+#define PEXOR_TRB_DMA_CRE 0x0705 /* Status Register: Available
+ credits (t.b.d.) */
+#define PEXOR_TRB_DMA_CNT 0x0706 /* Status Register: Counter
+ values (t.b.d.) */
#define PEXOR_TRB_CMD_REGISTER_READ 0x08
#define PEXOR_TRB_CMD_REGISTER_READ_MEM 0x0a
#define PEXOR_TRB_NET_READUNIQUEID 0x5e1d
#define PEXOR_TRB_NET_SETADDRESS 0x5ead
+
+/* formerly pexor_user.h */
+
+#include <linux/ioctl.h>
+
+#define PEXORVERSION "0.995"
+
+
+/* the states:*/
+#define PEXOR_STATE_STOPPED 0 /* daq stopped */
+#define PEXOR_STATE_DMA_SINGLE 1 /* trigger a single dma transfer into
+ next free buf */
+#define PEXOR_STATE_DMA_FLOW 2 /* each dma transfer will initiate the
+ next = dataflow or chained DMA */
+#define PEXOR_STATE_DMA_AUTO 3 /* TODO: board fpga will automatically
+ initate next DMA when send fifo is full */
+#define PEXOR_STATE_DMA_SUSPENDED 4 /* used for backpressure until free
+ buffer list is empty no more */
+#define PEXOR_STATE_IR_TEST 5 /* this state is used to test raising an ir
+ manually */
+
+#define PEXOR_TRIGGER_FIRED 0 /* return value from wait trigger to inform
+ that trigger ir was fired reached */
+#define PEXOR_TRIGGER_TIMEOUT 1 /* return value from wait trigger to inform
+ that wait timeout was reached */
+
+#define PEXOR_TRIX_RES 0 /* Command for ioctl set trixor to reset
+ trigger - clear dt flag */
+#define PEXOR_TRIX_GO 1 /* Command for ioctl set trixor to start
+ acquisition */
+#define PEXOR_TRIX_HALT 2 /* Command for ioctl set trixor to stop
+ acquisition */
+#define PEXOR_TRIX_TIMESET 3 /* Command for ioctl set trixor to set
+ trigger time windows */
+
+
+struct pexor_userbuf
+{
+ unsigned long addr; /* user space virtual address (=buffer id) */
+ unsigned long size; /* allocated size or used size */
+};
+
+
+struct pexor_bus_io
+{
+ unsigned long sfp; /* sfp link id 0..3 (optional) */
+ unsigned long slave; /* slave device id at the sfp (optional) */
+ unsigned long address; /* address on the "field bus" connected to
+ the optical links */
+ unsigned long value; /* value for read/write at bus address.
+ Contains result status after write */
+};
+
+struct pexor_token_io
+{
+ unsigned char sync; /* 1:synchronous mode, 0: asynchronous mode */
+ unsigned long sfp; /* sfp link id 0..3 */
+ unsigned long bufid; /* switch double buffer id on slave (1 or 0) */
+ struct pexor_userbuf tkbuf; /* dma buffer with received token data
+ (on synchronous reply) */
+};
+
+
+
+
+
#endif
* pexor_user.h
*
* Created on: 01.12.2009
- * Author: J. Adamczewski-Musch
+ * Author: J. Adamczewski-Musch
*
- * Contains all common definitions for kernel driver and user space library
+ * Contains all common definitions for the kernel driver and
+ * user space library
*/
#ifndef PEXOR_USER_H_
#define PEXOR_USER_H_
-#include <linux/ioctl.h>
-#define PEXORVERSION "0.995"
-
-/* the ioctl stuff here:*/
-#define PEXOR_IOC_MAGIC 0xE0
-
-#define PEXOR_IOC_RESET _IO( PEXOR_IOC_MAGIC, 0)
-#define PEXOR_IOC_FREEBUFFER _IOW( PEXOR_IOC_MAGIC, 1, struct pexor_userbuf)
-#define PEXOR_IOC_DELBUFFER _IOW( PEXOR_IOC_MAGIC, 2, struct pexor_userbuf)
-#define PEXOR_IOC_WAITBUFFER _IOR( PEXOR_IOC_MAGIC, 3, struct pexor_userbuf)
-#define PEXOR_IOC_USEBUFFER _IOR( PEXOR_IOC_MAGIC, 4, struct pexor_userbuf)
-#define PEXOR_IOC_SETSTATE _IOR( PEXOR_IOC_MAGIC, 5, int)
-#define PEXOR_IOC_TEST _IOR( PEXOR_IOC_MAGIC, 6, int)
-#define PEXOR_IOC_CLEAR_RCV_BUFFERS _IO( PEXOR_IOC_MAGIC, 7)
-#define PEXOR_IOC_WRITE_BUS _IOWR( PEXOR_IOC_MAGIC, 8, struct pexor_bus_io)
-#define PEXOR_IOC_READ_BUS _IOWR( PEXOR_IOC_MAGIC, 9, struct pexor_bus_io)
-#define PEXOR_IOC_INIT_BUS _IOW( PEXOR_IOC_MAGIC, 10, struct pexor_bus_io)
-#define PEXOR_IOC_WRITE_REGISTER _IOW( PEXOR_IOC_MAGIC, 11, struct pexor_reg_io)
-#define PEXOR_IOC_READ_REGISTER _IOWR( PEXOR_IOC_MAGIC, 12, struct pexor_reg_io)
-#define PEXOR_IOC_REQUEST_TOKEN _IOWR( PEXOR_IOC_MAGIC, 13, struct pexor_token_io)
-#define PEXOR_IOC_WAIT_TOKEN _IOWR( PEXOR_IOC_MAGIC, 14, struct pexor_token_io)
-#define PEXOR_IOC_WAIT_TRIGGER _IO( PEXOR_IOC_MAGIC, 15)
-#define PEXOR_IOC_SET_TRIXOR _IOR( PEXOR_IOC_MAGIC, 16, struct pexor_trixor_set)
-#define PEXOR_IOC_TRBNET_REQUEST _IOWR( PEXOR_IOC_MAGIC, 17, struct pexor_trbnet_io)
-#define PEXOR_IOC_MAXNR 18
-
-/* the states:*/
-#define PEXOR_STATE_STOPPED 0 /* daq stopped */
-#define PEXOR_STATE_DMA_SINGLE 1 /* trigger a single dma transfer into next free buf */
-#define PEXOR_STATE_DMA_FLOW 2 /* each dma transfer will initiate the next = dataflow or chained DMA */
-#define PEXOR_STATE_DMA_AUTO 3 /* TODO: board fpga will automatically initate next DMA when send fifo is full */
-#define PEXOR_STATE_DMA_SUSPENDED 4 /* used for backpressure until free buffer list is empty no more */
-#define PEXOR_STATE_IR_TEST 5 /* this state is used to test raising an ir manually */
-
-#define PEXOR_TRIGGER_FIRED 0 /* return value from wait trigger to inform that trigger ir was fired reached */
-#define PEXOR_TRIGGER_TIMEOUT 1 /* return value from wait trigger to inform that wait timeout was reached */
-
-#define PEXOR_TRIX_RES 0 /* Command for ioctl set trixor to reset trigger - clear dt flag */
-#define PEXOR_TRIX_GO 1 /* Command for ioctl set trixor to start acquisition */
-#define PEXOR_TRIX_HALT 2 /* Command for ioctl set trixor to stop acquisition */
-#define PEXOR_TRIX_TIMESET 3 /* Command for ioctl set trixor to set trigger time windows */
-
-
-
-struct pexor_userbuf
-{
- unsigned long addr; /* user space virtual address (=buffer id) */
- unsigned long size; /* allocated size or used size */
-};
-
-
-struct pexor_bus_io
-{
- unsigned long sfp; /* sfp link id 0..3 (optional) */
- unsigned long slave; /* slave device id at the sfp (optional) */
- unsigned long address; /* address on the "field bus" connected to the optical links */
- unsigned long value; /* value for read/write at bus address. Contains result status after write */
-};
-
-struct pexor_token_io
-{
- unsigned char sync; /* 1:synchronous mode, 0: asynchronous mode */
- unsigned long sfp; /* sfp link id 0..3 */
- unsigned long bufid; /* switch double buffer id on slave (1 or 0) */
- struct pexor_userbuf tkbuf; /* dma buffer with received token data (on synchronous reply) */
-};
-
-
-struct pexor_reg_io
-{
- unsigned int address; /* address of a board register, relative to the specified BAR */
- unsigned int value; /* value for read/write at register address */
- unsigned char bar; /* the BAR where the register is mapped to PCI access. */
-};
-
-
-/* ---------------------------------------------------------------------- */
+/* ---------------------------------------------------------------------- */
#define PEXOR_TRBNETCOM_REG_WRITE 0
#define PEXOR_TRBNETCOM_REG_WRITE_MEM 1
struct pexor_trbnet_io
{
- unsigned int command; /* command to issue on trbnet */
- unsigned short trb_address; /* address of board in trbnet */
- unsigned int reg_address; /* address on board */
- unsigned short dma; /* activate DMA-engine */
- unsigned int arg0; /* optional argument 0 */
- unsigned int arg1; /* optional argument 1 */
- unsigned int arg2; /* optional argument 2 */
+ unsigned int command; /* command to issue on trbnet */
+ unsigned short trb_address; /* address of board in trbnet */
+ unsigned int reg_address; /* address on board */
+ unsigned short dma; /* activate DMA-engine */
+ unsigned int arg0; /* optional argument 0 */
+ unsigned int arg1; /* optional argument 1 */
+ unsigned int arg2; /* optional argument 2 */
+ unsigned int error; /* return value in case of ioctl error */
};
+/* ---------------------------------------------------------------------- */
+
+/* the ioctl stuff here:*/
+#define PEXOR_IOC_MAGIC 0xE0
+
+#define PEXOR_IOC_RESET _IO( PEXOR_IOC_MAGIC, 0)
+#define PEXOR_IOC_FREEBUFFER _IOW( PEXOR_IOC_MAGIC, 1, \
+ struct pexor_userbuf)
+#define PEXOR_IOC_DELBUFFER _IOW( PEXOR_IOC_MAGIC, 2, \
+ struct pexor_userbuf)
+#define PEXOR_IOC_WAITBUFFER _IOR( PEXOR_IOC_MAGIC, 3, \
+ struct pexor_userbuf)
+#define PEXOR_IOC_USEBUFFER _IOR( PEXOR_IOC_MAGIC, 4, \
+ struct pexor_userbuf)
+#define PEXOR_IOC_SETSTATE _IOR( PEXOR_IOC_MAGIC, 5, int)
+#define PEXOR_IOC_TEST _IOR( PEXOR_IOC_MAGIC, 6, int)
+#define PEXOR_IOC_CLEAR_RCV_BUFFERS _IO( PEXOR_IOC_MAGIC, 7)
+#define PEXOR_IOC_WRITE_BUS _IOWR( PEXOR_IOC_MAGIC, 8, \
+ struct pexor_bus_io)
+#define PEXOR_IOC_READ_BUS _IOWR( PEXOR_IOC_MAGIC, 9, \
+ struct pexor_bus_io)
+#define PEXOR_IOC_INIT_BUS _IOW( PEXOR_IOC_MAGIC, 10, \
+ struct pexor_bus_io)
+#define PEXOR_IOC_WRITE_REGISTER _IOW( PEXOR_IOC_MAGIC, 11, \
+ struct pexor_reg_io)
+#define PEXOR_IOC_READ_REGISTER _IOWR( PEXOR_IOC_MAGIC, 12, \
+ struct pexor_reg_io)
+#define PEXOR_IOC_REQUEST_TOKEN _IOWR( PEXOR_IOC_MAGIC, 13, \
+ struct pexor_token_io)
+#define PEXOR_IOC_WAIT_TOKEN _IOWR( PEXOR_IOC_MAGIC, 14, \
+ struct pexor_token_io)
+#define PEXOR_IOC_WAIT_TRIGGER _IO( PEXOR_IOC_MAGIC, 15)
+#define PEXOR_IOC_SET_TRIXOR _IOR( PEXOR_IOC_MAGIC, 16, \
+ struct pexor_trixor_set)
+#define PEXOR_IOC_TRBNET_REQUEST _IOWR( PEXOR_IOC_MAGIC, 17, \
+ struct pexor_trbnet_io)
+#define PEXOR_IOC_MAXNR 18
+
+struct pexor_reg_io
+{
+ unsigned int address; /* address of a board register, relative to
+ the specified BAR */
+ unsigned int value; /* value for read/write at register address */
+ unsigned char bar; /* the BAR where the register is mapped to
+ PCI access. */
+};
+
#endif
jspc29 / trbnettools.git / commitdiff