change of the calibration clock to a derived clock from the recovered clock via a...

diff --git a/combiner_cts/combiner.prj b/combiner_cts/combiner.prj
index 32fc35fb7e7772084b80ff737eec7bbe1f4e3912..a8a7b83abdd3828e0e25a6bac166f0088417dd71 100644 (file)
--- a/combiner_cts/combiner.prj
+++ b/combiner_cts/combiner.prj
@@ -260,6 +260,7 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in240_out50.vhd"
 
 #TDC Calibration
 add_file -vhdl -lib work "./code_EBR/Calibration.vhd"

diff --git a/combiner_cts/combiner.vhd b/combiner_cts/combiner.vhd
index ca13409a5b6f72a3c90ebd0a36b78988ed87e8d9..e83fb5860014ea76b2acefba052a24122cfb5807 100644 (file)
--- a/combiner_cts/combiner.vhd
+++ b/combiner_cts/combiner.vhd
@@ -252,6 +252,8 @@ architecture arch of combiner is
   signal reset_via_cri_long, reset_via_cri_timer, last_reset_via_cri_long, make_reset : std_logic;
   signal reset_via_cri : std_logic := '0';
   signal last_cri_resetPulse : std_logic;
+  
+  signal clk_cal           : std_logic;
 
   attribute syn_keep of bus_mbs_rx     : signal is true;
   attribute syn_preserve of bus_mbs_rx : signal is true; 
@@ -356,7 +358,18 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler_240
     end if;
     last_reset_via_cri_long <= reset_via_cri_long;
     make_reset <= last_reset_via_cri_long and not reset_via_cri_long;
-  end process;      
+  end process;     
+  
+
+  
+-- generation of TDC calibration clock from recovered clock
+THE_CAL_PLL : entity work.pll_in240_out50
+  port map(
+    CLK   => med2int(INTERFACE_NUM).clk_full,  -- recovered 240MHz clk
+    CLKOP => clk_cal,    -- 50MHz calibration Clock (multiple of 5ns)
+    LOCK  => open
+  );
+  
 ---------------------------------------------------------------------------
 -- TrbNet Uplink
 ---------------------------------------------------------------------------
@@ -1137,7 +1150,7 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
         CLK_READOUT        => clk_sys,    -- Clock for the readout
         REFERENCE_TIME     => cts_trigger_out,  -- Reference time input
         HIT_IN             => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),  -- Channel start signals
-        HIT_CAL_IN         => clk_full_osc,--clk_cal,    -- Hits for calibrating the TDC  --FIXME: here we need a good cal clock!
+        HIT_CAL_IN         => clk_cal,    -- Hits for calibrating the TDC
         -- Trigger signals from handler
         BUSRDO_RX          => cts_rdo_rx,
         BUSRDO_TX          => cts_rdo_additional(INCLUDE_ETM),--_TDCcal