DEFINE PORT GROUP "LED_ADDON_GROUP" "led_addon*";
IOBUF GROUP "LED_ADDON_GROUP" IO_TYPE=LVCMOS25 DRIVE=12;
-LOCATE COMP "hitbus" SITE "J23";
-IOBUF PORT "hitbus" IO_TYPE=LVDS25;
+LOCATE COMP "hitbus" SITE "H24";
+IOBUF PORT "hitbus" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-LOCATE COMP "testpulse" SITE "V6";
+LOCATE COMP "testpulse" SITE "T7";
IOBUF PORT "testpulse" IO_TYPE=LVDS25;
-LOCATE COMP "ctrl_ld" SITE "R1";
-LOCATE COMP "ctrl_rb" SITE "K23";
-LOCATE COMP "ctrl_din" SITE "Y19";
-LOCATE COMP "ctrl_clk1" SITE "AB24";
-LOCATE COMP "ctrl_clk2" SITE "AD24";
+LOCATE COMP "ctrl_ld" SITE "F2";
+LOCATE COMP "ctrl_rb" SITE "K8";
+LOCATE COMP "ctrl_din" SITE "H6";
+LOCATE COMP "ctrl_clk1" SITE "H5";
+LOCATE COMP "ctrl_clk2" SITE "C3";
DEFINE PORT GROUP "CTRL_GROUP" "ctrl*";
IOBUF GROUP "CTRL_GROUP" IO_TYPE=LVDS25;
-LOCATE COMP "ctrl_dout" SITE "W8";
+LOCATE COMP "rd_ldcol" SITE "K23";
+LOCATE COMP "rd_rdcol" SITE "M22";
+LOCATE COMP "rd_ldpix" SITE "AB24";
+LOCATE COMP "rd_pulldown" SITE "N23";
+DEFINE PORT GROUP "READOUT_GROUP" "rd_*";
+IOBUF GROUP "READOUT_GROUP" IO_TYPE=LVDS25;
+
+LOCATE COMP "ctrl_dout" SITE "G26";
IOBUF PORT "ctrl_dout" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-LOCATE COMP "spi_clk" SITE "K3";
-LOCATE COMP "spi_din" SITE "Y5";
-LOCATE COMP "spi_ld_tmp_dac" SITE "AB1";
-LOCATE COMP "spi_ld_adc" SITE "N5";
-LOCATE COMP "spi_ld_thres" SITE "F2";
+LOCATE COMP "spi_clk" SITE "R5";
+LOCATE COMP "spi_din" SITE "J4";
+LOCATE COMP "spi_ld_tmp_dac" SITE "K3";
+LOCATE COMP "spi_ld_adc" SITE "D4";
+LOCATE COMP "spi_ld_thres" SITE "Y5";
DEFINE PORT GROUP "SPI_GROUP" "spi*";
IOBUF GROUP "SPI_GROUP" IO_TYPE=LVDS25;
-LOCATE COMP "spi_dout_adc" SITE "K8";
+LOCATE COMP "spi_dout_adc" SITE "AA1";
IOBUF PORT "spi_dout_adc" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-LOCATE COMP "spi_dout_dac" SITE "H5";
+LOCATE COMP "spi_dout_dac" SITE "P4";
IOBUF PORT "spi_dout_dac" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-LOCATE COMP "spi_dac4_dout" SITE "G26";
+LOCATE COMP "spi_dac4_dout" SITE "J23";
IOBUF PORT "spi_dac4_dout" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-LOCATE COMP "syncres" SITE "D1";
+LOCATE COMP "syncres" SITE "K19";
IOBUF PORT "syncres" IO_TYPE=LVDS25;
-LOCATE COMP "clkref" SITE "T7";
+LOCATE COMP "clkref" SITE "Y19";
IOBUF PORT "clkref" IO_TYPE=LVDS25;
-LOCATE COMP "clkext" SITE "H6";
+LOCATE COMP "clkext" SITE "AD24";
IOBUF PORT "clkext" IO_TYPE=LVDS25;
###########################################################
ctrl_clk2 : out std_logic; --slow control clk2
ctrl_ld : out std_logic; --slow control load latched data
ctrl_dout : in std_logic; --serial data from mupix
- ctrl_rb : out std_logic; --slow control readback??
+ ctrl_rb : out std_logic; --slow control readback
spi_dout_adc : in std_logic; --adc serial data from board
spi_dout_dac : in std_logic; --dac serial data from board
dac4_dout : in std_logic; --serial data in from threshold dac
spi_ld_thres : out std_logic; --load threshold and injection dac
hitbus : in std_logic; --hitbus signal
+ --connections to data fifos
+ --fifo_rden : out std_logic_vector(3 downto 0); -- read enable to mupix data FIFOs
+ --fifo_empty : in std_logic_vector(3 downto 0); -- mupix data FIFO empty flags
+ --fifo_full : in std_logic_vector(3 downto 0); -- mupix data FIFO full flags
+ --fifo_data : in std_logic_vector(127 downto 0); -- mupix readout data from FIFOs
+
--resets
timestampreset_in : in std_logic; --time stamp reset
eventcounterreset_in : in std_logic; --event number reset
signal hit_sync : std_logic;
signal testpulse_i : std_logic;
- signal spi_clk_i : std_logic;
- signal spi_din_i : std_logic;
- signal spi_ld_tmp_dac_i : std_logic;
- signal spi_cs_adc_i : std_logic;
- signal spi_ld_thres_i : std_logic;
+ signal spi_clk_i : std_logic;
+ signal spi_din_i : std_logic;
+ signal spi_ld_tmp_dac_i : std_logic;
+ signal spi_cs_adc_i : std_logic;
+ signal spi_ld_thres_i : std_logic;
component HitbusHistogram
generic(
reset : in std_logic; --reset
--mupix control
mupixslctrl : out MupixSlowControl;
- ctrl_dout : in std_logic; --serial data from mupix
+ ctrl_dout : in std_logic; --serial data from mupix
--TRB slow control
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1)
);
- --need to invert signals due to addon board layout
- ctrl_din <= not mupixslctrl_i.sin;
- ctrl_clk1 <= not mupixslctrl_i.clk1;
- ctrl_clk2 <= not mupixslctrl_i.clk2;
- ctrl_ld <= not mupixslctrl_i.load;
+ ctrl_din <= mupixslctrl_i.sin;
+ ctrl_clk1 <= mupixslctrl_i.clk1;
+ ctrl_clk2 <= mupixslctrl_i.clk2;
+ ctrl_ld <= mupixslctrl_i.load;
+ ctrl_rb <= mupixslctrl_i.rb;
boardcontrol_1 : component MupixBoardDAC
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2)
);
- --need to invert signals due to addon board layout
- spi_clk <= not spi_clk_i;
- spi_din <= not spi_din_i;
- spi_ld_tmp_dac <= not spi_ld_tmp_dac_i;
- spi_ld_thres <= not spi_ld_thres_i;
- spi_cs_adc <= not spi_cs_adc_i;
- testpulse <= not testpulse_i;
+ testpulse <= testpulse_i;
+
+ spi_output_pipe : process (clk) is
+ begin
+ if rising_edge(clk) then
+ if reset = '1' then
+ spi_clk <= '0';
+ spi_din <= '0';
+ spi_ld_tmp_dac <= '0';
+ spi_ld_thres <= '0';
+ spi_cs_adc <= '1';
+ else
+ spi_clk <= spi_clk_i;
+ spi_din <= spi_din_i;
+ spi_ld_tmp_dac <= spi_ld_tmp_dac_i;
+ spi_ld_thres <= spi_ld_thres_i;
+ spi_cs_adc <= spi_cs_adc_i;
+ end if;
+ end if;
+ end process spi_output_pipe;
+
+
end Behavioral;
clk : in std_logic;
pulse_length : in std_logic_vector(31 downto 0);
pulse_pause : in std_logic_vector(31 downto 0);
+ pulse_number : in std_logic_vector(31 downto 0);
pulse_start : in std_logic;
pulse_o : out std_logic
);
end component injection_generator;
- constant c_bits_threshold_dacs : integer := 64;--4*16 bit of the four DACs
- signal start_write_threshold : std_logic := '0';
- signal spi_data_in_threshold : std_logic_vector(c_bits_threshold_dacs - 1 downto 0);
+ constant c_bits_threshold_dacs : integer := 64; --4*16 bit of the four DACs
+ signal start_write_threshold : std_logic := '0';
+ signal spi_data_in_threshold : std_logic_vector(c_bits_threshold_dacs - 1 downto 0);
signal spi_data_to_chip_threshold : std_logic;
- signal spi_data_out_threshold : std_logic_vector(c_bits_threshold_dacs - 1 downto 0);
- signal spi_clk_threshold : std_logic;
-
- constant c_bits_temperature_dac : integer := 16;
- signal start_write_temperature : std_logic := '0';
- signal spi_data_in_temperature : std_logic_vector(c_bits_temperature_dac - 1 downto 0);
- signal spi_data_to_chip_temperature : std_logic;
- signal spi_data_out_temperature : std_logic_vector(c_bits_temperature_dac - 1 downto 0);
+ signal spi_data_out_threshold : std_logic_vector(c_bits_threshold_dacs - 1 downto 0);
+ signal spi_clk_threshold : std_logic;
+
+ constant c_bits_temperature_dac : integer := 16;
+ signal start_write_temperature : std_logic := '0';
+ signal spi_data_in_temperature : std_logic_vector(c_bits_temperature_dac - 1 downto 0);
+ signal spi_data_to_chip_temperature : std_logic;
+ signal spi_data_out_temperature : std_logic_vector(c_bits_temperature_dac - 1 downto 0);
signal spi_clk_temperature_temperature : std_logic;
-
- signal start_write_adc : std_logic := '0';
- signal config_adc : std_logic_vector(15 downto 0);
+
+ signal start_write_adc : std_logic := '0';
+ signal config_adc : std_logic_vector(15 downto 0);
signal spi_data_to_chip_adc : std_logic;
- signal spi_data_out_adc : std_logic_vector(31 downto 0);
- signal spi_clk_adc : std_logic;
-
- signal pulse_start_i : std_logic := '0';
- signal pulse_length_i, pulse_pause_i : std_logic_vector(31 downto 0) := (others => '0');
+ signal spi_data_out_adc : std_logic_vector(31 downto 0);
+ signal spi_clk_adc : std_logic;
+
+ signal pulse_start_i : std_logic := '0';
+ signal pulse_length_i : std_logic_vector(31 downto 0) := (others => '0');
+ signal pulse_pause_i : std_logic_vector(31 downto 0) := (others => '0');
+ signal number_pulses_i : std_logic_vector(31 downto 0) := (others => '0');
begin
clk => clk,
pulse_length => pulse_length_i,
pulse_pause => pulse_pause_i,
+ pulse_number => number_pulses_i,
pulse_start => pulse_start_i,
pulse_o => injection_pulse
);
--0x0099: injection length
--0x009a: injection pause
--0x009b: start injection pulse
+ --0x009c: number of injection pulses
-----------------------------------------------------------------------------
SLV_BUS_HANDLER : process(clk)
begin -- process SLV_BUS_HANDLER
when x"009a" =>
SLV_DATA_OUT(31 downto 0) <= pulse_pause_i;
SLV_ACK_OUT <= '1';
+ when x"009c" =>
+ SLV_DATA_OUT(31 downto 0) <= number_pulses_i;
+ SLV_ACK_OUT <= '1';
when others =>
SLV_UNKNOWN_ADDR_OUT <= '1';
end case;
when x"009b" =>
pulse_start_i <= '1';
SLV_ACK_OUT <= '1';
+ when x"009c" =>
+ number_pulses_i <= SLV_DATA_IN(31 downto 0);
+ SLV_ACK_OUT <= '1';
when others =>
SLV_UNKNOWN_ADDR_OUT <= '1';
end case;
architecture rtl of MupixBoardInterface is
- signal spi_dout_adc_i : std_logic;
- signal spi_dout_dac_i : std_logic;
- signal dac4_dout_i : std_logic;
- signal hitbus_i : std_logic;
-
component InputSynchronizer
generic(depth : integer);
port(
sync_spi_dout_adc : component InputSynchronizer
generic map(depth => 2)
- port map(clk_in, reset, spi_dout_adc, spi_dout_adc_i);
+ port map(clk_in, reset, spi_dout_adc, spi_dout_adc_sync);
sync_spi_dout_dac : component InputSynchronizer
generic map(depth => 2)
- port map(clk_in, reset, spi_dout_dac, spi_dout_dac_i);
+ port map(clk_in, reset, spi_dout_dac, spi_dout_dac_sync);
sync_dac4_dout : component InputSynchronizer
generic map(depth => 2)
- port map(clk_in, reset, dac4_dout, dac4_dout_i);
+ port map(clk_in, reset, dac4_dout, dac4_dout_sync);
sync_hitbus : component InputSynchronizer
generic map(depth => 2)
- port map(clk_in, reset, hitbus, hitbus_i);
+ port map(clk_in, reset, hitbus, hitbus_sync);
sync_trigger : component InputSynchronizer
generic map(depth => 2)
generic map(depth => 2)
port map(fast_clk_in, reset, trigger, trigger_sync_fast);
- --need to invert some input signals due to addon board layout
- spi_dout_adc_sync <= not spi_dout_adc_i;
- spi_dout_dac_sync <= not spi_dout_dac_i;
- dac4_dout_sync <= not dac4_dout_i;
- hitbus_sync <= not hitbus_i;
-
-
end architecture rtl;
SLV_ACK_OUT <= '1';
when x"0108" =>
SLV_DATA_OUT(g_cyc_mem_address_width downto 0) <= cycl_fillcnt;
- SLV_DATA_OUT(g_cyc_mem_address_width + 1) <= cycl_empty;
- SLV_DATA_OUT(g_cyc_mem_address_width + 2) <= cycl_full;
+ SLV_DATA_OUT(31) <= cycl_empty;
+ SLV_DATA_OUT(30) <= cycl_full;
SLV_ACK_OUT <= '1';
when x"0109" =>
SLV_DATA_OUT <= cycl_inword_freq;
mupix_ctrcl_select <= SLV_DATA_IN(4);
reset_crc_to_mupix_ext <= SLV_DATA_IN(5);
reset_crc_from_mupix_ext <= SLV_DATA_IN(6);
+ mupix_ctrl_ext.rb <= SLV_DATA_IN(7);
bitstosend <= unsigned(SLV_DATA_IN(31 downto 16));
SLV_ACK_OUT <= '1';
when others =>
SLV_DATA_OUT(4) <= mupix_ctrcl_select;
SLV_DATA_OUT(5) <= reset_crc_to_mupix_ext;
SLV_DATA_OUT(6) <= reset_crc_from_mupix_ext;
+ SLV_DATA_OUT(7) <= mupix_ctrl_ext.rb;
SLV_DATA_OUT(31 downto 16) <= std_logic_vector(bitstosend);
SLV_ACK_OUT <= '1';
when others =>
end process output_pipe;
--matching to outputs
- mupixslctrl <= mupix_ctrl_reg;
+ mupixslctrl <= mupix_ctrl_reg;
end Behavioral;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-library work;
---use work.trb_net_std.all;
---use work.trb_net_components.all;
---use work.trb3_components.all;
---use work.version.all;
-
entity resethandler is
port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- TimestampReset_OUT : out std_logic;
- EventCounterReset_OUT : out std_logic;
+ CLK_IN : in std_logic; -- system clock
+ RESET_IN : in std_logic; -- reset input
+ timestampreset_out : out std_logic; -- reset FPGA timestamps
+ eventcounterreset_out : out std_logic; -- reset FPGA event counters
+ mupixdata_reset_out : out std_logic; -- reset data structures holding mupix data
-- Slave bus
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
signal timestampreset_i : std_logic := '0';
signal eventcounterreset_i : std_logic := '0';
+ signal mupixdata_reset_i : std_logic := '0';
signal timestampreset_edge : std_logic_vector(1 downto 0) := (others => '0');
signal eventcounterreset_edge : std_logic_vector(1 downto 0) := (others => '0');
+ signal mupixdatareset_edge : std_logic_vector(1 downto 0) := (others => '0');
begin -- architecture behavioral
- timestamp_edge_detect : process (CLK_IN) is
- begin -- process timestamp_edge_detect
- if rising_edge(CLK_IN) then
- timestampreset_edge <= timestampreset_edge(0) & timestampreset_i;
- if timestampreset_edge = "01" then
- TimestampReset_OUT <= '1';
- else
- TimestampReset_OUT <= '0';
- end if;
- end if;
- end process timestamp_edge_detect;
+ timestamp_edge_detect : process(CLK_IN) is
+ begin -- process timestamp_edge_detect
+ if rising_edge(CLK_IN) then
+ if reset_in = '1' then
+ timestampreset_edge <= (others => '0');
+ timestampreset_out <= '0';
+ else
+ timestampreset_edge <= timestampreset_edge(0) & timestampreset_i;
+ if timestampreset_edge = "01" then
+ timestampreset_out <= '1';
+ else
+ timestampreset_out <= '0';
+ end if;
+ end if;
+ end if;
+ end process timestamp_edge_detect;
- eventcounter_edge_detect : process (CLK_IN) is
- begin -- process eventcounter_edge_detect
- if rising_edge(CLK_IN) then
- eventcounterreset_edge <= eventcounterreset_edge(0) & eventcounterreset_i;
- if eventcounterreset_edge = "01" then
- EventCounterReset_OUT <= '1';
- else
- EventCounterReset_OUT <= '0';
- end if;
- end if;
- end process eventcounter_edge_detect;
+ eventcounter_edge_detect : process(CLK_IN) is
+ begin -- process eventcounter_edge_detect
+ if rising_edge(CLK_IN) then
+ if reset_in = '1' then
+ eventcounterreset_edge <= (others => '0');
+ eventcounterreset_out <= '0';
+ else
+ eventcounterreset_edge <= eventcounterreset_edge(0) & eventcounterreset_i;
+ if eventcounterreset_edge = "01" then
+ eventcounterreset_out <= '1';
+ else
+ eventcounterreset_out <= '0';
+ end if;
+ end if;
+ end if;
+ end process eventcounter_edge_detect;
+
+ data_struct_reset : process (CLK_IN) is
+ begin
+ if rising_edge(CLK_IN) then
+ if reset_in = '1' then
+ mupixdatareset_edge <= (others => '0');
+ mupixdata_reset_out <= '0';
+ else
+ mupixdatareset_edge <= mupixdatareset_edge(0) & mupixdata_reset_i;
+ if mupixdatareset_edge = "01" then
+ mupixdata_reset_out <= '1';
+ else
+ mupixdata_reset_out <= '0';
+ end if;
+ end if;
+ end if;
+ end process data_struct_reset;
+
------------------------------------------------------------
- --TRB SLV-BUS Hanlder
- ------------------------------------------------------------
- --0x0001: reset timestamps
- --0x0002: reset eventcounter
- slv_bus_handler : process (CLK_IN) is
- begin -- process slv_bus_handler
- if rising_edge(CLK_IN) then
- slv_data_out <= (others => '0');
- slv_ack_out <= '0';
- slv_no_more_data_out <= '0';
- slv_unknown_addr_out <= '0';
+ --TRB SLV-BUS Hanlder
+ ------------------------------------------------------------
+ --0x0001: reset timestamps
+ --0x0002: reset eventcounter
+ --0x0003: reset data structures
+ slv_bus_handler : process(CLK_IN) is
+ begin -- process slv_bus_handler
+ if rising_edge(CLK_IN) then
+ slv_data_out <= (others => '0');
+ slv_ack_out <= '0';
+ slv_no_more_data_out <= '0';
+ slv_unknown_addr_out <= '0';
- if SLV_WRITE_IN = '1' then
- case SLV_ADDR_IN is
- when x"0001" =>
- timestampreset_i <= SLV_DATA_IN(0);
- slv_ack_out <= '1';
- when x"0002" =>
- eventcounterreset_i <= SLV_DATA_IN(0);
- slv_ack_out <= '1';
- when others =>
- slv_unknown_addr_out <= '1';
- end case;
- end if;
+ if SLV_WRITE_IN = '1' then
+ case SLV_ADDR_IN is
+ when x"0001" =>
+ timestampreset_i <= SLV_DATA_IN(0);
+ slv_ack_out <= '1';
+ when x"0002" =>
+ eventcounterreset_i <= SLV_DATA_IN(0);
+ slv_ack_out <= '1';
+ when x"0003" =>
+ mupixdata_reset_i <= SLV_DATA_IN(0);
+ slv_ack_out <= '1';
+ when others =>
+ slv_unknown_addr_out <= '1';
+ end case;
+ end if;
- if SLV_READ_IN = '1' then
- case SLV_ADDR_IN is
- when x"0001" =>
- slv_data_out(0) <= timestampreset_i;
- slv_ack_out <= '1';
- when x"0002" =>
- slv_data_out(0) <= eventcounterreset_i;
- slv_ack_out <= '1';
- when others =>
- slv_unknown_addr_out <= '1';
- end case;
- end if;
- end if;
- end process slv_bus_handler;
+ if SLV_READ_IN = '1' then
+ case SLV_ADDR_IN is
+ when x"0001" =>
+ slv_data_out(0) <= timestampreset_i;
+ slv_ack_out <= '1';
+ when x"0002" =>
+ slv_data_out(0) <= eventcounterreset_i;
+ slv_ack_out <= '1';
+ when x"0003" =>
+ slv_data_out(0) <= mupixdata_reset_i;
+ slv_ack_out <= '1';
+ when others =>
+ slv_unknown_addr_out <= '1';
+ end case;
+ end if;
+ end if;
+ end process slv_bus_handler;
end architecture behavioral;
clk1 : std_logic;
clk2 : std_logic;
load : std_logic;
+ rb : std_logic;
end record MupixSlowControl;
- constant c_mupix_slctrl_init : MupixSlowControl := ('0', '0', '0', '0');
+ constant c_mupix_slctrl_init : MupixSlowControl := ('0', '0', '0', '0', '0');
type t_counter_array is array(integer range <>) of unsigned(31 downto 0);
clk : in std_logic;--! clock input
pulse_length : in std_logic_vector(31 downto 0); --! length of injection pulse
pulse_pause : in std_logic_vector(31 downto 0); --! pause between pulses
+ pulse_number : in std_logic_vector(31 downto 0); --! number of pulses to send (adds one additional pulse)
pulse_start : in std_logic;--! start generation of pulse
pulse_o : out std_logic --! output signal to mupix board
);
architecture rtl of injection_generator is
type injection_generator_type is (idle, gen, pause);
- signal injection_generator_fsm : injection_generator_type := idle;
- signal length_counter, pause_counter : unsigned(31 downto 0) := (others => '0');
+ signal pulse_i : std_logic;
+ signal injection_generator_fsm : injection_generator_type := idle;
+ signal length_counter : unsigned(31 downto 0) := (others => '0');
+ signal pause_counter : unsigned(31 downto 0) := (others => '0');
+ signal pulse_counter : unsigned(31 downto 0) := (others => '0');
begin
length_counter <= (others => '0');
pause_counter <= (others => '0');
injection_generator_fsm <= idle;
- pulse_o <= '0';
+ pulse_i <= '0';
else
case injection_generator_fsm is
when idle =>
- pulse_o <= '0';
+ pulse_i <= '0';
length_counter <= (others => '0');
- if pulse_start = '1' then
+ pulse_counter <= (others => '0');
+ if pulse_start = '1' and unsigned(pulse_length) > 0 then
injection_generator_fsm <= gen;
else
injection_generator_fsm <= idle;
end if;
when gen =>
- pulse_o <= '1';
+ pulse_i <= '1';
+ pause_counter <= (others => '0');
length_counter <= length_counter + 1;
- if length_counter = unsigned(pulse_length) - 1 then
- injection_generator_fsm <= pause;
- pause_counter <= (others => '0');
- else
- injection_generator_fsm <= gen;
+ if unsigned(pulse_length) > 0 then
+ if length_counter < unsigned(pulse_length) - 1 then
+ injection_generator_fsm <= gen;
+ else
+ injection_generator_fsm <= pause;
+ end if;
+ else
+ injection_generator_fsm <= idle;
end if;
when pause =>
- pulse_o <= '0';
- if pulse_pause /= x"0000" then
- if pause_counter = unsigned(pulse_pause) - 1 then
- injection_generator_fsm <= gen;
- length_counter <= (others => '0');
+ pulse_i <= '0';
+ length_counter <= (others => '0');
+ pause_counter <= pause_counter + 1;
+ if unsigned(pulse_pause) > 0 then
+ if pause_counter < unsigned(pulse_pause) - 1 then
+ injection_generator_fsm <= pause;
else
- pause_counter <= pause_counter + 1;
+ if unsigned(pulse_number) > 0 then
+ if pulse_counter < unsigned(pulse_number) then
+ pulse_counter <= pulse_counter + 1;
+ injection_generator_fsm <= gen;
+ else
+ injection_generator_fsm <= idle;
+ end if;
+ else
+ injection_generator_fsm <= gen;
+ end if;
end if;
else
injection_generator_fsm <= idle;
end if;
end process injection_gen;
+ output_pipe : process (clk) is
+ begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ pulse_o <= '0';
+ else
+ pulse_o <= pulse_i;
+ end if;
+ end if;
+ end process output_pipe;
+
end rtl;
wait for 100 ns;
--test injection pulse
--single pulse, no pause
- TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00500000", x"0099", c_clk_period);
+ TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"0000000a", x"0099", c_clk_period);
+ TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000001", x"009b", c_clk_period);
wait for 100*c_clk_period;
--several pulse, 20 clk periods pause
- TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"000A0014", x"0099", c_clk_period);
- wait for 400*c_clk_period;
- TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000", x"0099", c_clk_period);
+ TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"0000000b", x"0099", c_clk_period);
+ TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"0000000a", x"009a", c_clk_period);
+ TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000001", x"009b", c_clk_period);
+ TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000002", x"009c", c_clk_period);
+ wait for 100*c_clk_period;
+ TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000", x"009a", c_clk_period);
--write to threshold DACs (2x to test readback)
TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"AAAABBBB", x"0090", c_clk_period);
TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"CCCCDDDD", x"0091", c_clk_period);
CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
SERDES_INT_TX : out std_logic_vector(3 downto 0);
SERDES_INT_RX : in std_logic_vector(3 downto 0);
- SERDES_ADDON_TX : out std_logic_vector(11 downto 0);
- SERDES_ADDON_RX : in std_logic_vector(11 downto 0);
+ --SERDES_ADDON_TX : out std_logic_vector(11 downto 0);
+ --SERDES_ADDON_RX : in std_logic_vector(11 downto 0);
+ mupix_serdes_rx : in std_logic_vector(7 downto 0);
--Inter-FPGA Communication
FPGA5_COMM : inout std_logic_vector(11 downto 0);
--Bit 0/1 input, serial link RX active
spi_ld_adc : out std_logic; --load adc
spi_dac4_dout : in std_logic; --serial data in from dac 4
hitbus : in std_logic; --hitbus
+ --classic state machine signals (currently unused)
+ rd_ldcol : out std_logic;
+ rd_rdcol : out std_logic;
+ rd_ldpix : out std_logic;
+ rd_pulldown : out std_logic;
-- fast signals
clkext : out std_logic;
clkref : out std_logic;
ctrl_rb : out std_logic; --slow control readback??
spi_dout_adc : in std_logic; --adc serial data from board
spi_dout_dac : in std_logic; --dac serial data from board
- dac4_dout : in std_logic; --serial data in from threshold dac
+ dac4_dout : in std_logic; --serial data in from threshold dac
spi_clk : out std_logic; --serial clock
spi_din : out std_logic; --serial data out
spi_ld_tmp_dac : out std_logic; --load temperature dac
spi_ld_thres : out std_logic; --load threshold and injection dac
hitbus : in std_logic; --hitbus signal
+ --connections to data fifos
+ --fifo_rden : out std_logic_vector(3 downto 0);
+ --fifo_empty : in std_logic_vector(3 downto 0);
+ --fifo_full : in std_logic_vector(3 downto 0);
+ --fifo_data : in std_logic_vector(127 downto 0);
+
--resets
timestampreset_in : in std_logic; --time stamp reset
eventcounterreset_in : in std_logic; --event number reset
SLV_NO_MORE_DATA_OUT : out std_logic;
SLV_UNKNOWN_ADDR_OUT : out std_logic);
end component resethandler;
+
+ -- component MupixDataLink is
+ -- port(
+ -- sysclk : in std_logic;
+ -- dataclk : in std_logic;
+ -- rst : in std_logic;
+ -- clear : in std_logic;
+ -- rst_fifo : in std_logic;
+ -- mupix_data : in std_logic_vector(7 downto 0);
+ -- refclk2core : out std_logic;
+ -- clk_rx_half_out : out std_logic;
+ -- clk_rx_full_out : out std_logic;
+ -- fifo_rden : in std_logic_vector(3 downto 0);
+ -- fifo_empty : out std_logic_vector(3 downto 0);
+ -- fifo_full : out std_logic_vector(3 downto 0);
+ -- fifo_data : out std_logic_vector(127 downto 0);
+ -- channel_status_led : out std_logic_vector(3 downto 0));
+ -- end component MupixDataLink;
component pll_mupix_main
port (CLK: in std_logic;
--common reset signals for mupix frontends
signal reset_timestamps_i : std_logic;
signal reset_eventcounters_i : std_logic;
+ signal reset_mupixdata_i : std_logic;
signal resethandler_regio_addr_in_0 : std_logic_vector (15 downto 0);
signal resethandler_regio_data_in_0 : std_logic_vector (31 downto 0);
signal resethandler_regio_data_out_0 : std_logic_vector (31 downto 0);
signal resethandler_regio_no_more_data_out_0 : std_logic;
signal resethandler_regio_unknown_addr_out_0 : std_logic;
+ --connections between mupix data fifos and mupix board
+ signal fifo_rden_i : std_logic_vector(3 downto 0);
+ signal fifo_empty_i : std_logic_vector(3 downto 0);
+ signal fifo_full_i : std_logic_vector(3 downto 0);
+ signal fifo_data_i : std_logic_vector(127 downto 0);
+
--dummy
- signal dummy_counter : integer range 0 to 7 := 0;
+ signal dummy_counter : integer range 0 to 8 := 0;
signal mupix_clk_i : std_logic;
begin
- --tie not connected outputs to 0
- --not_connected(25 downto 18) <= (others => '0');
- --not_connected(16 downto 0) <= (others => '0');
- led_addon <= (others => '0');
+ rd_ldcol <= '0';
+ rd_rdcol <= '0';
+ rd_ldpix <= '0';
+ rd_pulldown <= '0';
+
---------------------------------------------------------------------------
-- Reset Generation
---------------------------------------------------------------------------
timestampreset_in => reset_timestamps_i,
eventcounterreset_in => reset_eventcounters_i,
+ -- fifo_rden => fifo_rden_i,
+ -- fifo_empty => fifo_empty_i,
+ -- fifo_full => fifo_full_i,
+ -- fifo_data => fifo_data_i,
+
--slow control signals
testpulse => testpulse,
ctrl_din => ctrl_din,
REGIO_WRITE_ACK_OUT => mu_regio_write_ack_out_0,
REGIO_NO_MORE_DATA_OUT => mu_regio_no_more_data_out_0,
REGIO_UNKNOWN_ADDR_OUT => mu_regio_unknown_addr_out_0);
+
+
+ -- mupix_data_link_1 : entity work.MupixDataLink
+ -- port map(
+ -- sysclk => clk_100_i,
+ -- dataclk => mupix_clk_i,
+ -- rst => reset_i,
+ -- clear => clear_i,
+ -- rst_fifo => reset_mupixdata_i,
+ -- mupix_data => mupix_serdes_rx,
+ -- refclk2core => open,
+ -- clk_rx_half_out => open,
+ -- clk_rx_full_out => open,
+ -- fifo_rden => fifo_rden_i,
+ -- fifo_empty => fifo_empty_i,
+ -- fifo_full => fifo_full_i,
+ -- fifo_data => fifo_data_i,
+ -- --misc
+ -- channel_status_led => led_addon);
+
+ led_addon <= (others => '1');
resethandler_1 : entity work.resethandler
port map (
RESET_IN => reset_i,
TimestampReset_OUT => reset_timestamps_i,
EventCounterReset_OUT => reset_eventcounters_i,
+ mupixdata_reset_out => reset_mupixdata_i,
SLV_READ_IN => resethandler_regio_read_enable_in_0,
SLV_WRITE_IN => resethandler_regio_write_enable_in_0,
SLV_DATA_OUT => resethandler_regio_data_out_0,
dummy_proc : process(clk_100_i)
begin
if rising_edge(clk_100_i) then
- if reset_i = '0' then
- dummy_counter <= 0;
- else
- syncres <= '0';
- dummy_counter <= dummy_counter + 1;
- if dummy_counter = 7 then
- syncres <= '1';
- dummy_counter <= 0;
- end if;
- end if;
+ if dummy_counter = 7 then
+ syncres <= not syncres;
+ dummy_counter <= 0;
+ else
+ syncres <= syncres;
+ dummy_counter <= dummy_counter + 1;
+ end if;
end if;
end process dummy_proc;
jspc29 / trb3.git / commitdiff